JPH0743018U - Board noise pattern structure - Google Patents

Board noise pattern structure

Info

Publication number
JPH0743018U
JPH0743018U JP7518193U JP7518193U JPH0743018U JP H0743018 U JPH0743018 U JP H0743018U JP 7518193 U JP7518193 U JP 7518193U JP 7518193 U JP7518193 U JP 7518193U JP H0743018 U JPH0743018 U JP H0743018U
Authority
JP
Japan
Prior art keywords
pattern
substrate
back surface
noise countermeasure
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7518193U
Other languages
Japanese (ja)
Other versions
JP2599674Y2 (en
Inventor
一明 田中
重夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsuba Corp
Original Assignee
Mitsuba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsuba Corp filed Critical Mitsuba Corp
Priority to JP1993075181U priority Critical patent/JP2599674Y2/en
Publication of JPH0743018U publication Critical patent/JPH0743018U/en
Application granted granted Critical
Publication of JP2599674Y2 publication Critical patent/JP2599674Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Structure Of Printed Boards (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

(57)【要約】 【目的】 表面に配線パターンを形成された基板の裏面
にノイズ対策用パターンを形成した際の基板の反りを防
止する。 【構成】 基板1をガラスエポキシ材により形成し、そ
の表面1aに銅からなるパターン材により配線パターン
2を形成し、基板1の裏面1bに、配線パターン2と約
同面積であって、基板1の裏面全面へのリフロー時に反
り易い方向について間隔を開けた縞模様状にノイズ対策
用パターン3を形成する。 【効果】 表裏両面のパターン面積を約同等としたこと
から、リフロー時の熱ストレスで反りが生じることを防
止し得る。
(57) [Abstract] [Purpose] To prevent the warp of the board when the noise countermeasure pattern is formed on the back surface of the board on which the wiring pattern is formed. [Structure] A substrate 1 is formed of a glass epoxy material, and a wiring pattern 2 is formed on a front surface 1a of the pattern material made of copper. The noise countermeasure pattern 3 is formed in a striped pattern with an interval in the direction in which it is likely to warp during reflow over the entire back surface of. [Effect] Since the pattern areas on the front and back sides are made approximately equal, it is possible to prevent warpage due to thermal stress during reflow.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、基板のノイズ対策用パターン構造に関し、特に、表面に配線パター ンを形成された基板の裏面にノイズ対策用パターンを形成した基板のノイズ対策 用パターン構造に関する。 The present invention relates to a noise countermeasure pattern structure of a substrate, and more particularly to a noise countermeasure pattern structure of a substrate having a wiring pattern formed on the front surface and a noise countermeasure pattern formed on the back surface of the substrate.

【0002】[0002]

【従来の技術】[Prior art]

従来、ハイブリッドICなどに於いて、セラミックスなどからなる基板上に所 望の配線パターンを形成したものでは、外部からのノイズ対策として基板の裏面 全面にパターン材をリフローしてノイズ対策用パターンを形成したものがある。 一方、軽量化のために、基板をガラスエポキシ材などの合成樹脂材により形成し たものがある。 Conventionally, in a hybrid IC, etc., where a desired wiring pattern is formed on a substrate made of ceramics etc., as a countermeasure against external noise, a pattern material is reflowed over the entire back surface of the substrate to form a noise countermeasure pattern. There is something I did. On the other hand, in order to reduce the weight, there is one in which the substrate is made of a synthetic resin material such as a glass epoxy material.

【0003】 しかしながら、上記合成樹脂基板に於いて、配線パターンの面積よりもノイズ 対策用パターンの面積が比較的広い場合には、例えば銅のパターン材と基板との 膨張・収縮率が異なるため、リフロー時などの熱ストレスにより、基板に大きな 反りが生じるという問題があった。However, in the above-mentioned synthetic resin substrate, when the area of the noise countermeasure pattern is relatively larger than the area of the wiring pattern, for example, the expansion / shrinkage rate of the copper pattern material and the substrate are different, There was a problem that the substrate was greatly warped due to thermal stress during reflow.

【0004】[0004]

【考案が解決しようとする課題】[Problems to be solved by the device]

このような従来技術の問題点に鑑み、本考案の主な目的は、基板の反りを防止 し得る基板のノイズ対策用パターン構造を提供することにある。 In view of the above problems of the prior art, a main object of the present invention is to provide a pattern structure for noise suppression of a substrate, which can prevent the warp of the substrate.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

このような目的は、本考案によれば、表面に配線パターンを形成された基板の 裏面に形成したノイズ対策用パターンが、前記配線パターンと約同面積にて形成 されていることを特徴とする基板のノイズ対策用パターン構造を提供することに より達成される。特に、前記ノイズ対策用パターンが、前記裏面の全面に形成し た場合に於ける反り易い方向に間隔を開けた縞模様状に形成されていると良い。 According to the present invention, such an object is characterized in that the noise countermeasure pattern formed on the back surface of the substrate having the wiring pattern formed on the front surface is formed in approximately the same area as the wiring pattern. This is achieved by providing a pattern structure for noise suppression of the substrate. Particularly, it is preferable that the noise countermeasure pattern is formed in a striped pattern with an interval in the direction in which it easily warps when formed on the entire back surface.

【0006】[0006]

【作用】[Action]

このように、基板の表面と裏面とにそれぞれ約同面積のパターン材を形成する ことにより、基板の表裏各面に対するパターン材による熱膨張・収縮の影響をほ ぼ等しくすることができる。特に、基板裏面全面にパターン材を形成した際に反 り易い方向に間隔を開けた縞模様状にパターン形成することにより、ノイズ対策 用パターンによる熱膨張・収縮の影響を軽減できる。 By thus forming the pattern material having approximately the same area on the front surface and the back surface of the substrate, the effects of thermal expansion and contraction of the pattern material on the front and back surfaces of the substrate can be made substantially equal. In particular, when the pattern material is formed on the entire back surface of the substrate, the pattern is formed in a striped pattern with intervals in the direction in which the pattern material is easily warped, so that the effect of thermal expansion and contraction due to the noise countermeasure pattern can be reduced.

【0007】[0007]

【実施例】【Example】

以下、本考案の好適実施例を添付の図面を参照して詳しく説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

【0008】 図1は、本考案が適用された例えばハイブリッドICの基板1の平面図であり 、(a)は基板1の表面1aを示し、(b)は基板1の裏面1bを示す。FIG. 1 is a plan view of a substrate 1 of, for example, a hybrid IC to which the present invention is applied. (A) shows a front surface 1a of the substrate 1 and (b) shows a back surface 1b of the substrate 1.

【0009】 基板1の表面1aには、導体膜・抵抗体膜などからなる配線パターン2が、例 えば銅からなるパターン材により形成されている。この配線パターン2には、チ ップなどが載置される電極部領域が形成されている。A wiring pattern 2 made of a conductor film, a resistor film, etc. is formed on the surface 1 a of the substrate 1 by a pattern material made of copper, for example. The wiring pattern 2 has an electrode portion region on which a chip or the like is placed.

【0010】 基板の裏面1bには、ノイズ対策用パターン3が、配線パターン2と同じパタ ーン材を用いて形成されている。このノイズ対策用パターン3は、配線パターン 2を形成後の工程でリフローにより形成されるが、配線パターン2と約同量のパ ターン材を用いて、図に於ける縦縞模様状に形成されている。On the back surface 1b of the substrate, a noise countermeasure pattern 3 is formed by using the same pattern material as the wiring pattern 2. The noise countermeasure pattern 3 is formed by reflow in the step after the wiring pattern 2 is formed, but is formed in a vertical striped pattern in the figure by using a pattern material in the same amount as that of the wiring pattern 2. There is.

【0011】 なお、基板1がガラスエポキシ材などの合成樹脂材により形成されており、裏 面1bの全面にパターンを形成した場合には、基板1とパターン材との熱膨張・ 収縮率が大きく異なることから、実施例では図に於ける長手方向を湾曲させるよ うに反り易くなる。When the substrate 1 is made of a synthetic resin material such as a glass epoxy material and a pattern is formed on the entire back surface 1b, the coefficient of thermal expansion / contraction between the substrate 1 and the pattern material is large. Because of the difference, in the embodiment, the warp tends to occur by bending the longitudinal direction in the drawing.

【0012】 本基板1では、ノイズ対策用パターン3が、各縞を上記長手方向に間隔を開け るようにされており、反り易い方向についてのノイズ対策用パターン3の面積の 割合を小さくすることができる。また、裏面1b全体のパターンの面積を表面1 aと約同じにしており、ノイズ対策用パターン3のリフロー時などに於いて基板 1とパターン材との熱膨張・収縮率の違いの影響により基板1が沿ってしまうこ とを防止できる。なお、裏面1b全面をパターン材にて覆っていないが、上記し たように表面1aと裏面1bとの各パターン面積を約同じにした本実施例に於い て、耐ノイズ性能に変化が無く、反りも生じることがなかった。In the substrate 1, the noise countermeasure pattern 3 is arranged such that the stripes are spaced in the longitudinal direction, and the ratio of the area of the noise countermeasure pattern 3 in the direction of easy warping should be reduced. You can Further, the pattern area of the entire back surface 1b is approximately the same as that of the front surface 1a, and when the noise countermeasure pattern 3 is reflowed, due to the influence of the difference in the thermal expansion / contraction rate between the substrate 1 and the pattern material, It is possible to prevent 1 from following along. Although the entire back surface 1b is not covered with the pattern material, in this embodiment in which the pattern areas of the front surface 1a and the back surface 1b are approximately the same as described above, there is no change in the noise resistance performance. , No warpage occurred.

【0013】[0013]

【考案の効果】[Effect of device]

このように本考案によれば、基板材とパターン材との間に於ける熱膨張・収縮 率の違いが大きな場合であっても、表面の配線パターンに対して裏面のノイズ対 策用パターンを約同面積にしたことから、ノイズ対策用パターンのリフロー時な どに於ける熱ストレスによるパターンの基板への影響を表裏両面で約同等にでき 、基板に生じる反りを防止し得る。特に、ノイズ対策用パターンを、反りの生じ 易い方向に間隔を開けた縞模様状に形成することにより、反り易い方向について は表面のパターンと面積比を約同等にすることができると共に、基板の裏面全域 に渡ってパターンを形成でき、耐ノイズ性が悪化することがない。 As described above, according to the present invention, even if there is a large difference in the coefficient of thermal expansion / contraction between the substrate material and the pattern material, the noise countermeasure pattern on the back surface can be provided to the wiring pattern on the front surface. Since the areas are approximately the same, the influence of the thermal stress on the board due to the thermal stress during the reflow of the noise countermeasure pattern can be made equal on both the front and back sides, and the warpage of the board can be prevented. In particular, by forming the noise countermeasure pattern in a striped pattern with intervals in the direction in which warpage is likely to occur, it is possible to make the area ratio approximately the same as the surface pattern in the direction in which warpage is likely to occur, and to A pattern can be formed over the entire back surface, and the noise resistance does not deteriorate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案が適用された基板の平面図であり、
(a)は表面を示し、(b)は裏面を示す。
FIG. 1 is a plan view of a substrate to which the present invention is applied,
(A) shows the front surface and (b) shows the back surface.

【図2】図1のII−II線に沿って見た部分拡大断面図。FIG. 2 is a partially enlarged sectional view taken along the line II-II in FIG.

【符号の説明】[Explanation of symbols]

1 基板 1a 表面 1b 裏面 2 配線パターン 3 ノイズ対策用パターン 1 substrate 1a front surface 1b back surface 2 wiring pattern 3 noise countermeasure pattern

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 表面に配線パターンを形成された基板の
裏面に形成したノイズ対策用パターンが、前記配線パタ
ーンと約同面積にて形成されていることを特徴とする基
板のノイズ対策用パターン構造。
1. A noise countermeasure pattern structure for a substrate, wherein a noise countermeasure pattern formed on the back surface of a substrate having a wiring pattern formed on the front surface is formed in approximately the same area as the wiring pattern. .
【請求項2】 前記ノイズ対策用パターンが、前記裏面
の全面に形成した場合に於ける反り易い方向に間隔を開
けた縞模様状に形成されていることを特徴とする請求項
1に記載の基板のノイズ対策用パターン構造。
2. The noise suppression pattern is formed in a striped pattern with a gap in the direction in which it easily warps when formed on the entire back surface. Pattern structure for noise suppression on the board.
JP1993075181U 1993-12-28 1993-12-28 Pattern structure for noise suppression of substrate Expired - Fee Related JP2599674Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1993075181U JP2599674Y2 (en) 1993-12-28 1993-12-28 Pattern structure for noise suppression of substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1993075181U JP2599674Y2 (en) 1993-12-28 1993-12-28 Pattern structure for noise suppression of substrate

Publications (2)

Publication Number Publication Date
JPH0743018U true JPH0743018U (en) 1995-08-11
JP2599674Y2 JP2599674Y2 (en) 1999-09-13

Family

ID=13568787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1993075181U Expired - Fee Related JP2599674Y2 (en) 1993-12-28 1993-12-28 Pattern structure for noise suppression of substrate

Country Status (1)

Country Link
JP (1) JP2599674Y2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199814A (en) * 1996-01-18 1997-07-31 Nec Corp Printed wiring board
JP2010157553A (en) * 2008-12-26 2010-07-15 Sharp Corp Interconnect sheet, solar cell with the interconnect cell, solar cell module, and method of manufacturing the solar cell with the interconnect sheet, and method of manufacturing the solar cell moidule
JP2011517063A (en) * 2008-03-31 2011-05-26 巨擘科技股▲ふん▼有限公司 Method for balancing stress of multilayer substrate and multilayer substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094168A (en) * 2007-10-04 2009-04-30 Denso Corp Circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199814A (en) * 1996-01-18 1997-07-31 Nec Corp Printed wiring board
JP2011517063A (en) * 2008-03-31 2011-05-26 巨擘科技股▲ふん▼有限公司 Method for balancing stress of multilayer substrate and multilayer substrate
JP2010157553A (en) * 2008-12-26 2010-07-15 Sharp Corp Interconnect sheet, solar cell with the interconnect cell, solar cell module, and method of manufacturing the solar cell with the interconnect sheet, and method of manufacturing the solar cell moidule

Also Published As

Publication number Publication date
JP2599674Y2 (en) 1999-09-13

Similar Documents

Publication Publication Date Title
CA2161569A1 (en) Circuit element mounting structure
JPH0743018U (en) Board noise pattern structure
JPH0260185A (en) circuit board
JPH0223005Y2 (en)
JP2761871B2 (en) Printed board
JPS57160150A (en) Heat dissipating board for hybrid ic
EP0442491A2 (en) Semiconductor device having a wiring pattern in which a plurality of lines are arranged in close proximity to one another
SE9803043L (en) Component carrier with improved component retention
JPH08279680A (en) Multilayer printed wiring board
KR970058409A (en) Printed circuit board to prevent warpage
JPH0258894A (en) On-surface mounting method of circuit element
JPS6279629A (en) Manufacture of semiconductor device
JPH0629164U (en) Double-sided printed wiring board
JP2563336Y2 (en) Hybrid integrated circuit board
JPH03230597A (en) Semiconductor device mounting structure
JP2612844B2 (en) Printed board
JPH03187289A (en) Method of preventing warp of board
JPH056687Y2 (en)
JPS6311721Y2 (en)
JPS5892290A (en) Electric circuit board
JPH0241917Y2 (en)
JPH04159793A (en) Mounting device for electronic component
JPH0147032B2 (en)
JPH0729867U (en) Printed circuit board
JPH03283590A (en) Manufacture of ceramic board

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees