JPH0744455B2 - A / D conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device for converting an analog signal into a digital code, and in particular, an integrated circuit means for converting at a sampling frequency that is one digit or more higher than the frequency of the signal. Structure suitable for.

(Prior art and its problems) Converting an analog signal into a digital code (A / D conversion) faster than the frequency of the signal by one digit or more is necessary to prevent aliasing noise, which is a problem during A / D conversion. It is known that this is a very effective method for reducing the requirement for the performance of the filter that performs band limitation in advance on the signal input to the A / D converter. This A / D conversion method based on the signal diagram shown in Fig. 2 is a method of performing A / D conversion with a small amount of hardware. The IEICE Communications Division National Convention was held in October 1984. Proceedings of 2-
It is publicly known and published on page 208. The circuit of FIG. 3 in which this signal diagram is described in a concrete circuit is also described on the same page. The operation of this circuit is as follows: input signal sampling cycle, cycle in which the difference between the charge proportional to the sampled signal and the charge proportional to the contents of the up / down counter is accumulated in the integrator, and the output of this integrator is the ground potential. The operation is performed in three cycles, that is, the polarity and the cycle for controlling the up / down counter. It is now assumed that the reference potential is a constant negative value, the input voltage is a positive value, the polarity output is positive, and the value of the up / down counter is incremented by, for example, one cycle before, and is 0101. Switch SB to the input signal sampling period on, SF is off, S0 to S4 and SN are brought down to the reference potential -V _R side, SI is brought down on the input side. Then, the input of the integrator is virtually grounded, and 32C _O V _i corresponding to the input voltage V _i is charged across 32C _O in FIG. next
Close the SF open the SB, the defeat S2 and S0 and SN corresponding to the up-down counter value 00101 Fold ground side SI to the ground, -32C to integrator _{O V i + 4C O V R} + C O V _R + C _O V _R becomes charge flows into the integrator, the charge is accumulated in the 32C _O in the integrator. As a result, the integrator output voltage becomes (32C _O V _i −
6C _O V _R) / 32C _O by one cycle before the integrator output voltage changes. Whether the voltage is positive or negative is determined by a voltage comparator. After making the judgment, SF is opened again, SB is closed, and SI is input to S0.
And S2 to the reference potential side. At this time, SN remains at the ground potential during the countdown. Then, the up / down counter is decremented by 1 to 00100 and the next integration cycle is waited for. In this series of operations, if the content of the up / down counter becomes zero and 1 is further decreased, the polarity is inverted and 1 is added to the up / down counter. At this time, SO to S4 are all collapsed to the ground potential side, and the switches corresponding to the bit positions of the up / down counter are collapsed to the reference potential side during integration, so that the polarities of the added charges are inverted.

By such an operation, the value of the up / down counter changes in the form of following the change of the input signal. The value of this counter corresponds to the result of good A / D change for the input signal.

This circuit has a simple circuit configuration, but each time the input signal cuts off the ground potential, SO to S4 switch between the ground potential and the reference potential. At this time, in order to keep the input terminal of the integrator at the virtual ground state, charging / discharging must be performed from the output side of the integrator through the switch SB. This charge / discharge charge amount is 31 _{C O} V _R, which is considerably large. Further, the input signal cuts off the ground potential most often when the input signal is small. If the integration operation is started before the integrator reaches the virtual ground state sufficiently in the transition state of this switching, this error means that the noise accompanying the A / D conversion is generated. Therefore, this circuit imposes a heavy load on the driving capability of the operational amplifier that constitutes the integrator, and becomes a bottleneck in increasing the operating speed. Further, this circuit also has a drawback that it is vulnerable to power supply noise because it also amplifies ground potential noise.

(Object of the Invention) A first object of the present invention is to reduce the requirement for the driving capability of an operational amplifier and to facilitate high-speed operation.
A second purpose is to balance the analog signal paths and prevent performance degradation due to power supply noise. Further, these objects are realized with a small number of additional elements as compared with the conventionally proposed circuits. A third object of the present invention is to provide a circuit configuration suitable for integration into an integrated circuit.

(Structure of the Invention) The A / D conversion circuit of the present invention is 2 balanced with respect to the ground potential.
A first capacitor and a first switch are connected in series between one input and one output of an operational amplifier having two inputs and outputs, and a second switch is connected in parallel,
A charge integrator in which a second capacitor and a third switch are connected in series between the other input and the other output and a fourth switch is connected in parallel, and this charge integrator A voltage comparator having two outputs as inputs, a toggle flip-flop, an up-down counter, and a first count-up and count-down control based on the output of the voltage comparator and the output of the toggle flip-flop. Control gate, a second control gate for controlling the state of the toggle flip-flop by the output of the up / down counter and the output of the first control gate, and a charge amount proportional to the count value of the up / down counter. A means for supplying one input of the charge integrator, and a charge amount equal to the charge amount to the other input of the charge integrator. Means for deducting, a fifth switch for reversing the connection by the output of the toggle flip-flop when the means for supplying the charge and the means for subtracting are connected to the input of the charge integrator, and the charge integrator. Means for supplying a charge proportional to the input voltage to one of the inputs, and means for subtracting a charge equal to the charge proportional to the input voltage from the other input of the charge integrator,
A constant between half and twice the minimum resolution charge generated by the means for supplying one input of the charge integrator with a charge proportional to the count value of the counter in response to the output of the voltage comparator. Means to supply or subtract charge
And a means for subtracting or supplying the constant charge to the other input of the charge integrator,
It is characterized in that the output of the voltage comparator or the output of the up / down counter is used as the conversion output.

(Embodiment) Next, an embodiment of the present invention will be described with reference to FIG. First
The figure is a circuit diagram when a 5-bit up / down counter is used as the up / down counter. This circuit is a switch SFN connected in series with 32C _O when the minimum capacity is C _O at one of the two input / output terminals of the balanced operational amplifier,
And a switch SBN is connected in parallel, and a switch SFP and a switch SBN, which are also connected in series with 32C _O, and a switch SBN are connected in parallel to form a balanced charge integrator. The integrator output is connected to the voltage comparator. The output of the comparator is matched with the output of the toggle flip-flop. The output of the up / down counter one cycle before is judged by the NOR circuit whether the count value is zero, and the toggle flip-flop is inverted when the count value is zero and the coincidence logic is zero. At the same time, when the value of the up / down counter at the time one cycle before is 0 or the coincidence logic is
If so, add 1 to the up / down counter. Otherwise, 1 is subtracted. Weighted by a power of 2, one end is commonly connected and the other end is a switch SPO, SP1, SP
2, SP3 and SP4 connect to a switch that switches between reference potential and ground potential, and this switch has the same structure as a capacitor array that supplies negative charge that is controlled by the state of each bit of the up / down counter, and SPO, SP
1, SP2, SP3 and SP4 are also controlled by each bit of the up / down counter to supply the positive charge, and the capacitor array is connected to each of the charge integrators by the switches SPN and SPP, respectively. The connection is reversed depending on the direction. Further capacitors having a capacitance equal to or less than the minimum value of the capacitor array are connected to the input ends of the charge integrators, and the other ends are connected to switches SPF and SNF that can be switched between a reference potential and a ground potential. The falling directions of SPF and SNF are controlled by the output of the voltage comparator. One end of another capacitor having a value of 32 C _O is connected to each input terminal of the charge integrator, and the other end is connected to switches SIP and SIN for switching between a ground potential and an input voltage and is proportional to the input voltage. A means for supplying the generated charges to the integrating circuit is configured. Here although the capacitance connected to the SIP and SIN and 32C _O, the maximum amplitude of the input voltage is the number of bits equal counter to a reference potential is designed with 2 ^N C _O when N bits. If the ratio of the maximum amplitude and the reference voltage of the input voltage is 1 to K, 32C _O is 2 ^N C _O
Must be a value of K. 32C _O in the integrator may have any value, but an intermediate value between 2 ^N C _O and 2 ^N C _O K is desirable. Also SPF
The capacitor C _O connected to and SNF may be in the range between 1/2 C _O and C _O , but is easiest to manufacture equal to C _O.

Next, the operation of this circuit when an input signal is obtained in a balanced type will be described. The operation of this circuit is as follows. It operates in three cycles of determining and determining the states of the up / down counter and the toggle flip-flop. Now, set the reference potential −V _R to a negative value. It is assumed that a positive voltage is applied as the input voltage to the positive input terminal and a voltage equal to the positive voltage and inverted with respect to the ground potential is applied to the negative input terminal. SBP and SBN turned on during input sampling, SFP
And SFN are off. Further, SP0 to SP4 are tilted to the ground potential side, and SN0 to SN4 are tilted to the reference potential side.
SPF and SNF are logic 1 indicating that the toggle flip-flop is positive, and when the voltage comparator output is 1, SPF is pulled down to the ground side and SNF is pulled down to the reference potential side. Also, SIP and SIN are pushed down to the input terminal side. The SPP and SPN are connected in the forward direction as shown in the figure. Then the integration period opens SBP and SBN, SF
Close P and SFN, bring SIP and SIN to the ground potential side,
By setting the clock to logic 1, the lower side of the switches corresponding to the up / down counter is set to the reference potential side, and the upper side is set to the ground potential side.
Assuming that the content of the up / down counter is 00101, SP0, SP2 and SPF are switched from the ground potential side to the reference potential side, and SN0, SN2 and SNF are switched from the reference potential side to the ground potential side. Assuming that the positive input voltage is V _{i and the} negative input voltage is −V _i , −32C _O V _i +
The electric charge of 6C _O V _R is input, and 32C _O V _i −6 is input to the negative side input.
The electric charge of C _O V _R is input. Therefore, on the plus side of the charge integrator output, V _i −6V is applied to the integrator output voltage one cycle before.
The voltage change of _R / 32 is -V _R + 6V _R / 32 voltage change is obtained on the negative side, and the accumulation of the X (z) input part in Fig. 2 is achieved in a balanced form with respect to the analog signal. As a result, the output voltage changes twice as much as that of the conventional unbalanced circuit. The output of this integrator is judged to be positive or negative by the voltage comparator, and the first
It is transferred to the logic circuit portion in the lower part of the figure. At the end of the comparison, SFP and SFN are opened, SBP and SBN are closed and the clock is reset to zero. The output of the voltage comparator is matched with the output of the toggle flip-flop. The coincidence logic output detects the zero count value one cycle before by taking the NOR logic with respect to the up / down counter output, and if the count value is zero and the coincidence logic output is zero, a toggle flip-flop is used. Invert. At the same time, when the coincidence logic is 1 or the count value at the time point one cycle before is 0, the up / down counter is set to 1
Add. When the value one cycle before is not zero and the coincidence logic is zero, 1 is subtracted from the count value. In this example, the count value is 00101 and is not zero. The output of the toggle flip-flop is 1. Assuming that the output of the comparator is 1, this means that the input signal is larger than the sum of the voltage corresponding to the value of the up / down counter and the voltage stored in the charge integrator one cycle before. .
In this case, since the coincidence logic output is 1, 1 is added to the up / down counter. If the output of the comparator is now zero, it means that the input signal is smaller. In this case, the coincidence logic output becomes zero. Further, since the NOR gate output connected to the counter is also zero, 1 is subtracted from the counter. In this way, the value of the counter increases or decreases according to the input signal.

It is assumed that the contents of the counter are now zero and the output of the voltage comparator is also zero in the next cycle. Then, since the NOR gate connected to the up / down counter outputs 1, the up / down counter 1 is counted. At the same time, the input of the toggle flip-flop also becomes 1 and the toggle flip-flop is inverted. When the toggle flip-flop is inverted, SPP and SPN are cross-connected, the condenser array supplying negative charges is connected to the negative input of the charge integrator, and the condenser array supplying positive charges is connected to the positive input of the charge integrator. To be done. At this time, since the input terminal of the charge integration circuit remains virtually grounded, the voltage change unlike the conventional example does not occur anywhere. Therefore, when the polarities are switched, it becomes possible to shorten the settling time of the charge integrator, which has been very important in the past, and it is possible to easily operate at high speed.

The above explanation has been given for the case where the inputs are balanced, but in the case of unbalanced inputs, the two input terminals are connected in common and used as the input terminals. Sometimes the same effect as described above can be obtained by tilting it to the input side.

(Effects of the Invention) As described above, according to the present invention, it is possible to significantly reduce the load on the driving capability of the integrating circuit which occurs when the polarity of the input signal is switched, which is a conventional problem.
A significantly high speed operation is possible. Furthermore, since analog signals operate in balance, they are also resistant to power supply noise, and combined with the effect of doubling the internal signal voltage, noise that is received from other parts even if integrated into a large-scale integrated circuit. It is suitable for integrated circuits because it can be made very small.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is a signal diagram which is the basis of the present invention. FIG. 3 is a conventional circuit diagram embodying the signal diagram of FIG.

Claims (1)

[Claims] 1. An operational amplifier having two inputs and outputs balanced with respect to ground potential, wherein a first capacitor and a first switch are connected in series between one input and one output of the operational amplifier. The second switch is connected in parallel, and the second capacitor and the third switch are connected in series between the other input and the other output, and the fourth switch is connected in parallel. Charge integrator, a voltage comparator having two outputs of the charge integrator as inputs, a toggle flip-flop, an up / down counter, and the up / down counter based on the output of the voltage comparator and the output of the toggle flip-flop. A control gate for controlling the count-up and count-down of the toggle flip-flop by the output of the up-down counter and the output of the first control gate. A second control gate for controlling the state,
Means for supplying a charge amount proportional to the count value of the up / down counter to one input of the charge integrator; means for subtracting a charge amount equal to the charge amount from the other input of the charge integrator; A fifth switch whose connection is reversed by the output of the toggle flip-flop when the means for supplying charge and the means for subtracting are connected to the input of the charge integrator, and one input of the charge integrator Means for supplying a charge proportional to the input voltage, a means for subtracting a charge equal to the charge proportional to the input voltage from the other input of the charge integrator, and the input to one input of the charge integrator. It also supplies a constant charge between half and twice the minimum resolution charge generated by the means for supplying a charge proportional to the count value of the counter according to the output of the voltage comparator. Or subtracting means and means for subtracting or supplying the constant charge to the other input of the charge integrator, and using the output of the voltage comparator or the output of the up / down counter as the conversion output. A / D conversion circuit characterized by.