JPH0748643B2 - Latch circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention mainly relates to an A / D converter that performs a high-speed operation, particularly a parallel A / D converter.
The present invention relates to a latch circuit used in a converter.

Conventional technology Normally, when implementing an A / D converter with MOS transistors,
When a differential amplifier is used as the comparator, it is usual to employ a differential circuit as a latch circuit that determines the output signal of the comparator to amplify and hold the output signal of the comparator.

A circuit diagram of a conventional differential latch circuit is shown in FIG. The differential latch circuit of FIG. 2 is composed of P-channel transistors 1-6 and N-channel transistors 7-10. The gate terminals and drain terminals of the P-channel transistors 1 and 2 are alternately connected, and N
The gate terminals and drain terminals of the channel transistors 7 and 8 are connected alternately. In addition, the source and drain terminals of the P-channel transistors 1 and 2 are connected in parallel to the source and drain terminals of the P-channel transistors 3 and 4, respectively, and the P-channel transistors 3 and 4 gate terminals are respectively connected to the inverting signal input terminal 11 and Non-inverted signal input terminal 12
Is done. Then, the source and drain terminals of the N-channel transistors 9 and 10 are connected in parallel with the source and drain terminals of the N-channel transistors 7 and 8, respectively, and the P-channel transistor 1 and the drain terminal of the N-channel transistor 7 are connected to each other by P-channel transistors. The channel transistor 5 is inserted in series, and the P-channel transistor 6 is inserted in series between the drain terminals of the P-channel transistor 2 and the N-channel transistor 8. The gate terminals are connected to each other to form the clock input terminal 13. In addition,
P-channel transistor 5 and N-channel transistor 7,
The connection point between the drain terminals of 9 is the non-inverting output terminal 14
The connection point between the drain terminals of the P-channel transistor 6 and the N-channel transistors 8 and 10 becomes the inverting output terminal 15. The terminal 16 is a power supply terminal.

Next, the operation of the differential latch circuit shown in FIG. 2 will be described. First, consider the case where the clock signal applied to the clock input terminal 13 is "H". In this case, the P-channel transistors 5 and 6 are off and the N-channel transistors 9 and 10 are on. As a result, the non-inverting output terminal 14 and the inverting output terminal 15 both output “L”. The P-channel transistors 3 and 4 are in a weak ON state according to the signal voltage applied to the inverted signal input terminal 11 and the non-inverted signal input terminal 12. However, the P-channel transistor 5,
Since 6 is off, P-channel transistors 1 to
No current flows through 4. In this way, the clock signal is "H"
When, the operation of the latch circuit is in the standby state. Next, it is assumed that the clock signal becomes "L". In this case, the P-channel transistors 5 and 6 are on and the N-channel transistors 9 and 10 are off. Since the P-channel transistors 3 and 4 are weakly turned on according to the signal voltage applied to the inverted signal input terminal 11 and the non-inverted signal input terminal 12, the clock signal changes from “H” to “L”. At the instant, a voltage corresponding to the signal voltage applied to the inverted signal input terminal 11 and the non-inverted signal input terminal 12 is generated in the internal nodes 17 and 18 which are the drain terminals of the P-channel transistors 3 and 4. Inverted signal input terminal 11 and non-inverted signal input terminal
If there is a slight potential difference between the signal voltages applied to 12, a potential difference will occur in the voltage generated at the internal nodes 17 and 18. Then, since the gate terminals and drain terminals of the P-channel transistors 1 and 2 are respectively connected and connected to the internal nodes 17 and 18, the P-channel transistors 1 and 2 show the potential difference of the voltage generated at the gate terminals. After amplification, one of the internal nodes 17 and 18 becomes "H", and the other one becomes an intermediate potential between "H" and "L", that is, "M". The "H" and "M" signals generated at the internal nodes 17 and 18 are applied to the drain terminals of the N channel transistors 7 and 8 through the P channel transistors 5 and 6. Then, since the gate terminal and the drain terminal of the N-channel transistors 7 and 8 are connected to each other by crossing, the N-channel transistors 7 and 8 amplify the potential difference of the voltage applied to the gate terminals and Is “H” and the other one is “L” and is held. Non-inverting output terminal 14 and inverting output terminal, respectively
It is output from 15. When the clock signal becomes "L" in this way, the circuit enters the latch operation state.

Here, a circuit diagram of a typical differential amplifier is shown in FIG. In the differential amplifier circuit of FIG. 3, the N-channel transistors 19 and 20 are driving transistors, the P-channel transistors 21 and 22 are load transistors, and the constant-current source is a bias-voltage input terminal 23. Use 24. The gates of the N-channel transistors 19 and 20 are used as the signal voltage input terminal 25 and the reference voltage input terminal 26, respectively, and the connection point between the drain terminals of the N-channel transistor 19 and the P-channel transistor 21 is inverted output terminal 27.
The connection point between the drain terminals of the N-channel transistor 20 and the P-channel transistor 22 is used as the non-inverting output terminal 28. The terminal 16 is a power supply terminal.

The operation of the differential amplifier circuit shown in FIG. 3 will be briefly described.
This circuit is a circuit that obtains an output signal according to the magnitude relation between the input signal applied to the signal voltage input terminal 25 and the comparison reference voltage applied to the reference voltage input terminal 26. The output signal is the inverting output terminal 27 and the non-inverting output terminal 28. The difference in voltage appearing at is used. The bias voltage applied to the bias voltage input terminal 23 in order to use the N-channel transistor 24 as a constant current source is a voltage at which the N-channel transistor 24 operates as an appropriate drain current in the saturation operation region. In this differential amplifier circuit, when the input signal is higher than the comparison reference voltage, the voltage appearing at the non-inverting output terminal 28 becomes the intermediate potential “M” and the voltage appearing at the inverting output terminal 27 becomes the low potential “L”. . The low voltage “L” is lower than the intermediate potential “M”, but never lower than the drain voltage of the N-channel transistor 24. When the input signal is lower than the comparison reference voltage, the voltage appearing at the non-inverting output terminal 28 remains at the intermediate potential “M”, but the voltage appearing at the inverting output terminal 27 becomes the high potential “H”. This high potential “H” is almost the power supply terminal
Power up to the voltage applied to 16.

Now, in an actual A / D converter, a differential amplifier circuit as shown in FIG. 3 and a latch circuit as shown in FIG. 2 are connected in series and used as a voltage comparator. That is, the inverting output terminal 27 of FIG. 3 is connected to the inverting signal input terminal 11 of FIG.
Further, the non-inverting output terminal 28 in FIG. 3 is connected to the non-inverting signal input terminal 12 in FIG. 2 and used as a voltage comparator.

SUMMARY OF THE INVENTION However, in the above-mentioned conventional latch circuit,
There is a problem in that an input signal of the latch circuit is given from the output of the differential amplifier located in the preceding stage of the latch circuit, which may cause a malfunction under a specific condition.

Now, consider the case where the clock signal applied to the clock input terminal 13 of the differential latch circuit shown in FIG. 2 is "H". In this case, the non-inverting output terminal 14 and the inverting output terminal 15
Both output “L”. P-channel transistor 3,4
Is in a state corresponding to the signal voltage applied to the inverted signal input terminal 11 and the non-inverted signal input terminal 12, that is, the output voltage of the inverted output terminal 27 and the non-inverted output terminal 28 of the differential amplifier circuit in FIG. ing. If the non-inverting output terminal 28 of the differential amplifier circuit is "M" and the inverting output terminal 27 is "L", the P-channel transistors 3 and 4 are both in the ON state regardless of the strength. Internal node of 17,18
Becomes "H". However, if the non-inverting output terminal 28 of the differential amplifier circuit is "M" and the inverting output terminal 27 is "H",
Since the P-channel transistor 4 is in the ON state but the P-channel transistor 3 is in the OFF state, the internal node 18 of the latch circuit is determined to be "H", but the internal node 17 becomes high impedance and the latch data in the previous state is stored. Retained. However, if only the clock signal goes to "L" in this state, the non-inverting output terminal 14 is "H" and the inverting output terminal is irrespective of the previous latched data held in the internal node 17. There is no problem because it becomes 15 “L”. However, if the inverting output terminal 27 of the differential amplifier circuit also changes from “H” to “L” immediately before the clock signal changes from “H” to “L”, the output of the latch circuit is held at the internal node 17. Since it is affected by the data in the latched state before being operated, it causes a malfunction under a specific condition. That is, the internal node
While the data "L" in the previous latched state is held in 17, the inverting output terminal 27 of the differential amplifier circuit is changed from "H" to "L" immediately before the clock signal changes from "H" to "L". When it changes to, the "L" held in the internal node 17 has an influence, and originally, the non-inverting output terminal 14 should output "L" and the inverting output terminal 15 should output "H". The non-inverting output terminal 14 is in the "H" level, and the inverting output terminal 15 is in the "L" level. This is because the inverting output terminal 27 of the differential amplifier circuit originally changes from "H" to "L" and the P-channel transistor 3 turns on, so that the charge of the internal node 17 changes from "L" to "H". However, since the delay time of the ON operation of the P-channel transistor 3 and the ON state are weak, the charging and discharging of the parasitic capacitance of the internal node 17 is still insufficient at the timing when the clock signal changes, and the internal node 17 is insufficient. This is because there is a potential difference between and.

As described above, since the latch circuit in the conventional example causes a malfunction under a specific condition, it has been inconvenient in a high-speed conversion application such as a parallel A / D converter.

Means for Solving the Problems In order to solve the above problems, a latch circuit according to the present invention has gate terminals and drain terminals of first and second transistors alternately connected, and third and fourth transistors. Alternately connecting the gate terminal and the drain terminal of the transistor,
The source and drain terminals of the second transistor are connected in parallel to the source and drain terminals of the fifth and sixth transistors, respectively, and the gate terminals of the fifth and sixth transistors are respectively connected to the inverting signal input terminal and the non-inverting signal input terminal. The source and drain terminals of the seventh and eighth transistors are connected in parallel with the source and drain terminals of the third and fourth transistors, respectively, to form the inverted signal input terminal, and the first and third transistors are connected. A ninth transistor is inserted in series between the drain terminals of the transistors, and a tenth transistor is inserted in series between the drain terminals of the second and fourth transistors. The source and drain terminals of the second transistor are connected in parallel with the source and drain terminals of the second transistor, respectively, and
The gate terminals of the seventh, eighth, ninth, and tenth transistors are positive phase clock input terminals, and the gate terminals of the eleventh and twelfth transistors are negative phase clock input terminals. There is.

Action Since the latch circuit according to the configuration of the present invention does not malfunction at any input timing, when the latch circuit according to the configuration of the present invention is applied to an A / D converter, particularly a parallel A / D converter, the input signal is It has an effect that a correct conversion can be always performed even when changing at high speed.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a differential latch circuit according to an embodiment of the present invention. The differential type latch circuit of FIG.
It is composed of channel transistors 1 to 6, 29, 30 and N channel transistors 7 to 10. The gate terminals and drain terminals of the P-channel transistors 1 and 2 are alternately connected, and the gate terminals and drain terminals of the N-channel transistors 7 and 8 are alternately connected. In addition, the source and drain terminals of the P-channel transistors 1 and 2 are connected in parallel to the source and drain terminals of the P-channel transistors 3 and 4, respectively, and the gate terminals of the P-channel transistors 3 and 4 are connected to the inverted signal input terminal 11 respectively.
And the non-inverted signal input terminal 12, and the source and drain terminals of the N-channel transistors 7 and 8 are connected in parallel to the source and drain terminals of the N-channel transistors 7 and 8, respectively. Then, the P-channel transistor 5 is inserted in series between the drain terminals of the P-channel transistor 1 and the N-channel transistor 7, and P
The P-channel transistor 6 is inserted in series between the drain terminals of the channel transistor 2 and the N-channel transistor 8, and the sources of the P-channel transistors 29 and 30 are connected in parallel with the source and drain terminals of the P-channel transistors 1 and 2, respectively. Connect the terminal and drain terminal, P
Channel transistors 5 and 6 and N channel transistors 9 and 1
Positive phase clock input terminal 1 by connecting the gate terminals of 0
3, the gate terminals of the P-channel transistors 29, 30 are connected to each other to form the negative phase clock input terminal 31.
The connection point between the drain terminals of the P-channel transistor 5 and the N-channel transistors 7 and 9 is connected to the non-inverting output terminal 14, and the connection point between the drain terminals of the P-channel transistor 6 and the N-channel transistors 8 and 10 is , And is connected to the inverting output terminal 15. The terminal 16 is a power supply terminal.

Next, the operation of the differential latch circuit shown in FIG. 1 will be described. The basic operation is not much different from that of the conventional example shown in FIG. However, in the latch circuit according to the present invention, the clock terminal and the clock signal are particularly referred to as a positive-phase clock terminal and a positive-phase clock signal, and are distinguished from the negative-phase clock terminal and the negative-phase clock signal which have not been found in the conventional example. First, consider a case where the positive-phase clock signal applied to the positive-phase clock input terminal 13 is "H". At this time, the reverse phase clock input terminal
The negative-phase clock signal applied to 31 is "L". In this case, the P-channel transistors 5 and 6 are off and N
Channel transistors 9 and 10, P-channel transistor 2
9,30 is turned on. As a result, the non-inverting output terminal 14 and the inverting output terminal 15 both output “L” as in the conventional example, but the potentials of the internal nodes 17 and 18 are also determined to be “H”. Next, consider the case where the positive-phase clock signal is "L". At this time, the negative phase clock signal is "H". In this case, the P-channel transistors 5 and 6 are on, the N-channel transistors 9 and 10 and the P-channel transistors 29 and 30 are
Turns off. The outputs of the non-inverting output terminal 14 and the inverting output terminal 15 are output according to the signal voltage applied to the inverting signal input terminal 11 and the non-inverting signal input terminal 12. Moreover, in the latch circuit according to the present invention, since the P-channel transistors 29 and 30 are turned on in the standby state, the internal nodes 17 and 18 are set to the "H" state instead of the high impedance. It does not cause malfunctions like the example.

Note that in the case of the present invention, the negative phase clock does not necessarily have to be a strictly negative phase with respect to the positive phase clock, and in order to achieve at least the object of the present invention, the P of the latch circuit in the standby state in FIG. Channel transistor
It suffices if the potentials of the internal nodes 17 and 18 can be removed by determining the potentials of the internal nodes 17 and 18 to be in the “H” state from the occurrence of an unstable element due to the high impedance state of the potentials of the internal nodes 17 and 18 that are once turned on. Further, although the latch circuit according to the present embodiment has shown the example in which the P-channel transistor is used as a signal input, it goes without saying that the present invention can be applied to a circuit in which the N-channel transistor and the P-channel transistor are interchanged.

EFFECTS OF THE INVENTION As described above with reference to the drawings, the latch circuit according to the present invention has a circuit configuration that does not cause a malfunction due to the high impedance state of the internal node at any input timing. When the circuit is adopted as an A / D converter, especially a parallel type A / D converter,
This has the effect of facilitating the realization of an excellent A / D converter capable of high-speed conversion without erroneous conversion.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a latch circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional latch circuit, and FIG. 3 is a circuit diagram showing a differential amplifier circuit for explanation. . 1-6,21,22,29,30 ... P-channel transistor, 7-1
0,19,20,24 …… N-channel transistor, 11 …… Inverted signal input terminal, 12 …… Non-inverted signal input terminal, 13 …… Positive phase clock input terminal, 14,28 …… Non-inverted signal output terminal, 15,27
…… Inverted signal output terminal, 16 …… Power supply terminal, 17,18 …… Internal node of latch circuit, 23 …… Bias voltage input terminal,
25 …… Signal voltage input terminal, 26 …… Reference voltage input terminal, 31
…… Reverse-phase clock input terminal.

Claims (1)

[Claims] 1. A gate terminal and a drain terminal of the first and second transistors are alternately connected, and a gate terminal and a drain terminal of the third and fourth transistors are alternately connected,
The source and drain terminals of the fifth and sixth transistors are connected in parallel to the source and drain terminals of the first and second transistors, respectively, and the gate terminals of the fifth and sixth transistors are inverted signals. An input terminal and a non-inverted signal input terminal, and the source and drain terminals of the seventh and eighth transistors are connected in parallel with the source and drain terminals of the third and fourth transistors, respectively. A ninth transistor is inserted in series between the drain terminals of the third and third transistors, and a tenth transistor is inserted in series between the drain terminals of the second and fourth transistors. In parallel with the source and drain terminals of the first and second transistors, the eleventh and first terminals, respectively.
The source terminal and the drain terminal of the second transistor are connected, and the gate terminals of the seventh, eighth, ninth, and tenth transistors are positive-phase clock input terminals, and the gates of the eleventh and twelfth transistors are connected. A latch circuit characterized in that the terminal is formed as a reverse-phase clock input terminal.