JPH0749865Y2 - Pulse frequency multiplier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a pulse frequency multiplier circuit for multiplying an input pulse by 2 ^N to obtain a multiplied output with a duty ratio of 1/2.

[Prior Art] Conventionally, as a pulse frequency multiplier circuit for obtaining a doubled output with a duty ratio of 1/2, a doubler circuit utilizing a sawtooth wave has been known.

This will be described with reference to FIGS. 3 and 4.

The leading edge and trailing edge pulses Ea and Eb of the input pulse Ei having a duty ratio of 1/2 are detected by the edge detecting circuit 1, and the sawtooth wave generating circuit 2 is detected by the leading edge and trailing edge pulses Ea and Eb. The leading and trailing edge pulses at its output.
A sawtooth wave Ec synchronized with Ea and Eb is obtained. 3 is a level comparator, the threshold value of which is set to zero. Therefore, the level comparator 3 switches at the central level of the sawtooth wave Ec and outputs a square wave with a duty ratio of 1/2. The wave signal Ed (doubled output) can be obtained.

[Problems to be Solved by the Invention] Since the conventional system is a doubling circuit using a sawtooth wave, only 2 doubling of the input pulse is possible and 4 ^N , 8 ^N, etc. 2 ^N multiplication (N is a natural number) ) If you want to
Multiple multiplication circuits must be connected in cascade.

Further, this system is an unsuitable circuit for an integrated circuit because it detects the center level of the sawtooth wave Ec in an analog manner to obtain a doubled output.

[Means for Solving Problems] The present invention has the following requirements (1) to (6).

(1) A clock pulse generation circuit 7 that generates a clock pulse.

(2) A reference pulse generation circuit 10 for obtaining a reference pulse having a cycle corresponding to 1/2 cycle of the input pulse.

(3) A first counter circuit 11 that counts clock pulses during one cycle of the reference pulse and obtains a count value corresponding to one cycle of the reference pulse.

(4) The count value of the first counter circuit 11 is LSB (l
east significant bit Bit of the least significant digit of binary data)
Shift from, 1/2 ^{N of the} above count value (N is a natural number)
Latch circuit for obtaining 12.

(5) A second counter circuit 14 that counts the clock pulses and outputs a carrier signal when the count reaches the 1/2 ^N value.

(6) A flip-flop circuit 17 which is inverted by the carrier signal of the second counter circuit 14 to obtain a 2 ^N multiplied output of the duty ratio 1/2 of the input pulse.

[Operation] First step: A reference pulse having a period corresponding to 1/2 period of the input pulse is obtained, and the first counting circuit 11 counts the clock pulse for one period of this reference pulse to obtain the reference pulse. A count value corresponding to one cycle of the reference pulse is obtained.

Second step: This count value is set to the LSB (least signi
ficant bit Shift from the bit of the minimum digit of binary number data) to obtain 1/2 ^N value (N is a natural number) of the above count value.

Third step: The second counter circuit counts the clock pulses, outputs a carrier signal when the count reaches the 1/2 ^N value, and is preset by the carrier signal or the reference pulse. Then, the above counting operation is repeated.

That is, the second counter circuit outputs a carrier signal having a cycle corresponding to 1/2 ^N value of the count value corresponding to one cycle of the reference pulse.

4th step: The flip-flop circuit is inverted by this carrier signal, and the duty ratio of the input pulse is reduced to 1/2.
2 ^N multiplied output of is obtained.

[Embodiment] FIGS. 1 and 2 show an embodiment of the present invention.
In the figure, the input pulse is multiplied by 2 and the duty ratio is 1/2.
An embodiment is shown for obtaining a multiplied output.

FIG. 1 is a diagram showing the configuration of a first counter circuit, a latch circuit, a second counter circuit, a flip-flop circuit, and a reference pulse generating circuit for outputting edge pulses and reference pulses for controlling them according to the present invention. Similarly, it is a signal waveform diagram.

Hereinafter, description will be given with reference to the drawings.

The reference pulse generating circuit 10 for outputting the edge pulse and the reference pulse of the input pulse for controlling the first counter circuit 11, the latch circuit 12, the second counter circuit 14 and the flip-flop circuit 17 has the following configuration.

4, 5, 6 are data input D1, D2, D3, clock input CLK
First, second and third D-flip-flop circuits which have 1, CLK2 and CLK3 and whose outputs Q1, Q2 and Q3 keep the state of one bit before, between the data input D and the output Q, The relation of Qn + 1 = Dn is established.

The input pulse Ei is input to the data input D1 of the first D-flip-flop circuit 4, its output Q1 is input to the data input D2 of the second D-flip-flop circuit 5, and similarly its output Q2 is input to the third. The data input D3 of the D-flip-flop circuit 6 is input to obtain the output Q3. On the other hand, clock pulse fc
The first, second and third D-flipflop circuits 4,
Input to clock inputs CLK1, CLK2, and CLK3 of 5 and 6, respectively. Reference numeral 7 is a clock pulse generation circuit.

Here, the output Q1 of the first D-flip-flop circuit 4 is
2 corresponds to the leading edge and the trailing edge of the input pulse Ei and is the current period of the falling edge of the clock pulse fc, and the second D-flip-flop circuit 5
Output Q2 is the output Q1 of the first D-flipflop circuit 4.
From the clock pulse fc by 1 cycle, similarly,
The output Q3 of the D-flip-flop circuit 6 is delayed from the output Q2 of the second D-flip-flop circuit 5 by one cycle of the clock pulse fc.

Then, the first and second D-flip-flop circuits 4, 5
Outputs Q1 and Q2 of the EX-OR circuit 8 (exclusive OR
Circuit), and its OR output is used as the edge pulse A of the input pulse Ei, and the outputs Q2 and Q3 of the second and third D-flipflop circuits 5 and 6 are supplied to the EX-NOR circuit 9 (exclusive (exclude (exclude
sive) NOR circuit) and inputs its NOR output to the reference pulse B
And

One cycle of the reference pulse B corresponds to a half cycle of the input pulse Ei and is synchronized with the clock pulse fc. Further, the edge pulse A of the input pulse Ei is advanced by one cycle of the clock pulse fc with respect to the reference pulse B.

Next, the first counter circuit 11, the latch circuit 12, the second counter circuit 14, and the flip-flop circuit 17 will be described.

A first counter circuit 11 counts up the clock pulse fc, and inputs the clock pulse fc to its clock input terminal 11C and the reference pulse B to the reset terminal 11R.

The first counter circuit 11 sequentially counts the clock pulse fc from the initial value [OO ... O] and outputs the count value [O0O1 ... On]. Then, the first counter circuit 11 is reset for each reference pulse B and repeats the same operation as above.

Therefore, the count output of the first counter circuit 11 [O0
O1 ... On] f The count value corresponds to one cycle of the reference pulse B.

12 is a latch circuit, whose input is the first counter circuit
11 count output [O0 O1 ...... On] LSB (least sig
Input the value [0 1 ... On] excluding the minimum digit bit of the nificant bit binary number data, and input the above edge pulse A to the latch enable terminal 12LE.

Then, in synchronization with this edge pulse A, the value [O1 ...
… On is held and this is latch output [L1 L2 ……
Ln] is output.

That is, the count value [O0 O1 ... On] corresponding to one cycle of the reference pulse B is shifted by one digit from its LSB, and the value [O0 O1 ... On] is half the value [O0 O1 ... On].
1 …… Holds [On] and outputs it as latch output [L1 L2
Output as [Ln].

This latch output [L1 L2 ... Ln] is inverted by the first inverter circuits 13a, 13b ... 13k, and its complementary value [Q0 Q1 ... Qn-1] is created.

Here, the reason why the edge pulse A which is advanced by one cycle of the clock pulse fc with respect to the reference pulse B is used as the latch enable signal is that the first counter circuit 11 is set by the reference pulse B before it is set. , It holds the count value [O0 O1 ... On] and outputs it as a latch output [L1 L2 ... Ln].

A second counter circuit 14 counts up the clock pulse fc, inputs the clock pulse fc to its clock input terminal 14C, and presets the complementary value [Q0 Q1 ... Qn-1] to the preset input 14P. .
The second counter circuit 14 has the complementary value [Q0 Q1 ...
[Qn-1] as the initial value, the clock pulse fc is sequentially counted, and when the count value reaches the full count, the carrier signal CA is output from the carrier output terminal 14CA.

The carrier signal CA is inverted by the second inverter circuit 15 and then input to the AND circuit 16 together with the reference pulse B, and the AND output is input to the preset terminal 14PR of the second counter circuit 14 as a preset signal. To do.

The second counter circuit 14 sequentially counts the clock pulses fc with the preset value, that is, the complementary value [Q0 Q1 ... Qn-1] as an initial value, and outputs the carrier signal CA when the count value reaches a full count. It is output and preset by the carrier signal CA or the reference pulse B, and the above counting operation is repeated.

The inverted carrier signal ▲ ▼ is input to the clock input unit 17C of the fourth D-flip-flop circuit 17, and its negative output is input to the data input 17D, while the reference pulse B is input to the set terminal 17S. Then, the fourth D-flip-flop circuit 17 is inverted by the inverted carrier signal ▲ ▼ to obtain the duty ratio.
Obtain 1/2 output.

Although the present embodiment shows a configuration in which the input pulse is doubled to obtain a doubled output with a duty ratio of 1/2, other embodiments as described below can also be configured as merely design matters.

In this embodiment, the count output [O0 O1 ... On] of the first counter circuit 11 is set to the LSB (least significant b).
It is shifted by one digit from the smallest digit bit of binary data, and the half value [O1 ...... On] of the above count value [O1 ...... On] is held and this is output as a latch. L1 L2
... Ln] is output to obtain a doubled output.

Therefore, the count output of the first counter circuit 11 [O0
If you shift O1 ... On] by 2 digits from the LSB, the value will be 1/0 of the above count value [O0 O1 ... On].
The value of 4 becomes [O2 ... On], and 4 times output is obtained. Similarly, when the count output [O0 O1 ... On] of the first counter circuit 11 is shifted by 3 digits from its LSB, an 8 times multiplication output is obtained. Thereafter, in the same manner, 2 ^N multiplied output is obtained.

Further, in short, the second counter circuit 14 counts 1/2 ^N value of the count value corresponding to one cycle of the reference pulse B. Therefore, when the second counter circuit 14 is a down counter, Latch output above [L1 L2 …… Ln]
Is preset as it is, and the first inverter circuits 13a, 13b ... 13k are unnecessary.

Further, when the duty ratio of the input pulse Ei is not 1/2, only the leading edge of the input pulse Ei is detected to create the reference pulse, and the count output [O0 of the first counter circuit 11 is generated.
O1 ... On] By appropriately selecting the number of digits to be shifted, a multiplied output with a duty ratio of 1/2 can be obtained in the same manner.

[Advantages of the Invention] In the present invention, (1) the count output [O0 O1 ... On] of the first counter circuit 11 is converted into its LSB (least significant b).
by shifting the minimum digit bit of it binary data, the input pulse frequency is doubled according to the number of digits.
It can be multiplied by 4, ... 2 ^N (N is a natural number),
(2) It has an effect that it is the most suitable circuit for integrated circuits.

[Brief description of drawings]

FIG. 1 shows the first part of the pulse frequency multiplier circuit of the present invention.
Showing a counter circuit, a latch circuit, a second counter circuit, a flip-flop circuit, and a reference pulse generating circuit for outputting edge pulses and reference pulses for controlling these circuits, FIG. 2 is the same as the signal waveform diagram, and FIG. 3 is conventional. FIG. 4 is a signal waveform diagram showing the configuration of the pulse frequency multiplication circuit of FIG. 4, 5, 6 ... First, second and third D-flip-flop circuits, 7 ... Clock pulse generation circuit, 10 ... Reference pulse generation circuit, 11 ... First counter circuit, 12 ... Latch circuit , 14 …… Second counter circuit, 17 …… Flip-flop circuit.

Claims (3)

[Scope of utility model registration request] 1. A pulse frequency multiplying circuit having the following (a) to (f) as constituent elements. (A) A clock pulse generation circuit (7) for generating a clock pulse. (B) A reference pulse generation circuit (10) for obtaining a reference pulse having a cycle corresponding to 1/2 cycle of the input pulse. (C) A first counter circuit (11) for counting clock pulses during one cycle of the reference pulse to obtain a count value corresponding to one cycle of the reference pulse. (D) The count value of the first counter circuit (11) is LS
A latch circuit (12) that shifts from B (least significant bit bit of the minimum digit of binary number data) to obtain 1/2 ^N value (N is a natural number) of the above count value. (E) A second counter circuit (14) that counts the clock pulse and outputs a carrier signal when the count reaches the 1/2 ^N value. (F) Inverted by the carrier signal of the second counter circuit (14), the duty ratio of the input pulse is 1/2 of 2
^A flip-flop circuit (17) that obtains ^N- multiplied output. 2. The second counter circuit (14) is an up counter, and the second counter circuit (14) is provided with the above 1/2 ^N.
A pulse frequency multiplier circuit according to claim 1, wherein the complement value of the value (N is a natural number) is preset. 3. The second counter circuit (14) is a down counter, and the second counter circuit (14) is provided with the above 1/2 ^N.
The pulse frequency multiplier circuit according to claim 1, wherein the value (N is a natural number) is preset as it is.