JPS603228A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To obtain a frequency dividing output having a duty of 50% when an input signal is frequency-divided in the odd number by counting an input signal of (N-1)/2 and (N+1)/2 alternately in taking N (odd number) as the frequency dividing ratio. CONSTITUTION:The (N-1)/2 and (N+1)/2 are set to the 1st and 2nd setting devices 1a, 1b as setting values X, Y, where N is the odd number frequency dividing ratio. Then the value X is selected by a signal P of the 2nd FF circuit 7 and inputted to a preset input terminal PS of a counter 3. When a clock pulse CP becomes the value X, a signal CO is generated, a signal G is applied to the counter 3 via an OR gate 4 as a load enable signal LE and the value Y is preset. Outputs Q1, Q2 of FF ciruits 5, 7 go to ''L'' at the leading/trailing of the signal G, and an output Q2' selects the value X as the signal P and is applied to the counter 3. Then, an output having 4-5 period width of the pulse CP is obtained through the logical sum of the signals Q1 and Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a frequency divider circuit, and more particularly to a frequency divider circuit that can obtain an output with a duty of 50% when frequency is divided by an odd number.

The background technology frequency dividing circuit divides the frequency of an input signal to a predetermined frequency division ratio and outputs the frequency, and is a particularly important circuit in devices that handle digital signals. When the frequency division ratio N is an even number, the flip-flop circuit can be controlled by using a counter to generate an output every time N/2 input signals are counted, and by using this output signal to trigger the flip-flop circuit. A frequency-divided output with a duty ratio of 50% is obtained from the loop circuit. However, if the frequency division ratio N is an odd number, there is a problem that a frequency divided output with a duty of -50% cannot be obtained.

DISCLOSURE OF THE INVENTION Accordingly, it is an object of the present invention to provide a frequency dividing circuit that can obtain a frequency divided output with a duty of -50% even during odd frequency division.

In order to achieve such an object, the frequency dividing circuit according to the present invention has a frequency division ratio of (N-1)/2 and (
N+1)/2 input signals are alternately counted to generate an output, and a flip-flop circuit that is triggered by this output and a flip-flop circuit that is triggered by the inverted output of the counting output are provided. The OR output of the circuit is extracted as a frequency divided output.

The frequency divider circuit configured in this way has an extremely simple configuration and is numerous, so even when the input signal is frequency-divided by an odd number, it has the advantage of being able to accurately obtain a frequency-divided output with a duty of -50%. It has a great effect.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 is a circuit diagram showing an embodiment of a frequency dividing circuit according to the present invention, in which la and lb are first and second settings set to a desired division ratio N. The device 2 is the first and second setting device 1.
3 is a counter that counts the clock input signal OK, and takes the setting output output from selector 2 as a preset value when the load enable signal LE is supplied. , generates an output signal CO when its count value reaches a preset value. Reference numeral 4 denotes an OR gate for calculating the logical sum of the clock signal OK and the output signal CO of the counter 3, and its output signal is supplied to the counter 3 as a load enable signal LD. Reference numeral 5 denotes a seventeenth lip 70-tub circuit which accepts the output signal of the OR gate 4 supplied via the inverter 6 as a clock input, and its reset output Q1 is supplied to the input end. 7 is OK to clock the output of OR gate 4
A 27th lip flop circuit whose reset output Q! is supplied to the input end and also supplied to the selector 2 as a select control signal P. 8 is the first.
Set output Ql, Q of the 27th lip 70 circuit 5°7
This is an OR gate that outputs a frequency-divided output S by calculating the logical sum of 11.

In this way, in the frequency divider circuit with 'Ili', the first
The second setters 1a and 1bK set (N-1)/2 and (N+1)/2 as set values X and Y, respectively, when the odd frequency division ratio is N. For example, when configuring a 9 frequency divider circuit, x=4 is set in the first setter la, and the second
Note that Y=5 is set in the setting device 1b. And the first. The setting outputs X and Y of the second setting devices 1a and lb are as follows:
They are supplied to selector 20 input terminals AI and A2, respectively.

Here, since the second fritsoflop circuits 5 and 7 are reset at the time of start, Ll is
The select control signal P generated from the reset output terminal Q2 of the 7-rip 70-tub circuit 7 becomes "H", and accordingly, the selector 2 outputs the input terminal A1 from the first setting device 1a.
The set value X=4 supplied to the counter 3 is selected and supplied to the preset input PS of the counter 3.

Here, the counter 3 counts the clock pulse OF shown in FIG. 2(a) one by one, and when the set value is reached, it generates an output signal 00 shown at time tl in FIG. 2(b).

Then, when the clock 7 signal OP becomes "L" when this output signal 00 is generated, the output from the OR gate 4 as shown in FIG. 2 (C) occurs.
Since the output signal G shown between time points 12 and 13 is generated and supplied to the counter 3 as the load enable signal LE, the counter 3 receives the set value X=4 supplied from the selector 2. Preset.

On the other hand, the inverter 6 inverts the output signal G of the OR gate 4 and supplies the output signal G shown in FIG. 2(d) to the clock input terminal OK of the 17th lip-flop circuit 6. Therefore, the 17th rip circuit 5 is triggered by the fall of the output signal G supplied from the inverter 6, and outputs the set output Q shown in FIG. 2(e).
Generates 1. Further, the 27th lip-flop circuit 7 is triggered by the falling edge of the output signal G supplied from the OR gate 4, thereby generating the set output signal Q2 shown in FIG. 2(f).

Furthermore, when the 27th lip-flop circuit 7 is set,
The reset output is supplied to the selector 2 as the selection control signal P, so that the selector 2 selects the set value Y=5 supplied from the second setter 1b to the input terminal A2, and inputs the preset input of the counter 3. Supplied to the end PS.

Here, the counter 3 sequentially counts the clock pulses CP, and when the counted value reaches the above-mentioned preset value "4", the counter 3 generates the output signal CO shown at time t4 in FIG. 2(b). . Then, this output signal CO is logically summed with the clock pulse OP in the OR gate 4, so that an output signal G shown at time t5 to t6 in FIG. 2(C) is generated, and this output signal G is supplied to the counter 3 as load enable No. 4N LE, and the set value Y=
5 is preset.

On the other hand, the output signal G of the OR gate 4 is supplied as the output signal G to the 17th lip flop circuit 5 via the inverter 6, so that the rising edge of the output signal G resets the 17 th lip flop circuit 5. Set output Ql(l″1. As shown at time t5 in FIG. 2(e), “
The 27th lip flop circuit 7 is triggered by the falling edge of the output signal G of the OR gate 4, so that its set output Q2 becomes "H" as shown in FIG. 2(f). When the 27th lip flop circuit 7 is reset, the reset output Q2 is supplied to the selector 2 as the select control signal P, so that the selector 2 adjusts the setting value X of the first setting device 1a. =4 is selected and supplied to the counter 3. Also, the 1st.27th
Set output signal Q of lipfrost circuits 5 and 7, 1. Q
2 is 1H'' shown between time points 12 and 16 in FIG.
A divided output S of the level is generated. In this case, the ``H''H'' of the frequency divided output S is the clock pulse OF
It has a period width of 4.5 periods. Next, counter 3
When the count reaches "5", time t7 is shown in FIG. 2(b).
An output signal 00 indicated by is generated. When the clock pulse OF becomes "H" during this output signal 000 generation period, the output signal G shown between time t8 and time t9 in FIG. 2(C)
is generated. This output signal G is supplied to the counter 3 as load enable signals I and E, whereby a set value X=4 is preset in the counter 3.

On the other hand, the output signal G of the OR gate 4 is inverted in the inverter 6 and is supplied to the 17th lip-flop circuit 5 as the output signal G shown in FIG. 2(d). The 17th lip flop circuit 5 is triggered at time t8 when the output signal G falls, so that its set output Q1 becomes "H" as shown in FIG. 2(e). Further, since the output signal G of the OR gate 4 triggers the second fritz-flop circuit 7, its set output Q2 becomes "H" at time t9 when the output signal G falls. And this first one. 27th lip-flop circuit 5, 7
The set outputs Ql and Q2 are logically summed in the OR gate 8, so that the output is "L" for 4.5 cycles of the clock pulse ξ shown between time t6 and t8 in FIG. 2(g). A frequency-divided signal S having a period of `` is generated.

By repeating such an operation, the nine cycles of the clock pulse CP are made into one cycle, and the "H" period and the "1H"
A frequency-divided signal S with a duty of -50% and a period corresponding to 4.5 cycles of the clocked Qi-less OP is generated.

In the above embodiment, the output signal G is generated by the OR gate 4 which receives the clock pulse CP as the input signal and the output signal of the counter 3, but the present invention is not limited to this. Instead, any gate circuit may be used as long as it generates an output signal having a pulse width equal to a half period of the input signal when the counter 3 generates an output. Further, the counter 8 is also the first one. Needless to say, any gate circuit that performs a logical sum on the output signals of the 27th lip flop circuits 5 and 7 may be used.

As explained above, although the frequency divider circuit with the above configuration has an extremely simple configuration, when the input signal is divided by an odd number, the duty is exactly 50%.
No. 6 can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a frequency dividing circuit according to the present invention, and FIGS. 2(a) to 2(g) are operation waveform diagrams of each part of the circuit shown in FIG. 1. 1a...first setting device, lb...second setting device, 2...
- Selector, 3... Counter, 4, 8... OR gate, 5.7... 1st -+ Kf, 2 flip-flop circuit, 6... Inverter. Client: ShinNippon Electric Co., Ltd.

Claims (1)

[Claims] (1) A counter that generates an output signal every time it alternately counts (N-1)/2 and (N+1)/2 input signals for a predetermined odd N frequency division value; A gate circuit generates an output signal whose pulse width is half a cycle of the input signal by inputting the output signal and the input signal of this counter, and a trigger is generated by the leading edge of the output signal generated from this gate circuit. a first flip-flop circuit,
a second flip-flop circuit triggered by the trailing edge of the output signal generated from the gate circuit;
1. A frequency dividing circuit comprising: a gate circuit that generates a branch signal by performing a logical sum on the output signal of the second fritz-flop circuit.