JPH076082A - Address generating device - Google Patents

Abstract

PURPOSE:To provide the address generating device which efficiently transfer data by generating two different addresses by at least one address register and using those addresses as addresses of a 1st data memory and a 2nd data memory. CONSTITUTION:This address generating device is equipped with an instruction register 20 which analyzes an instruction, an address register 8 which stores address information, a 1st address allocation unit 7 which generates an address on the basis of information on the instruction code analyzed by the instruction register 20, and a 1st address output unit 22 and a 2nd address output unit 23 which convert the addresses of the 1st address allocation unit 7 and 2nd address allocation unit 10 on the basis of the instruction code of the instruction register 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital computer having a plurality of data memories and performing arithmetic processing based on the contents of the data memories, and more particularly to an address generator for designating an address of the data memories.

[0002]

2. Description of the Related Art Due to advances in semiconductor technology and microprocessor architecture, the memory space of a processor is divided into a program memory space and a data memory space, and RISC processor and digital signal processor adopting Harvard architecture for speeding up instruction execution. (Hereinafter referred to as DSP) is being put to practical use.

Particularly, the DSP can be easily realized on one chip, and the processing by the DSP can perform highly accurate processing as compared with the analog signal processing, and the setting of the parameter allows an arbitrary filter characteristic or the like. It is possible to obtain stable and uniform characteristics. Further, the use of the DSP has a feature that it is not necessary to perform fine adjustment due to the precision of parts as compared with the analog configuration, and is rapidly spreading. The application range of the DSP is used in a wide range of digital signal processing such as audio signal processing, communication signal processing, measurement signal processing, image signal processing, and sound processing.

When the above-mentioned digital signal processing is performed by the DSP, as shown in equation (1),

[0005]

[Equation 1]

Coefficient (corresponding to ai and bi in the equation (1))
And the data (corresponding to xi and yi in the equation (1)) are mostly used, and the data is stored in the data memory, while the coefficient is written in the data memory in advance as immediate data. A digital computer for performing such a sum of products operation is disclosed in Japanese Patent Laid-Open No. 63-303452.

FIG. 9 is a schematic configuration diagram of an address generating device in a conventional digital computer.

In FIG. 9, 1 is a first data memory in which data and the like are stored, 2 is a first address bus through which a signal designating an address of the first data memory 1 passes, 3
Is a first data bus for exchanging data in the first data memory 1, 4 is a second data memory in which coefficients used for calculation are stored, and 5 is an address of the second data memory 4. A second address bus through which signals pass, a second data bus 6 for communicating data between an accumulator 16 and a second data memory 4 described later, and a first data bus 7 for designating an address of the first data memory 1. An address allocation unit, 8 is a first address register that stores an address value that is a basis of an address generated by the first address allocation unit 7, and 9 is used together with the first address register 8, A first offset register 10 that stores an increase / decrease value for the address value of the address register 8 is a second data memory 4
Second address allocation unit that specifies the address of the address, 11 is a second address register that stores the address value that is the basis of the address generated by the second address allocation unit 10, and 12 is the second address register. A second offset register which is used together with 11 and stores an increase / decrease value for the address value of the second address register 11, 13 and 14 via the first data bus 3 or the second data bus 6. The first and second data registers for reading and storing the value of the first data memory 1 or the second data memory 4 on the basis of the data sent by the first and second data memories 15, 15 is the first data register 1
3, a multiplier that multiplies the data value of the second data register 14, 16 is an accumulator that stores the result of multiplication by the multiplier 15, 17 is a system clock that becomes a clock pulse wave of the DSP, and 18 is the next execution Counter, which stores the address of the program to be saved, 1
9 is a program memory in which programs such as instruction codes are stored, 20 is an instruction register in which instruction codes are stored and analyzed, and 21 is a program bus for transferring program data.

FIG. 10 shows a program including an instruction for performing an operation using a data memory.

N-10, ..., N-1, in FIG.
n, n + 1, and n + 2 indicate addresses of the program memory 19, and the boxes indicate programs corresponding to the addresses. Further, A0, A1, C0, C1, R0, R1, and Acc are respectively a first address register 8, a second address register 11, a first offset register 9,
The second offset register 12, the first data register 13, the second data register 14, and the accumulator 16 are shown.

<Load A0,2000 at address n-9
H>, n <address C0,200H>, n-7, n
<Load A1, 2000H> at address -5 and <load C1, 100H> at address n-3 are the addresses next to the addresses at which the instruction codes are stored in registers A0, C0, A1, C1, for example, n- The address 9 is a machine language meaning that it is an instruction to store the data stored in the address n-8.

<Move R0, (A0)> at address n-1
Is a machine language meaning that it is an instruction to transfer the contents of the address shown in the first address register 8 to the first data register 13, <move R1, (A1 at address n
+ C1)> is an instruction to transfer the contents stored at the address indicated by the sum of the address indicated by the second address register 11 and the address indicated by the second offset register 12 to the second data register 14. Is a machine word that means, <mac R0, R1> at address n + 1 is the first
Contents of the data register 13 of the second data register 1
<Move, a machine language meaning that the instruction is to multiply the contents of 4 and perform cumulative addition with the contents of the accumulator 16.
(A0 + C0), Acc> indicates the contents of the accumulator 16 with the address indicated by the first address register 8 and the first address.
Is a machine language meaning that the instruction is to be transferred to the address indicated by the sum of the addresses indicated by the offset register 12.

FIG. 11 is a timing chart when the program shown in FIG. 10 is operated in the digital computer shown in FIG. CLK is the system clock 1
7 waveform, PCQ is a waveform output from the program counter 18, IRQ is a waveform of an instruction code output from the instruction register 20, ARO is a waveform of an address output from the first address register 8, and AR1 is a second waveform. The waveform of the address output from the address register 11, CR0 is the waveform of the address output from the first offset register 9, CR1 is the waveform of the address output from the second offset register 12, and AALU0 is the first address allocation. The waveform of the address generated by the unit 7, AALU1 is the waveform of the address generated by the second address allocation unit 10, XR0
Is the waveform of the first data register 13, XR1 is the waveform of the second data register 14, and ACCR is the accumulator 1
6 is a waveform showing the contents of No. 6.

Here, the content of the first address register 8 is 2000H and the content of the first offset register 9 is 2.
00H, the content of the second address register 11 is 2000
H, the content of the second offset register 12 is 100H,
Assume that the contents of address 2000H of the data memory are 500, the contents of address 2100H of the data memory are 30, and the contents of accumulator 16 are 5000, which will be sequentially described below according to the flow of the program.

The instruction <load A0, shown in FIG.
The address n-9 of 2000H> enters the program counter 18 in synchronization with the rising edge (hereinafter referred to as CLK) A of CLK. Address n to the program counter 18
When -9 is entered, an instruction code is output from the program memory 19, and the instruction code is read into the instruction register 20 in the instruction register 20 in synchronization with CLK B. At the same time, the instruction register 20 reads the instruction code <load A0, 20
Decoding that 00H> is an instruction for storing 2000H in the first address register 8, the value of the program counter 18 is updated to n-8.

Further, in synchronization with CLK C, the data stored in the program memory 19 at address n-8 <20
00H> is stored in the first address register 8 via the program bus 21.

Similarly, <200H is stored in the C0 register.
>, A1 register <2000H>, C1 register <
100H> is stored.

The address n-1 of the instruction <move R0, (A0)> is synchronized with CLK D and the program counter 1
Enter 8. When the address n-1 enters the program counter 18, an instruction code is output from the program memory 19, and the instruction code is output to the instruction register 20.
Is read into the instruction register 20 in synchronization with CLK D.

Next, in synchronization with CLK E, the value of the program counter 18 is updated to n, and at the same time, the instruction register 20 stores the instruction code <move R0,
(A0)> decodes that it is an instruction to transfer the data stored in the first data memory 1 to the first data register 13 in accordance with the address shown in the first address register 8.

The address n is synchronized with CLK F.
Instruction code stored in the address <move R1,
(A1 + C1)> is read into the instruction register 20 and decoded. Furthermore, the instruction code <move
R0, (A0)> is executed. The execution of instructions will be described below.

The instruction decoded in the instruction register 20 is transmitted to the first address allocation unit 7 via a control signal (not explicitly shown). The first address allocation unit 7 is
In synchronization with CLK F, the address <2000H> is read from the first address register 8 and output on the first address bus 2. When the address on the first address bus 2 is determined, the first data memory 1 outputs the data <500> stored at the address to the first data bus 3. The first data register 13 uses CLK
In synchronization with G, the contents on the first data bus 3 <500>
Read. Therefore, in the first data register 13,
The data <500> stored at the address 2000H of the first data memory 1 is stored. Further, the second address allocation unit 10 reads the address <2000H> from the second address register 11, and further reads the address <100H from the second offset register 12.
> Is read, the above two addresses are added, and the address <
2100H> and output to the second address bus 5.

When the address on the second address bus 5 is determined, the second data memory 4 outputs the data <30> stored at the above address to the second data bus 6. The second data register 14 reads the content <30> on the second data bus 6 in synchronization with CLKH. Therefore, the second data register 14 stores the data <30> stored at the address 2100H of the second data memory 4.

In synchronization with CLK I, the instruction <mac R
0, R1> is executed. Since the instruction decoded in the instruction register 20 is a multiplication instruction,
Contents of the first data register 13 in the multiplier 15 <
500> and the contents <30> of the second data register 14 are read, multiplication is performed, and the multiplication result <15000> is stored in the accumulator 16 as the calculation result. This operation result is added to the data <5000> already stored in the accumulator 16 and stored in the accumulator 16 as the data <20000>.

Next, in synchronization with CLK J, the instruction <mo
ve (A0 + C0), Acc> is executed. The instruction decoded in the instruction register 20 is the first
Of the first address allocation unit 7, the first address allocation unit 7 reads the address <2000H> from the first address register 8 and further the address <2H from the first offset register 9.
00H> is read, the above two addresses are added, and the address <2200H> is output to the first address bus 2.

On the other hand, the accumulator 16 outputs the stored data <20000> onto the first data bus 3. Address on first address bus 2 <2200
H> and the data <20000 on the first address bus 2
> Is determined, the first data memory 4 stores the data <20000> in the area corresponding to the above address.
Therefore, the data at the address 2200H in the first data memory 1 becomes <20000>.

[0026]

When performing the above product-sum operation, the address of the first data memory 1 in which the data is stored and the second data in which the coefficient and the like are stored. The addresses of the memories 4 are respectively stored in the address registers, and the address information is used to read the data from the first data memory 1 and the second data memory 4 into the data registers, and then the multiplier is operated. Is being done.

Therefore, in order to perform these calculations, it is necessary to store the corresponding address information in the address register in advance. Usually, such address information is stored in the program memory 20 as immediate data, so one instruction cycle is required to store the address information in one address register, and it takes a lot of time to set the address register. I was trying.

On the other hand, since cumulative multiplication by data and coefficient is provided with hardware capable of executing in one instruction cycle, when performing multiplication, the data and coefficient used for multiplication are compared with the actual multiplication time. There is a problem in that it takes a lot of time to store the data in the data register, which makes it difficult to perform efficient calculation.

Therefore, the present invention has been made in view of the above-mentioned problems, and one address register is used to
It is an object of the present invention to provide an address generator capable of setting an address of each of two address allocation units.

[0030]

In order to solve the above-mentioned problems, an address generator of the present invention comprises an address register for storing address information, an offset register for storing an increment / decrement value of the address register, and an address. A first address allocation unit for generating an address from the address values of the register and offset register;
A second address allocation unit that generates a second address from the address values of the address register and the offset register, and selection information of the address register and the offset register are stored for the first and second address allocation units. A status register, a first address output unit for selectively outputting address information output by the first address allocation unit, and a second address output unit for selectively outputting address information output by the second address allocation unit. By including the address output unit, it has a function of generating the addresses of the first data memory and the second data memory by a set of address registers and offset registers.

[0031]

According to the above means, when an instruction for accessing the data memory is read from the program memory into the instruction register, the instruction register decodes the instruction. At the time of executing the instruction, by the address selection information of the instruction register,
By determining the address to be generated by the address output unit, two sets of address information are generated by at least one set of address registers.

[0032]

【Example】

[First Embodiment] FIG. 1 is a schematic block diagram of a first embodiment of a digital computer equipped with an address generating device of the present invention. In FIG. 1, it has the same function as that of FIG. Are denoted by the same reference numerals, and description thereof will be omitted.

The present invention is different from the conventional example in that the first address output unit 22 is provided between the first address allocation unit 7 and the first data memory 1 and the second address output unit 22 is further provided.
That is, the address output unit 23 is provided between the second address allocation unit 10 and the second data memory 4. Thus, the first address output unit 22 and the second address output unit 23 output from the first address allocation unit 7 and the second address allocation unit 10 according to the instruction code decoded in the instruction register 20. It has a function to gate the address information to be
The address output unit 22 of the first data memory 1
And the second address output unit 23 makes it possible to access all address spaces to the second data memory 4 and the first address allocation unit 22.
Simultaneously accesses the first data memory 1 and at the same time
When the address allocation unit 23 of (1) accesses the data, the address of the second data memory 4 is designated, and the address is set to efficiently perform the data transfer.

In the first embodiment, the address space of the first data memory 1 is 0 to 3FFFH and the address space of the second data memory 4 is 4000H to 7FFFH.
And Here, XXXXXH represents a hexadecimal number.

FIG. 2 shows an example of a program of a digital computer provided with the address generating device of the present invention, <mov
e R0, (A0), R1, (A0 + C0)> is A0
It is a machine language meaning that it is an instruction to transfer the data stored in the address indicated by 1 to the R0 register and at the same time, transfer the data stored in the address indicated by A0 + C0 to the R1 register.

FIG. 3 shows a timing chart when the program shown in FIG. 2 is executed. In FIG. 3, waveforms having the same functions as those of FIG. Is omitted.

AOUT0 is the waveform of the first address output from the first address output unit 22, AOUT1
Is the second address output from the second address output unit 23.
Is the waveform of the address.

FIG. 4 shows the contents of the instruction code in the instruction register 20 and a part of the instruction code when the program shown in FIG. 2 is executed. ARS
0 and ARS1 each have a 2-bit structure.
0 and ARS1 are 0, the first address allocation unit 7 and the second address allocation unit 10 select the value of the first address register 8, while ARS0 and ARS1 are 1. The first address allocation unit 7 and the second address allocation unit 10 select the value of the second address register 11, and when ARS0 and ARS1 are 2, the first address allocation unit 7 and the second address allocation unit 7 are selected. Address allocation unit 10 selects the address of the sum of the value of the first address register 8 and the value of the first offset register 9, and if ARS0 and ARS1 are 3, the first address allocation unit 7, The second address allocation unit 10 has a second address register. Means to select a value and the address of the sum of the value of the second offset register 9 of motor 11. Further, DM means whether or not the instruction code is a dual data transfer instruction, and when DM is 1, it is a dual data transfer instruction.

FIG. 5 is a schematic block diagram of the first address output unit 22. 221 is an address area designating unit for designating an address stored in the memory space area of the first data memory 1, and 222 is a first address allocation unit when the DM signal of the instruction code is a dual data transfer instruction. The address area determination unit 223, which determines whether the address output by 7 belongs to the range of the address area specification unit 221, the address area determination unit 222 is an address area determination unit 222.
Is an address conversion unit that newly generates an address when it determines that the address output from the first address allocation unit 7 is out of the range.

FIG. 6 is a schematic configuration diagram of the second address output unit 23. Its function is the same as that of the first address output unit 22.

The operation of the digital computer shown in FIG. 1 for the program shown in FIG. 2 will be described with reference to the timing chart of FIG. The storage of the address information in the first address register 8 and the first offset register 9 is the same as that in the conventional example, and therefore its description is omitted.

The value of the program counter 18 is updated to n in synchronization with CLK K. In synchronization with CLK L,
The instruction register 20 is the program memory 1
Instruction code stored at address n of 9 <move R
0, (A0), R1, (A0 + C0)> is read, and the instruction code is stored in the A0 register at the same time as the dual data transfer instruction (the data stored in the address indicated by the A0 register is transferred to the data register R0). The address value is the sum of the address stored in the C0 register and the address stored in the C0 register, and the data stored therein is transferred to the data register R1). Further, the value of the program counter 18 is n + 1
Will be updated.

First address allocation unit 7
Reads the address selection information ARS0 from the instruction code. Address selection information AR read from the instruction code
Since S0 means that the value <2000H> stored in the A0 register is used as the output information of the first address allocation unit 7, the first address allocation unit 7 sets <2000H> as the value of AALU0.
Is output.

Second address allocation unit 1
0 reads the address selection information ARS1 from the instruction code. Address selection information A read from the instruction code
RS1 is the value stored in the A0 register <2000H>
<2100H>, which is the sum of the value <200H> stored in the C0 register and the value <2100H>, is used as the output information of the second address allocation unit 10. Therefore, the second address allocation unit 10 sets the value of AALU1 as <2200H> is output.

On the other hand, the instruction register 20 transfers the fact that the decoded instruction code is the dual data transfer instruction to the first address output unit 22 and the second address output unit 23. In the address area designating section 221 of the first address output unit 22, data (0-
3FFFH) is stored. Address area determination unit 2
22 is an address <2000H output from the first address allocation unit 7 based on the above two information.
> Is the address space of the first data memory 1 (0-3FF
FH), the output <2000H> of the first address allocation unit 7 remains unchanged, and the output AOUT0 of the first address output unit 22 remains unchanged.
<2000H> is output.

On the other hand, in the address area designating section 231 of the second address output unit 23, the data (4000H-7FF) already indicating the address area of the second data memory 4 is already stored.
FH) is stored. Address area determination unit 232
Is an address value <2200H output from the second address allocation unit 10 according to the above two information.
> Is the address space of the second data memory (4000H-
7FFFH), it is notified to the address conversion unit 233. Address conversion unit 233
Represents the address value <2200H> output from the second address allocation unit 10 as the corresponding address <6200H = 2200H + 4000H> in the address space (4000H to 7FFFH) of the second data memory 4.
And output.

The first data memory 1 and the second data memory 4 are the first address bus 2 and the second data memory 4, respectively.
When the address of the address bus 5 is determined, the first data bus 3 and the second data bus 6 change the values stored at the specified addresses to the first data bus 3 and the second data, respectively. Output on bus 6. In synchronization with CLK N, the first data register 13 is connected to the first data bus 3
Value <500> of the second data bus 6 and the second data register 14 takes in the value <30> of the second data bus 6.

The operation of the instruction code <mac R0, R1> is the same as that of the conventional example, and therefore its explanation is omitted. When the instruction code <move (A0 + C0), Acc> is decoded in the instruction register 20, the instruction register 20 transfers to the first address allocation unit 7 that it is a single data transfer instruction. First address output unit 2
2 determines that the output <2200H> of the first address allocation unit 7 exists in the address space (0-3FFFH) of the first data memory 1. Since the instruction decoded by the instruction register 20 is a single data transfer instruction, the first address output unit 22 specifies the address for accessing the space of the first data memory 1. Therefore, the first address output unit 22 outputs the output of the first address allocation unit 7 <2200H in synchronization with CLK O.
> Is output as it is as the address of the first data memory 4. When the address of the first data memory 1 is determined, the value A of the accumulator 16 is synchronized with CLK P.
cc <20000> is 2200H of the first data memory
It is stored in the address.

[Second Embodiment] FIG. 7 is a schematic block diagram of a digital computer according to a second embodiment of the present invention. In FIG. 7, those having the same functions as those of FIG. The same numbers are attached and the description thereof is omitted.

The present invention is different from the conventional example and the first embodiment in that the first address multiplexer 24 is provided between the first address register 8 and the first address allocation unit 7, and the first address multiplexer 24 is also provided. An offset multiplexer 25 is provided between the first offset register 9 and the first address allocation unit 7, a second address multiplexer 26 is provided between the second address register 11 and the second address allocation unit 10, and The second offset multiplexer 27 is provided between the second offset register 12 and the second address allocation unit 10, respectively.

The first address multiplexer 24 and the second address multiplexer 26 are arranged in either the first address register 8 or the second address register 11 based on the address selection information of the instruction code. Select the output, first offset multiplexer 2
5 and the second offset multiplexer 27, based on the address selection information of the instruction code, the first offset register 9 or the second offset register 12
Select one of the outputs.

FIG. 8 is a program showing the contents of the second embodiment.

In the instruction register 20, the instruction code <move R0, (A0), R1,
(A1 + C1)> is decoded, and the instruction code ASR0 is set to 0, ASR1 is set to 3, and DM is set to 1. Instruction code <move R0, (A0), R1, (A1 + C1)
The case where> is executed will be described. When the instruction is executed, the first address multiplexer 24 refers to the instruction code ASR0 and selects either the output AR0 of the first address register 8 or the output AR1 of the second address register 11. On the other hand, the first offset multiplexer 25 refers to the instruction code ASR0 and outputs the output CR0 of the first offset register 9 or the second offset register 9.
Any one of the outputs CR1 of the offset register 12 is selected.

Since the instruction code ASR0 is 0, the first address multiplexer 24 selects the output AR0 of the first address register 8 and the first offset multiplexer 25 selects the output CR0 of the first offset register 9. . Instruction code of instruction register 20 <move R0, (A0), R1, (A1 + C1)>
Means that the contents of the address indicated in the first address register 8 are stored in the first data register 13, so that the first address allocation unit 7
Outputs the output AR0 of the first address multiplexer 24. Since ASR1 is 3, the output AR1 of the second address register 11 is selected in the second address multiplexer 26, and the output CR0 of the second offset register 12 is selected in the second offset multiplexer 27. It The second address allocation unit 10 includes a second address register 11
And the address shown in the second offset register 12 is output.

As described above, by adding the function for efficiently generating the address, the address register,
Also, it becomes possible to reduce the number of instructions for reading a constant into the offset register.

In this embodiment, the first address multiplexer 24 is the first address register 8, the first offset multiplexer 24 is the first offset register 9, and the second address multiplexer 26 is the second. , The second offset multiplexer 27 selects the second offset register 12. However, the above selection can be arbitrarily selected according to the content of the instruction code. Also, the number of inputs to each offset multiplexer is not limited to two, and at least two or more inputs can be selected.

[0057]

As is apparent from the above description, the present invention provides the address output unit so that the address output unit converts the address into the address of the corresponding data memory according to the contents of the status register. This makes it possible to generate two different addresses with one address register and one offset register. Therefore, it is possible to reduce the number of instructions for reading the address information into the address register to specify the address of the data memory, so that it is possible to speed up the operation and reduce the program capacity.

Further, by providing a plurality of address registers and selecting them in the address multiplexer and the offset multiplexer according to the content of the instruction code, it is possible to generate addresses in various combinations, reducing the number of instructions, and Efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a digital computer including an address generation device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a program including a data transfer instruction in a digital computer provided with the address generation device of the present invention.

FIG. 3 is a diagram showing a timing chart when a data transfer instruction is executed in a digital computer provided with the address generation device of the present invention.

FIG. 4 is a diagram showing the contents of an instruction code, which is a feature of the present invention.

FIG. 5 is a configuration diagram of a first address output unit that is a feature of the present invention.

FIG. 6 is a configuration diagram of a second address output unit that is a feature of the present invention.

FIG. 7 is a schematic configuration diagram of a digital computer including an address generation device according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a program including a data transfer instruction in a digital computer provided with the address generation device of the present invention.

FIG. 9 is a schematic configuration diagram of a digital computer including a conventional address generation device.

FIG. 10 is a diagram showing a program including a data transfer instruction in a digital computer having a conventional address generation device.

FIG. 11 is a diagram showing a timing chart when a data transfer instruction is executed in a digital computer having a conventional address generation device.

[Explanation of symbols]

 1 1st data memory 2 1st address bus 4 2nd data memory 5 2nd address bus 7 1st address allocation unit 8 1st address register 9 1st offset register 10 2nd address allocation unit 11 Second Address Register 12 Second Offset Register 20 Instruction Register 22 First Address Output Unit 23 Second Address Output Unit 24 First Address Multiplexer 25 First Offset Multiplexer 26 Second Address Multiplexer 27 Second Offset multiplexer

Front page continuation (72) Inventor Akira Yoshida 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (3)

[Claims] 1. An instruction register for reading and decoding an instruction, a first data memory in which data used for operation is stored, and data different from the data stored in the first data memory are stored. The second
Data memory, and a first address allocation unit for generating an address of the first data memory,
A second address allocation unit that generates an address of the second data memory, an address that stores an address that is a basis of an address that is generated by the first address allocation unit and the second address allocation unit. A register, a first address output unit for selectively outputting the address output by the first address allocation unit, and a second address output for selectively outputting the address output by the second address allocation unit. A unit,
In the data transfer, the first address output unit outputs the first address output unit by the first address allocation unit based on the address selection information of the instruction code decoded by the instruction register.
Of the first data memory, and the second address output unit outputs the address of the second data memory output by the second address allocation unit. An address generator, which generates two sets of addresses corresponding to addresses of a data memory. 2. An offset register, which is used as a pair with the address register and stores an increase / decrease value of the address register, wherein the first address allocation unit and the second address allocation unit include the address register. And the address is generated based on the output of the offset register. 3. An instruction register for reading and decoding an instruction, a first data memory in which data used for operation is stored, and data different from the data stored in the first data memory are stored. The second
Data memory, and a first address allocation unit for generating an address of the first data memory,
A second address allocation unit that generates an address of the second data memory; a first address register that stores an address that is a basis of an address that is generated by the first address allocation unit; A second address register that stores an address that is the basis of an address generated by the second address allocation unit and the first address register are used as a pair, and the increase / decrease value of the first address register is stored. A first offset register and a second address register, which are used as a pair with the second address register, and store an increase / decrease value of the second address register; and the first address register,
Or the first to select the output of the second address register
Address multiplexer, and a second address multiplexer, and a first offset multiplexer that selects an output of the first offset register or the second offset register, and a second offset multiplexer. Based on the address selection information of the instruction code decoded by the instruction register, the first address multiplexer and the second address multiplexer select the output of the first address register or the second address register. In addition, the first offset multiplexer and the second offset multiplexer select the output of the first offset register or the second offset register.