JPH0763143B2 - Semiconductor boost signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor boost signal generating circuit in a MOS integrated circuit.

[Conventional technology]

Conventionally, a boost signal generating circuit of this type has been shown in FIG. In this figure, φ _A is the boosted signal,
Is the load capacitance of the boosted signal φ _A , and its value is C ₁ . φ _B is a boosting signal, 19 is a boosting capacitance, and its value is C ₂ .

FIG. 5 is a waveform diagram of the boosted signal φ _A and the boosted signal φ _B during the operation of the boosted signal generation circuit shown in FIG.

Next, the operation will be described with reference to FIG.

First, at time t ₅ , the boosted signal φ _A starts charging the load capacitor 18 and the boost capacitor 19. Next, at time t ₆ , the potential of the boosted signal φ _A becomes the power supply voltage V or a potential slightly lower than the power supply voltage V. Next, between time t ₆ and time t ₇ , the boosted signal φ _A and boosted capacitor 19 boost the boosted signal φ _A to the power source voltage V or higher. The maximum boost value of the boosted signal φ _A is Is.

In this way, the boosted signal φ _A is boosted by the boosted signal φ _B and applied to the load capacitance 18.

[Problems to be solved by the invention]

In the conventional boost signal generating circuit as described above, in order to obtain a high boost potential, the value of C ₂ of the boost capacitor 19 must be increased, power consumption increases due to charging of the boost capacitor 19, and There is a problem that the time interval t ₆ −t ₅ must be lengthened.

The present invention has been made to solve such a problem, and an object thereof is to obtain a semiconductor boost signal generating circuit that generates a boost signal at high speed and low power consumption.

[Means for solving problems]

A semiconductor boost signal generating circuit according to the present invention is an N-type MOS transistor which is connected between a high-potential power supply node and a connection node and has a gate electrode to which a first signal is applied.
A channel type MOS transistor, an N channel type MOS transistor which is a second MOS transistor connected between the connection node and the low potential power supply node, and a second signal is applied to the gate electrode, and a boosted potential is applied to the output node. A boosted potential generating device to be generated, a P-channel type MOS transistor which is a third MOS transistor connected between an output node and an output side of the boosted potential generating device and having a gate electrode connected to the connection node, and One electrode is connected to the gate electrode of the P-channel MOS transistor which is the third MOS transistor, and a capacitor to which the third signal is applied to the other electrode, and is connected between the output end and the low potential power supply node. And a fourth MOS to which a fourth signal is applied to the gate electrode
It is composed of an N-channel type MOS transistor which is a transistor.

[Action]

In the present invention, the first MOS transistor and the second M
The third MOS is connected between the OS transistors, to the gate of the third MOS transistor, and by the charge accumulated in the capacitor
The gate of the transistor is changed to the fourth MO by the fourth signal.
The gate of each S-transistor is controlled, and the third MOS
A boost signal is generated between the transistor and the fourth MOS transistor.

〔Example〕

FIG. 1 is a diagram showing the configuration of an embodiment of the semiconductor boost signal generating circuit of the present invention. In this figure, 1, 2, and 4 are N-channel MO that are the first, second, and fourth MOSFETs, respectively.
S-transistor 3 is a P-channel M that is the third MOSFET
The OS transistor 5 is a capacitor, and its value is C ₁₀ . 6
Is a power supply line, 7 is a GND line, 8 is a boosted potential generator, and its output voltage is V _p . Reference numerals 9 and 10 denote wirings, and wiring 9 electrically connects the source of the N-channel MOS transistor 1, the drain of the N-channel MOS transistor 2, the gate of the P-channel MOS transistor 3 and one electrode of the capacitor 5. . The wiring 10 electrically connects the source of the P-channel MOS transistor 3 and the drain of the N-channel MOS transistor 4. The drain of the N-channel type MOS transistor 1 is connected to the power supply line 6 and the N-channel type MOS transistor is
The sources of 2 and 4 are connected to the GND line 7, and the drain of the P-channel type MOS transistor 3 is wired so that the boosted potential V _p generated by the boosted potential generator 8 is supplied. The portion of the wiring 10 in FIG. 1, that is, the connection point between the source of the P-channel type MOS transistor 3 and the drain of the N-channel type MOS transistor 4 becomes the output terminal of the semiconductor boost signal generating circuit of this embodiment.

Reference numeral 11 is a capacitance equivalently representing the load capacitance of the wiring 9, and its value is C ₂₀ . Reference numeral 12 is a capacitance equivalently representing the load capacitance of the wiring 10, which is a voltage Vp higher than the power supply voltage V, that is,
This corresponds to the load capacitance charged by the boosted signal in the conventional example shown in FIG. 4, and its value is C ₃₀ . Then, the signals φ ₁ , φ ₂ , and φ ₄ , which are the first, second, and fourth signals, are applied to the gates of the N-channel type MOS transistors 1, 2, and 4, respectively, and the other electrode of the capacitor 5 is applied to the other electrode. A third signal, signal φ _3, is applied. The voltage of the power supply line 6 is V. First to fourth signals φ _{1 to} φ
Reference numeral ₄ is a signal for determining the timing of applying the output voltage Vp of the boosted potential generator 8 to the load capacitance 12.

FIG. 2 is a diagram showing a voltage waveform of a main part in FIG.

FIG. 3 is a diagram showing the configuration of an embodiment of the boost signal generator 8 in FIG. In this figure, 13 is a ring oscillator, 14 is a charge pump capacitor, and 15 and 16 are MOS.
The transistor 17 is a potential storage capacitor. One electrode of the charge pump capacitor 14 is connected to the output of the ring oscillator 13, and the other electrode is connected to the source of the MOS transistor 15, the drain and the gate of the MOS transistor 16. The drain and gate of the MOS transistor 15 are connected to a power supply, one electrode of the potential storage capacitor 17 is connected to the source of the MOS transistor 16, and the other electrode is grounded.

Since FIG. 3 is a known circuit, description of its operation is omitted.

Next, the operation of the semiconductor boost signal generating circuit of the present invention will be described with reference to FIG.

First, between times t ₀ and t ₁ , the signals φ ₁ and φ ₄ are set to the threshold voltages V _TH1 and V _TH4 of the N-channel MOS transistors 1 and 4 or less. Next, at time t ₁ , the signal φ ₂ becomes equal to or higher than the threshold voltage V _{TH2 of the} N-channel type MOS transistor 2 and the charges of the capacitors 5 and 11 are discharged, so that the potential of the wiring 9 becomes 0.
Lower to [V]. The P-channel type MOS transistor 3 turns on when the potential of the wiring 9 drops and outputs the boosted potential V _p . At this time t ₁ , the output voltage Vp of the boosted potential generating device 8, that is, a voltage higher than the power supply voltage V is applied to the load capacitance 12 through the P-channel MOS transistor 3. Then, between the times t ₁ and t ₂ , the signal φ ₂ is set to the threshold voltage V _TH2 of the N-channel type MOS transistor 2 or less, and the potential of the signal φ ₃ is also lowered. And time t ₂
, The potential of the signal φ ₁ rises, the N-channel type MOS transistor 1 is turned on, and the potential of the wiring 9 is charged to V−V _TH1 . Next, when the potential of the signal φ ₃ is raised at time t ₃ , the potential of the wiring 9 rises to V ′ _p due to the charges accumulated in the capacitor 5. Regarding the value of V ′ _p , if the amplitude of the signal φ ₃ is V, Given by the formula. Next, at time t ₃ , the signal φ ₄ changes to the threshold voltage V of the N-channel MOS transistor 4.
It becomes _TH4 or more, and the potential of the wiring 10 is set to 0 [V]. Then, the entire state when the potential of the wiring 10 becomes almost 0 [V] becomes equal to the initial state at the time t ₀ . At this time t ₄ , the charge of the load capacitance 12 is the N-channel type MOS.
The voltage of the load capacitance 12 is discharged to the ground potential by the transistor 4.

At this time, by _setting V _p ′> V _p − | V _TH4 |, the P-channel MOS transistor 3
Cuts off, and the current consumption can be almost ignored. Therefore, in this embodiment, the timing of the voltage Vp higher than the power supply voltage V applied to the load capacitance 12 is determined by the first to fourth signals, and when the third transistor 3 is turned on, the load is promptly increased. Since a voltage higher than the power supply voltage V is applied to the capacitor 12 from the boosted potential generator 8, the speed can be increased, and the output voltage Vp from the boosted potential generator 8 only needs to be charged to the load capacitor 12. Therefore, it consumes less power.

〔The invention's effect〕

As described above, the present invention is provided with a first MOS transistor connected between a high potential power supply node and a connection node and having a gate electrode to which a first signal is applied, and between the connection node and a low potential power supply node. Connected to the second gate electrode
A second MOS transistor to which the signal is applied, a boosted potential generator that generates a boosted potential at the output node, and a gate electrode connected to the connection node between the output node and the output side of the boosted potential generator. A third MOS transistor to be connected, a capacitor to which one electrode is connected to the gate electrode of the third MOS transistor, and a third signal is applied to the other electrode, the output terminal and the low potential power supply node. Since the fourth MOS transistor, which is connected to the gate electrode and the fourth signal is applied to the gate electrode, is provided, it is possible to generate the boosted signal at high speed and low power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a semiconductor boost signal generating circuit of the present invention, FIG. 2 is a waveform diagram of a main portion in FIG. 1, and FIG. 3 is a configuration of an embodiment of a boosted potential generator. FIG. 4 is a diagram showing an example of the configuration of a conventional boost signal generating circuit, and FIG. 5 is a waveform diagram for explaining the operation of the conventional boost signal generating circuit. In the figure, 1, 2, 4 are N-channel MOS transistors, 3 are P-channel MOS transistors, 5 are capacitors, 6 is a power supply line, 7 is a GND line, and 8 is a boosted potential generator. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first MO connected between a high-potential power supply node and a connection node and having a gate electrode to which a first signal is applied.
N-channel MOS transistor that is an S transistor, N-channel MOS transistor that is a second MOS transistor that is connected between the connection node and the low-potential power supply node, and has a second signal applied to its gate electrode, and output A boosted potential generator for generating a boosted potential at a node, a P-channel type which is a third MOS transistor connected between an output node and an output side of the boosted potential generator and having a gate electrode connected to the connection node One electrode is connected to the gate electrode of the MOS transistor and the third MOS transistor, and a capacitor to which the third signal is applied is connected to the other electrode, and is connected between the output end and the low potential power supply node. A semiconductor boost signal generating circuit including an N-channel MOS transistor which is a fourth MOS transistor to which a fourth signal is applied to its gate electrode.