JPH0767052B2 - Phase compensation circuit - Google Patents

Description

The present invention relates to an operational amplifier, and more particularly to a phase compensation circuit.

[Conventional technology]

Conventionally, there is what is called lead compensation as the phase compensation of the operational amplifier, and this is to obtain a phase margin by advancing the phase near the unity gain frequency by inserting a resistor in series with the mirror capacitance. . FIG. 5 shows the gain and phase-versus-frequency characteristic of the operational amplifier, 12 is the open gain, 10 is the pre-lead compensation and 11 is the phase-frequency characteristic after the lead compensation. In this example, the phase margin at the unity gain frequency is improved by 35 degrees.

[Problems to be solved by the invention]

In the operational amplifier using the conventional lead compensation described above, a frequency considerably higher than the unity gain frequency, for example, 10 to
There is a drawback that it oscillates at 20 MHz or abnormal peaking occurs, and when this operational amplifier is used in the communication line, it is a problem from the standard of voice in-band noise or out-of-band residual sound.

[Means for Solving Problems] The phase compensation circuit of the present invention adds a mirror compensation capacitance to a local closed loop in the arithmetic amplifier to prevent oscillation at frequencies higher than unity gain and abnormal peaking. is there.

According to the present invention, the base of the first transistor serves as an input terminal, the collector of the second transistor whose emitter is grounded serves as an output terminal, and the emitter of the first transistor serves as the second terminal.
Connected to the base of the first transistor, a resistor and a first capacitor are connected in series between the base of the first transistor and the collector of the second transistor, and the second capacitor is connected between the base and collector of the second transistor. A phase compensation circuit characterized by being connected is obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. It has an inverting input terminal 1, a non-inverting input terminal 2, a positive power supply terminal 3, a negative power supply terminal 4 and an output terminal 5. The input PNP transistors Q ₁ and Q ₂ and the active load NPN transistors Q ₃ and Q ₄ are the first stage. The amplifier of the
The NPN transistors Q ₅ and Q _{6 form} a second-stage amplifier. NP
N transistors Q ₈ and Q ₉ are NPN transistors Q ₇ and P in the output stage.
It is for keeping the NP transistor Q ₁₀ in class AB, I ₁ ,
I ₂ is a constant current source and R ₂ is a resistor that determines the bias current of the transistor Q ₅ . For read phase compensation, a resistor R ₁ is inserted in series with the mirror capacitance C ₁ between the collector of the transistor Q _{6 and} the base of the transistor Q ₅ . Furthermore, a capacitance Cg is added between the base and collector of the transistor Q ₆ .

First, the mechanism of oscillation at high frequency will be described with reference to FIG. The figure, the collector of the first second-stage growth in Figure width unit of the transistor Q _6, Miller capacitance C _1, the base from the base of the transistor Q ₆ of the transistor Q ₅ through the resistor R _1, a local back to the collector Closed loop with transistor Q ₆
It is an equivalent circuit cut by the collector of. 6 is an input terminal of the loop, the output terminal 7, R _IN, C _IN is the input impedance looking into the base direction of the transistor Q ₅ from the resistance R ₁ of FIG. 1, C _D6 is input transistor Q ₆ The capacitance, γo, Co is the output impedance at the collector point of the transistor Q ₆ . The transmission relation H ₆₇ from the terminal 6 to the terminal 7 is expressed by the following equation.

Here, γe ₅ is the output impedance of the transistor Q ₅ .

As an example, γo = 150KΩ, Co = 5pF, R _IN = 1MΩ, C _IN = 5
For pF, C ₁ = 50PF, R ₁ = 3KΩ, γe ₅ = 2KΩ, C _D6 = 4.4pF, each pole is Therefore, at frequencies above 10 KHz, equation (1) becomes Is represented. Here, Ao is about 50 dB in the second stage low frequency gain.
Is. Equation (2) has a three-pole characteristic and has poles f _p3 and f _p2.
Oscillates between and. On the other hand, the present invention is modeled as shown in FIG. Where A ₁ is transistor Q ₅
The emitter follower, A ₂ , represents the grounded emitter amplifier of transistor Q ₆ . By the mirror effect by the capacity Cg,
The transfer function H ₆₇ ′ from terminal 6 to terminal 7 is as follows.

Equation (3) has a two-pole characteristic, and if the value of the capacitance Cg is selected so that f _pg is sufficiently low, a sufficient phase margin can be obtained at the unity gain frequency, and the oscillation in the local loop described above can be avoided. A value of about 5 pF is sufficient for the capacitance Cg. FIG. 4 is a graph showing loop gain / frequency characteristics of the equivalent circuit of FIG. 12 is a loop gain / frequency characteristic without Cg, and it can be seen that it oscillates between 10.6M and 18.1MHz. FIG. 13 shows that the loop gain / frequency characteristic when the capacitance Cg of the present invention is added shows that a sufficient phase margin can be obtained at a unity gain frequency of 10 MHz. Since one end of the capacitor Cg is common to one end of the mirror capacitor, it can be formed using the same insulating region, and the chip area does not increase so much.

[Effects of the Invention] As described above, the present invention stabilizes the frequency characteristic of the local loop by adding another mirror capacitance in the local closed loop in the widening amplifier, and We solved the conventional problems such as high frequency oscillation and peaking. As a result, lead compensation can be performed in the vicinity of the unity gain frequency of the entire operational amplifier, and when the operational amplifier is used as a feedback amplifier, there is an effect that a sufficient phase margin can be taken even if the feedback impedance is high.

[Brief description of drawings]

FIG. 1 is an operational amplifier having phase compensation according to an embodiment of the present invention, FIG. 2 is a partial circuit diagram of an oscillation source in the operational amplifier of FIG. 1, and FIG. FIG. 4 is a circuit diagram modeling the phase compensation circuit of one embodiment, FIG. 4 is a graph showing the loop gain vs. frequency characteristic of the partial circuit, and FIG. 5 is a graph showing the open gain and phase vs. frequency characteristic of the entire operational amplifier. It is a graph shown.

 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-51-93581 (JP, A) JP-A-54-8444 (JP, A) JP-A-59-181808 (JP, A) Actually published 55- 22112 (JP, U) Actual development 56-19913 (JP, U) Actual public 44-31053 (JP, Y1) Special public 59-21205 (JP, B2)

Claims (1)

[Claims] 1. A base of a first transistor is an input terminal, a collector of a grounded second transistor is an output terminal, and an emitter of the first transistor is connected to a base of a second transistor. A resistor and a first resistor are provided between the base of the transistor and the collector of the second transistor.
A phase compensation circuit in which the second capacitor is connected in series, and the second capacitor is connected between the base and collector of the second transistor.