JPH0770231B2 - Electrically erasable PROM - Google Patents
Electrically erasable PROMInfo
- Publication number
- JPH0770231B2 JPH0770231B2 JP9882387A JP9882387A JPH0770231B2 JP H0770231 B2 JPH0770231 B2 JP H0770231B2 JP 9882387 A JP9882387 A JP 9882387A JP 9882387 A JP9882387 A JP 9882387A JP H0770231 B2 JPH0770231 B2 JP H0770231B2
- Authority
- JP
- Japan
- Prior art keywords
- erase
- erased
- mode
- signal
- electrically erasable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Read Only Memory (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、EEPROM（電気的に消去可能なPROM）に関し、
特に実装状態で書き換えを行なうEEPROMに関する。The present invention relates to an EEPROM (electrically erasable PROM),
Especially, it relates to the EEPROM that is rewritten in the mounted state.
従来のEEPROMは、消去信号が入力されると、無条件に記
憶している内容を消去していた。The conventional EEPROM unconditionally erases the stored contents when an erase signal is input.
上述した従来のEEPROMでは、接続されるCPUが暴走して
消去信号を出した場合でも消去が行なわれ、不用意に内
容が消去されてしまうことがあるという欠点があった。The conventional EEPROM described above has a drawback in that even if the connected CPU runs out of control and issues an erase signal, the data is erased and the contents may be erased carelessly.
上述した従来のEEPROMに対し、本発明はCPUの暴走等に
より、誤って消去信号が印加されても内容の消去が行な
われないという独創的内容を有する。In contrast to the conventional EEPROM described above, the present invention has an original content that the contents are not erased even if an erase signal is applied by mistake due to a runaway CPU.
本発明は、消去信号により記憶内容を消去することがで
きる電気的に消去可能なPROMにおいて、複数の記憶部を
有し、これらの記憶部の各々について記憶内容の消去が
可能なモードと不可能なモードとをセットするモードレ
ジスタと、このモードレジスタに記憶内部の消去が可能
なモードがセットされていて外部から外部消去信号を受
けた時にのみ前記消去信号を出力して記憶内容を消去す
る消去用ゲート回路とを備え、前記複数の記憶部の前記
消去用ゲート回路すべてに接続し前記消去信号が１つで
も出力されれば消去信号を出力する消去検出用ゲート回
路を含むことを特徴とする。The present invention is an electrically erasable PROM capable of erasing stored contents by an erasing signal, has a plurality of storage units, and is capable of erasing stored contents for each of these storage units. A mode register that sets a different mode and a mode in which the internal memory can be erased are set in this mode register, and the erase signal is output only when an external erase signal is received from the outside to erase the stored content. And an erase detection gate circuit which is connected to all the erase gate circuits of the plurality of storage units and outputs an erase signal when at least one erase signal is output. .
第１図は本発明の一実施例のブロック図である。 FIG. 1 is a block diagram of an embodiment of the present invention.
10はEEPROM記憶部で、11と12の各ページに分割される。
31,32はANDゲートで、ANDゲート31がページ11に、ANDゲ
ート32がページ12に接続され、このANDゲート31または3
2から信号“1"が入力されると、そのページ11または12
の記憶内容は消去される。20は、ページ毎に設定された
モードレジスタで、各ページの記憶内容を消去可能とす
る場合は“1"のデータを、消去不可能とする場合は“0"
のデータをページ毎に保持する。40は入力制御ブロック
で、外部より消去信号が入力されると、ANDゲート31,32
の消去すべきページのものに“1"の消去信号を出力す
る。また、制御ブロック40を介して外部よりモードレジ
スタ20のモードセットを行なう。60はANDゲート31,32に
接続されるORゲートで、50は出力バッファでORゲート60
の出力を外部へ伝達する。10 is an EEPROM storage unit, which is divided into 11 and 12 pages.
31 and 32 are AND gates. The AND gate 31 is connected to page 11 and the AND gate 32 is connected to page 12, and the AND gate 31 or 3 is connected.
When the signal “1” is input from 2, the page 11 or 12
The stored contents of are deleted. Reference numeral 20 is a mode register set for each page. When the stored contents of each page can be erased, the data of "1" is set. When it is not possible to erase the data, "0" is set.
Holds the data for each page. Reference numeral 40 is an input control block. When an erase signal is input from the outside, AND gates 31, 32
The erase signal of "1" is output to the page to be erased. Further, the mode of the mode register 20 is externally set via the control block 40. 60 is an OR gate connected to the AND gates 31 and 32, and 50 is an output buffer.
The output of is transmitted to the outside.
外部より、モードレジスタ20のうち消去したくないペー
ジに対応するレジスタに“0"、消去してもよいページに
対応するレジスタに“1"をセットしておけば、誤って消
去信号を入力しても、モードレジスタ20に“0"をセット
した消去不可モードのページは消去されない。また、OR
ゲート60の出力、すなわちバッファ50の出力を観測すれ
ば消去がなされているか否かを知る事が出来る。If "0" is set to the register corresponding to the page which is not desired to be erased in the mode register 20 and "1" is set to the register corresponding to the page which may be erased from the outside, the erase signal is erroneously input. However, the page in the non-erasable mode in which the mode register 20 is set to "0" is not erased. Also OR
By observing the output of the gate 60, that is, the output of the buffer 50, it can be known whether or not the erasure has been performed.
このように本実施例は、ページ毎に消去可能か不可能か
のモードレジスタを有しているので、これに対して消去
したくないページを消去不可能なモードにしておくこと
により、CPUの暴走等による誤消去を防止出来る。As described above, since the present embodiment has the mode register for each page that can be erased or cannot be erased. Accidental erasure due to runaway etc. can be prevented.
また、バッファ50の出力により消去がなされたか否かを
外部より知る事が出来るので、通常使用時には、これを
消去サイクル中に観測すれば、消去したにもかかわらず
消去がされていなかったというミスを防止出来るという
効果がある。Also, since it is possible to know from the outside whether or not the data has been erased from the output of the buffer 50, during normal use, if this is observed during the erase cycle, it is mistaken that it was not erased even though it was erased. There is an effect that can prevent.
以上説明したように本発明は、モードレジスタを設ける
ことにより、このモードレジスタに記憶内容を消去不可
能なモードをセットしておけば、CPU等の暴走等による
誤消去を防止できるという効果がある。As described above, according to the present invention, by providing the mode register, if the mode in which the stored contents cannot be erased is set in this mode register, there is an effect that erroneous erasure due to runaway of CPU or the like can be prevented. .
第１図は本発明の一実施例のブロック図である。 図において、10はEEPROM記憶部、11,12はページ、20は
モードレジスタ、31,32はANDゲート、40は入力制御ブロ
ック、50は出力バッファ、60はORゲートである。FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 10 is an EEPROM storage unit, 11 and 12 are pages, 20 is a mode register, 31 and 32 are AND gates, 40 is an input control block, 50 is an output buffer, and 60 is an OR gate.
Claims (1)
できる電気的に消去可能なPROMにおいて、 複数の記憶部を有し、 これらの記憶部の各々について記憶内容の消去が可能な
モードと不可能なモードとをセットするモードレジスタ
と、このモードレジスタに記憶内容の消去が可能なモー
ドがセットされていて外部から外部消去信号を受けた時
にのみ前記消去信号を出力して記憶内容を消去する消去
用ゲート回路とを備え、 前記複数の記憶部の前記消去用ゲート回路すべてに接続
し前記消去信号が１つでも出力されれば消去検出信号を
出力する消去検出用ゲート回路をを含むことを特徴とす
る電気的に消去可能なPROM。1. An electrically erasable PROM capable of erasing stored contents by an erasing signal, having a plurality of storage units, and a mode in which the stored contents can be erased for each of these storage units. A mode register that sets a possible mode and a mode in which the stored content can be erased are set in this mode register, and the erase signal is output to erase the stored content only when an external erase signal is received from the outside. And an erase detection gate circuit that is connected to all the erase gate circuits of the plurality of storage units and that outputs an erase detection signal if at least one erase signal is output. Characteristically electrically erasable PROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9882387A JPH0770231B2 (en) | 1987-04-21 | 1987-04-21 | Electrically erasable PROM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9882387A JPH0770231B2 (en) | 1987-04-21 | 1987-04-21 | Electrically erasable PROM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63263697A JPS63263697A (en) | 1988-10-31 |
| JPH0770231B2 true JPH0770231B2 (en) | 1995-07-31 |
Family
ID=14230021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9882387A Expired - Lifetime JPH0770231B2 (en) | 1987-04-21 | 1987-04-21 | Electrically erasable PROM |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770231B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03283095A (en) * | 1990-03-29 | 1991-12-13 | Nec Corp | Storage device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS595496A (en) * | 1982-06-30 | 1984-01-12 | Fujitsu Ltd | Memory protect system |
-
1987
- 1987-04-21 JP JP9882387A patent/JPH0770231B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63263697A (en) | 1988-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070731 Year of fee payment: 12 |