JPH077152A - Gallium antimonide field effect transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] Low current, low threshold, high speed operation M
Provide ISFET. In a complementary MISFET, a gate insulating layer is an epitaxial mixed layer formed by a superlattice of a portion in a channel region which is not intentionally doped in order to avoid a boundary state at a gate interface. The mixed layer is aluminum antimonide and aluminum arsenide,
Alternatively, it is composed of layers in which aluminum antimonide and gallium arsenide are alternately formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit using MISFET.

[0002]

2. Description of the Related Art One of the major problems in semiconductor integrated circuits is overheating due to heat generated in the circuits. In order to suppress such heat generation, complementary MIS
The use of FETs has been practiced. As a result, the current is suppressed to a low level and the diffusion of heat is also suppressed. Such complementary circuits include P-type and N-type MISFETs, requiring two types on the same chip as an integrated circuit. Further, an enhancement type field effect transistor is more desirable than a depletion mode type. This is because a transistor that is essentially off in the static state is advantageous in order to reduce the amount of current in the circuit. Another way to avoid overheating is to cool the integrated circuit. The operation at low temperature has an advantage that heat generation of charge carriers, holes and electrons can be suppressed, which enables low noise and low current operation of the integrated circuit and also suppresses heat diffusion.

Another important issue for integrated circuits is to reduce the delay due to transistor switching time. Generally, this time is an active charge carrier (electrons in N-type MISFET, P-type MISFET
The hole in the FET) is determined by the time it takes to cross the channel region. This time depends not only on the channel length but also on the mobility of the active charge carrier.
Therefore, in complementary circuits, the mobility of both electrons and holes is important for shortening the delay and increasing the speed.

A drawback of gallium arsenide when used in complementary circuits is low hole mobility.
This limits the switching speed of the P-type MISFET. This slows the speed of complementary circuits that use gallium arsenide devices.

The mobility of both holes and electrons is relatively high (especially at low temperatures such as 77K).
Gallium antimonide does not have this drawback. As described above, the operation at a temperature lower than room temperature suppresses thermal noise and enables the operation at a low level with respect to the signal.

[0006]

Conventionally, a problem in using gallium antimonide as an active semiconductor in a MISFET is that it is difficult to form a good insulating layer for gate connection to a channel region. . As is well known, in MISFETs, it is important to form an insulating layer for gate connection to a channel region which is relatively boundaryless. These interface conditions prevent the penetration of the electric field supplied for control by the gate voltage during operation and shield the channel. The success factor in silicon MISFETs (especially enhancement mode type) is due to the oxide layer serving as an insulating layer for gate connection, which is relatively interfaceless. For operation at the low threshold levels required to support low signal levels, eg, in the hundreds of volts, interface states need to be less than 10 ¹¹ per cubic centimeter, and preferably 10
Must be less than ¹⁰ However, gallium antimonide does not have this property and requires a different approach.

The resistivity of a semiconductor is related to its bandgap. Thus, a relatively wide bandgap semiconductor can behave as an insulator with respect to a relatively narrow bandgap semiconductor. Therefore, until now MISF
Wide band gap semiconductors have been proposed rather than channel semiconductors for use as ET gate insulating layers. However, in the case of gallium antimonide channels, it was difficult to increase the interface state. This is because the semiconductor layer must contain foreign atoms in order to facilitate lattice matching and to have a predetermined function, and doping for this purpose increases the interface state.

[0008]

The present invention relates to MI using gallium antimonide as an active channel material.
Regarding SFET. Since the MISFET of the present invention forms a mixed gate insulating layer having relatively no boundary state, for example, a superlattice layer in which aluminum antimonide and aluminum arsenide or aluminum antimonide and gallium arsenide are alternately formed is formed. To have. The combined thickness ratio of the two layers is important for lattice matching to the gallium antimonide to suppress interface conditions. The optimum ratio is obtained under the condition that the energy of elastic strain is minimized. A mixed layer of two compounds is a chemical compound at the interface.
Helps avoid Sorder. The superlattice layer mixed layer is formed on the gallium antimonide substrate by the MBE method. And the part closest to the substrate grows without intentional doping. As a result, that part can be relatively free of boundary surface conditions. MISFETs preferentially use enhancement mode channel layers, preferably unintentionally doped. Such a layer has high mobility and sufficiently high resistance. It is used in both N-type and P-type depending on the selection of appropriate source, gate and drain materials.

MISF for operation at low signal levels
It is desirable that ET has a low threshold voltage of, for example, several hundredths of volts. To this end, it is important that the offset voltage between the channel gate electrodes be reasonably low and have an appropriate polarity depending on the type of intended operation. Specifically, the desired offset voltage is obtained by doping the portion closest to the gate electrode and far from the channel. Such limited doping adds little interface state. On the other hand, the desired offset voltage can also be obtained by proper doping of the channel region. This doping will reduce the mobility of the charge carriers, but can be tolerated if the doping is light. Further, the offset voltage is influenced by the selection of the material of the gate electrode.

Anyway, the condition is a voltage condition between the channel and the gate in which the offset is slightly deviated from zero in the absence of the voltage applied to the gate electrode. The offset is a bit negative for the P-type MISFET and a little positive for the N-type MISFET with respect to the gate in order to achieve the desired enhancement mode operation.

Also, in the conventional method, there are source and drain regions on the opposite side of the gate channel. In a P-type MISFET, these regions are fully P-type doped to introduce holes that move from the source to the drain, and the N-type MISSF.
In ET, it is sufficiently N-type doped to introduce sufficient electrons.

[0012]

FIG. 1 shows a P-type enhancement mode MISF.
ET20 and N type enhancement mode MISFET3
3 is a cross-sectional view of an example of the semiconductor chip 10 including 0. FIG. The figure is not to scale; the chip is a combination of each type of transistor.

Chip 10 comprises a gallium antimonide single crystal layer containing the main signal current paths of MISFETs 20, 30. The P-type MISFET 20 has a P-type source region 21 and a drain region 22 with a deliberately undoped semi-insulating gallium antimonide channel region 23 therebetween.

The electrodes 24 and 25 have low resistance contacts to the source region 21 and the drain region 22, respectively. The gate electrode 26 is formed on the channel 2 via the mixed gate insulating layer 28.
It is capacity-connected to 3. The mixed gate insulating layer 28 is a superlattice layer, and is a layer in which an aluminum antimonide layer 28A and a gallium arsenide layer 28B are alternately formed.

The N-type MISFET 30 has an N-type source region 31 and a drain region 32, between which is a channel region 33 of semi-insulating gallium antimonide, which is not intentionally doped. The electrodes 34 and 35 have low resistance contacts to the source region 31 and the drain region 32, respectively. The gate electrode 36 is capacitively connected to the channel 33 via the mixed gate insulating layer 38. The mixed gate insulating layer 38 is a superlattice layer and is a layer in which an aluminum antimonide layer 38A and a gallium arsenide layer 38B are alternately formed. The mixed layers 28, 38 can be formed separately from what was initially formed as a continuous layer.

Chip 10 is made by depositing a gallium antimonide layer by a known MBE method on a suitable substrate such as high purity (100) gallium arsenide (not shown). To improve the quality of the grown layer, it is desirable to first form the buffer layer. The buffer layer includes a gallium arsenide-antimonide ternary compound layer in which the percentage of arsenide is gradually decreased in order to achieve lattice matching between gallium arsenide and gallium antimonide. The first grown portion of gallium antimonide is relatively inactive to the operation of the MISFET, so be careful of lattice defects in this area unless they propagate to the active portion of the later grown gallium antimonide layer. You don't have to. Gallium antimonide is grown without layer doping and is typically a few hundred angstroms thick (though thinner and thicker are possible).

Next, the mixed superlattice layer forming the gate insulating regions 28 and 38 is epitaxially grown. The relative thicknesses of the alternating layers are chosen so that good lattice matching is obtained. Specifically, the aluminum antimonide layer is formed first and the thickness is an integral multiple of 31 atomic layers along the (001) axis. An aluminum arsenide layer is then formed along the same axis with a thickness that is an integral multiple of the diatomic layer. These integer multiples are at least 10 times. If the thickness of the biatomic layer is sufficient, this thickness is used. Generally, each layer has several layers, and each of the layers 28 and 38 has a thickness of several hundred angstroms. This thickness is sufficient to minimize tunneling from the gate electrode to the gallium antimonide and may have a sufficiently low threshold voltage.

The relative thicknesses of the material and the alternating layers are selected to provide an interface between the superlattice layers 28, 38 and the gallium antimonide substrate layer 16 with small chemical order and small lattice mismatch that cause scattering. It is also chosen to give a superlattice with an effective bandgap sufficiently wider than gallium antimonide.

The bandgap of aluminum antimonide is between 1.6 and 1.7 eV and the aluminum arsenide is between 2.2 and 2.3 eV, both Both are higher than 0.7-0.8 eV of gallium antimonide. Furthermore, aluminum antimonide and aluminum arsenide have aluminum as a common cation, and aluminum antimonide and gallium antimonide have antimony as a common anion, so this combination is chemically advantageous. is there.

A combination of an integer multiple of 15 atomic layers of aluminum antimonide and an integral multiple of one atomic layer of gallium arsenide can be used. Perhaps other combinations are possible.

After the gate insulating layer is uniformly formed on the gallium antimonide, it is processed by a known process (photolithography, etching, heat treatment, ion implantation, masking, etc.). Only the basic steps are described below.

Generally, in a complementary integrated circuit, when P-type and N-type MISFETs are formed on the same chip, the two types are processed separately. When one is formed, the other area is masked. Because of the exposure
The P-type device is formed first, and the N-type device forming region is masked. In this example, the resulting MISFET is partially tuned by doping the mixed layers. Doping is performed earlier during the MBE growth of the mixed layer, but is usually performed at this stage. The latter doping is usually performed by ion implantation. It should be noted here that the ion implantation is controlled so that the introduced ions do not cause an undesired interface state in the mixed layer very close to the interface between the gallium antimonide channel region and the mixed layer.

Furthermore, it is desirable to utilize the self-aligned gate process used in the manufacture of complementary silicon MOSFETs. A gate electrode layer such as tungsten is formed on the mixed layer. The gate electrode layer is patterned by photolithography to become the gate electrode 26. The gate electrode 26 includes a source region 21 and a drain region 22.
It serves as a mask when etching the portion of the mixed layer in which is formed.

Next, a P type source region 21 and a drain region 22 are formed on the gallium antimonide from which the mixed layer has been removed. These regions are formed by ion implantation of ions such as beryllium, carbon, and zinc that act as acceptors. As a result, the ion implantation region can be changed to the P type after the heat treatment.

In another example, a protective layer may be formed on the surface to be ion-implanted to minimize surface damage. The amount of ion implantation and the acceleration voltage are selected depending on the concentration of the acceptor to be doped (usually about 10 ¹⁸ per cubic centimeter) and the depth (usually at least 200 angstrom). Next, ohmic contacts 24 and 25 for the source and drain are formed on the P-type regions 21 and 22. A metal, such as a zinc-gold alloy, is formed by vapor deposition and then patterned to leave the contacts 24, 25.
Source and drain contacts are both N-type and P-type M
Since the ISFET is formed in a common process, it may be later in the process.

After formation of the P-type MISFET, these regions are masked and the regions where N-type is to be formed are unmasked. The N-type MISFET is formed by the same method as the P-type, but the necessary material is selected because it is the N-type. In this case, selenium (Se) and sulfur (S) are donors for doping the source and drain. N-type MISFET
Also in this case, control of the gate is performed by ion implantation into the mixed gate insulating layer, and acceptor type ions are used.

The offset voltage of both P-type and N-type is influenced by the gate electrode material. Since the material selection depends also on the characteristics of the mixed layer and the channel region, the best one is selected empirically. Layers of appropriately doped aluminum antimonide, aluminum arsenide, gallium arsenide, etc. are suitable, zinc-gold alloys being used with little effect.

In yet another example, the offset voltage may be controlled by proper doping of the gallium antimonide channel rather than undoping. In this case, the doping of the individual regions should be done before the growth of the mixed gate insulating layer. In addition, various other processes are possible to implement the invention. It is clear that the method using the superlattice of the lattice matching mixed layer used as the insulating layer for the gate connection to the MISFET can be applied to the MISFET using other kinds of semiconductors.

[0029]

As described above, the MISFET using the gallium antimonide of the present invention can be operated at a low current and a low threshold value and can be obtained with little noise.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

[Explanation of symbols]

 10 integrated circuit device 20 P-type MISFET 30 N-type MISFET 23, 33 channel region 26, 36 gate electrode 24, 25, 34, 35 electrode 28, 38 gate insulating layer 21, 31 source region 22, 32 drain region

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H01L 29/43 27/095 7376-4M H01L 29/62 G 7376-4M 29/80 E

Claims (8)

[Claims] 1. A gallium antimonide single crystal member having one conductive and relatively low resistance source and drain separated on one surface by a relatively high resistance channel region, and a gallium antimonide single crystal member formed in the channel region. An epitaxial mixed layer which is an insulating layer and is composed of a superlattice layer, and a portion of the composite layer adjacent to the channel region has no doping in order to avoid an undesired interface state. A gallium antimonide field effect transistor, which is formed in the source / drain region and the mixed layer. 2. The gallium antimonide field effect transistor according to claim 1, wherein the mixed layer is a layer in which aluminum antimonide and aluminum arsenide are alternately formed. 3. The gallium antimonide field effect transistor according to claim 2, wherein the mixed layer is a layer in which aluminum antimonide and gallium arsenide are alternately formed. 4. The gallium antimonide field effect transistor according to claim 1, wherein the threshold voltage of the transistor is determined by the concentration of the dopant in the mixed layer remote from the interface with the gallium antimonide layer. 5. The gallium antimonide field effect transistor according to claim 1, wherein the source and drain regions are P-type. 6. The gallium antimonide field effect transistor according to claim 1, wherein the source and drain regions are N-type. 7. The gallium antimonide field effect transistor of claim 1, wherein the channel region has no intentional doping and is not sufficiently high in resistance to be used as a channel region of a P-type or N-type enhancement mode transistor. 8. A complementary MISFET comprising separate N-type and P-type enhancement mode transistors, both transistors having source and drain regions separated by a semiconductor channel, a gate connection to said channel and a channel. A mixed layer between the gate and gate connections, the mixed layer being essentially free of interfacial states and consisting of a number of layers forming an epitaxial superlattice with an effective bandgap width larger than the channel, whereby the mixed layer is isolated. Complementary MIS, which becomes a layer and produces a small offset voltage between the channel and the gate connection.
FET.