JPH0772189A - Fast Fourier transform analyzer - Google Patents

Abstract

(57) [Abstract] [Purpose] To facilitate the recognition of a waveform satisfying the determination condition by displaying the waveform when the determination condition is satisfied longer than the display time corresponding to the normal screen update rate. [Configuration] Function of performing a fast Fourier transform to perform frequency spectrum analysis and performing a predetermined calculation, further comparing the calculation result with a judgment condition to judge pass / fail, and outputting a judgment result as a signal, data of the calculation result F having a function of generating a data transfer signal representing the timing of sending
It is activated by the FT operation circuit and the signal of the determination result,
A timing circuit that generates a control signal in synchronization with the data transfer signal, and whether the operation data from the FFT operation circuit is stored in the memory and output as it is, or the data temporarily stored in the memory is read and output. A measurement data switching circuit is provided which selects based on the control signal and sends data in synchronization with the data transfer signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast Fourier transform analyzer (hereinafter, a fast Fourier transform is abbreviated as FFT), and more particularly to an FFT analyzer for analyzing a frequency domain. Improvements to make it easier.

[0002]

2. Description of the Related Art Conventionally, an FFT analyzer for analyzing a waveform of a signal under measurement is well known. The FFT analyzer is a frequency analysis measuring instrument used in many fields in vibration and acoustic analysis, servo circuit transfer characteristic analysis, and the like. In such an FFT analyzer,
A spectrum analysis in the frequency domain is performed. Further, as shown in FIG. 4, when a signal of a certain magnitude or more exists in the frequency domain A designated by the user, or conversely, when a signal of a certain magnitude does not exist, etc. Some have a function of detecting and determining.

In such a case, it is judged that the signal in the designated area A is good (normally GO), and the signal is not good (normally NOGO), and the TTL level (transistor logic signal level). ) Signal output, print output, waveform data storage, etc. may be output as a determination result that specifies.

FIG. 5 is a block diagram showing an example of such an FFT analyzer. An analog / digital converter (hereinafter abbreviated as AD converter) 1 converts a signal under measurement into a digital signal in synchronization with an internal sampling clock. The obtained digital data is input to the frequency shift circuit 2.
At this time, if the analysis frequency domain is not baseband,
For example, in the case of 50 KHz to 100 KHz, the input signal is frequency-shifted, and in the case where the analysis frequency is the base band, for example, 0 to 50 KHz, the frequency is not shifted.

The data thinning circuit 4 thins data for zooming in the frequency domain. The digital filter 3 placed between the frequency shift circuit 2 and the data thinning circuit 4 is a low-pass filter that removes signal components in the frequency domain after thinning in order to prevent aliasing noise caused by the operation of the data thinning circuit 4. Acts as a filter.

[0006] The FFT operation circuit 5 performs an FFT operation when a fixed number of data is input from the data thinning circuit 4 to obtain a frequency spectrum, and further performs various operations as necessary to perform power spectrum, transfer function, and other operations. Analyze. Further, GO / NOGO is judged by comparing the judgment condition input by the user with the calculation result. The calculation result is displayed on the display circuit 6. The determination result obtained by the FFT operation circuit 5 is output at the TTL level.

[0007]

However, in the FFT analyzer of this type, it is easy to recognize the measured waveform on the screen of the display circuit 6 only when the measurement rate is slow without outputting these judgment results. However, there is a drawback that it is difficult to recognize the measured waveform when the measurement rate and the screen update rate are high.

In view of the above point, an object of the present invention is to display a waveform when a judgment condition is satisfied, for a time longer than the display time corresponding to the normal screen update rate when the judgment function is provided. Thus, it is intended to realize an FFT analyzer which facilitates the recognition of the waveform satisfying the determination condition.

[0009]

In order to achieve such an object, according to the present invention, a sampled measured object is measured in a fast Fourier transform analyzer capable of displaying the obtained data by analyzing the frequency spectrum of the measured signal. When a fixed number of signal data is input, a function that performs a fast Fourier transform to perform frequency spectrum analysis and performs a predetermined calculation, and a function that compares the calculation result with a judgment condition to judge pass / fail and outputs the judgment result as a signal An FFT operation circuit having a function of generating a data transfer signal indicating a timing of transmitting the operation result data, and a control which is activated by the determination result signal and becomes active for a predetermined time in synchronization with the data transfer signal The timing circuit for generating a signal and the operation data given from the FFT operation circuit are displayed on the display data. A circuit for transmitting as input, selecting whether to output the operation data as it is while storing it in the memory, or to read out and output the data temporarily stored in the memory based on the control signal. It is characterized in that a measurement data switching circuit for transmitting data in synchronization with a transfer signal is provided.

[0010]

When the judgment output is generated, the timing circuit is activated at the trailing edge of the signal, and the control signal which is active for a predetermined time based on the data transfer signal is generated. The measurement data switching circuit operates according to this control signal. That is, when the control signal is not active, the current input data from the FFT operation circuit is output as it is, and when it is active, the stored data immediately before becoming active is read from the memory and sent out. As a result, the same measurement data is repeatedly displayed while the control signal is active.

[0011]

The present invention will be described in detail below. FIG. 1 is a block diagram showing an embodiment of an FFT analyzer according to the present invention. In the figure, the same parts as those in FIG.
Description of equivalent parts is omitted. FF is different from FIG.
A T operation circuit 5a, a measurement data switching circuit 7 and a timing circuit 8.

The FFT operation circuit 5a has a function of generating a data transfer signal representing the timing of data transfer, in addition to the same operation processing function as the conventional one. The measurement data switching circuit 7 has a memory (a readable / writable memory) for storing the measurement data therein, and according to the control signal from the timing circuit 8 and the data transfer signal from the FFT operation circuit 5, the measurement data switching circuit 7 operates. The calculation output is sent to the display circuit 6 as it is (in this case, the memory is in the write mode), or the stored data is read out from the memory and output (in this case, the memory is in the read mode).
This is a circuit for selecting.

The timing circuit 8 is activated by the judgment output output from the FFT operation circuit 5, and generates a control signal to be given to the measurement data switching circuit 7.
In this case, the data transfer signal is counted and the control signal is activated (for example, signal level 1) for a period longer than the measurement rate (for example, a period of two measurement cycles). This is because by extending the active period, the display time of the waveform data satisfying the determination condition is extended.

FIG. 2 shows details of the measurement data switching circuit 7. The buffer circuit 72 receives the output of the FFT operation circuit 5, and the memory 71 stores the output data of the buffer circuit 72 and sends the stored data. Control circuit 73
Is the control signal from the timing circuit 8 and the FFT
It receives a data transfer signal from arithmetic circuit 5 and generates a signal for controlling buffer circuit 72 and memory 71. When the control signal input to the control circuit 73 is 1 (in the memory write mode), the buffer circuit 72 sends out the current input data and stores the current input data every time the data transfer signal becomes active (for example, 1). The output data is written in 71.

On the other hand, when the control signal is 0 (in the memory read mode), the data output of the buffer circuit 72 is prohibited (for example, the output stage of the buffer circuit has a 3-state structure. Output is open). Instead, the stored data (previously stored value) is read from the memory 71 each time the data transfer signal becomes active, and is sent as a data output.

The operation of such a configuration will be described below with reference to FIG. However, here, only the operation relating to the display time of the output data of the FFT operation circuit 5a, which is a feature of the present invention, will be described.

From the FFT operation circuit 5a, as shown in FIG.
As shown in (b), the data N is synchronized with the data transfer signal.
-1, N, N + 1, N + 2, N + 3 ,. ． ． Shall be output.

Write Mode When the control signal ((e) in FIG. 3) output from the timing circuit 8 is 1, the memory mode is the write mode as shown in (d) in FIG. N-1 and N are directly output from the buffer circuit 72 in synchronization with the data transfer signal ((c) in FIG. 3) and input to the display circuit 6. At the same time, the output data is written in the same memory address in the memory 71 (the memory is updated to the latest data). The data display on the display circuit 6 is
Due to the inherent delay time in the display circuit 6, as shown in FIG. 3 (f), the display is made at a timing slightly deviated from the data output timing in FIG. 3 (c).

Read Mode Next, when data N is generated from the FFT operation circuit 5a, FIG.
It is assumed that the judgment output is generated as shown in (g). The timing circuit 8 is activated at the rising edge of the determination output, and makes the control signal active (level 0) during two cycles of the data transfer signal (in other words, two cycles of the measurement cycle, not limited to two cycles). As a result, the memory mode becomes the read mode as shown in FIG. Therefore, the data N + 1,
Although N + 2 is input, it is not output, and instead the stored data (previous value N) is read from the memory 71,
It is given to the display circuit 6. As a result, the data N can be continuously displayed for three cycles of the data transfer signal. That is, the display can be displayed longer than the display time corresponding to the normal screen display update rate. When the control signal that has been 0 for a predetermined period returns to 1,
The operation returns to the write mode operation similar to the above.

In the embodiment, the measurement data switching circuit 7 and the timing circuit 8 are provided separately from the FFT operation circuit 5a, but the present invention is not limited to this. Since the FFT operation circuit 5a is usually constructed by using a digital processing processor, the functions of the measurement data switching circuit 7 and the timing circuit 8 may be realized by a program processed by the processor and a memory around the processor. Good. Further, although the embodiment shows the configuration for one-channel input, the present invention is not limited to this, and can be applied to a multi-channel input.

[0021]

As described above, according to the present invention, even if the waveform when the judgment condition is satisfied is rarely observed, the waveform display is displayed for several cycles, which facilitates the observation. For example, when the measurement rate (display update rate) is 30 cycles / second, one waveform is 33
Although it is displayed only for ms, according to the present invention, this can be continuously displayed for, for example, 10 cycles (330 ms), so that the waveform when the judgment condition is satisfied can be observed very easily.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an FFT analyzer according to the present invention.

FIG. 2 is a configuration diagram showing details of a measurement data switching circuit.

FIG. 3 is a time chart for explaining the operation.

FIG. 4 is an explanatory diagram of a determination region in a power spectrum.

FIG. 5 is a configuration diagram showing an example of a conventional FFT analyzer.

[Explanation of symbols]

 1 AD converter 2 Frequency shift circuit 3 Digital filter 4 Data thinning circuit 5a FFT operation circuit 6 Display circuit 7 Measurement data switching circuit 8 Timing circuit 71 Memory 72 Buffer circuit 73 Control circuit

Claims (1)

[Claims] 1. A fast Fourier transform analyzer capable of displaying the data obtained by analyzing the frequency spectrum of a signal under measurement, and when a fixed number of sampled signal data under measurement is input, the frequency spectrum is obtained by performing a fast Fourier transform. A function of performing analysis and performing a predetermined calculation, a function of comparing the calculation result with a judgment condition to judge pass / fail, and outputting a judgment result as a signal, and a data transfer signal indicating a timing of transmitting the data of the calculation result An FFT operation circuit having a function to perform, a timing circuit activated by a signal of the determination result and generating a control signal which is activated for a predetermined time in synchronization with the data transfer signal, and operation data provided from the FFT operation circuit Is a circuit that sends the A measurement data switching circuit that selects whether to output the data stored in the memory as it is or to read and output the data temporarily stored in the memory based on the control signal, and sends the data in synchronization with the data transfer signal. A fast Fourier transform analyzer characterized in that it is provided.