JPH0773015A - Fixed-point data adder - Google Patents

Abstract

PURPOSE:To reduce the amount of hardware by detecting the case, where a overflow is brought about, from the combination of the number of negatives of operands, the final carries, and the value of the sign part. CONSTITUTION:An addition circuit 1 which adds three fixed-point data A to C expressed by complements of two, an operand negative detecting circuit 2 which detects the number of negatives of operands of data A to C, a final carry generating circuit 3 which generates final carries C0 and C1 from the addition result of data A to C, and an overflow detecting circuit 4 which is connected to circuits 1 to 3 and detects fixed-point overflow from the combination of the number of negatives of operands detected by the circuit 2, carries C0 and C1 generated by the circuit 3, and a sign S of the addition result from the circuit 1 are provided. The case where a overflow is brought about is detected from the combination of the number of negatives of operands, final carries, and the value of the sign part. Thus, overflow is detected with a smaller amount of hardware than conventional at the time of addition of fixed-point data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit for adding three or more fixed point data represented by 2's complement, and more particularly to a fixed point data adder capable of detecting fixed point overflow.

[0002]

2. Description of the Related Art Among the adder circuits for adding three or more fixed-point data represented by two's complement, a conventional fixed-point data adder capable of detecting a fixed-point overflow is provided in an adder. An operation is performed by expanding the sign of the operand to the higher order, and overflow is detected when the sign bit of the result and the expanded bit do not match.

[0003]

As described above, the conventional fixed-point data adder detects the signed fixed-point arithmetic overflow, so that the sign of the operand must be extended to the higher order in the adder. However, it has a drawback that the amount of hardware increases.

[0004]

A fixed-point data adder according to the present invention includes an adder circuit for adding three or more fixed-point data represented by a two's complement, and an operand of the three or more fixed-point data. Operand negative number detection circuit for detecting the negative number of
A final carry generation circuit for generating the final carry of
An overflow detection circuit for detecting a fixed-point overflow by a combination of the negative number of the operand from the operand negative number detection circuit, the two final carries from the final carry generation circuit, and the sign part from the addition circuit. I have it.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The embodiment of FIG. 1 has a 3's representation in 2's complement.
Adder circuit 1 for adding fixed-point data A, B, and C, and operand negative-number detection circuit 2 for detecting a negative number of operands of fixed-point data A, B, and C
Is connected to the adder circuit 1 and the final carry C ₀ and C _{1 is obtained} from the addition result of the fixed point data A, B and C.
And a final carry generating circuit 3 connected to the adder circuit 1 and the final carry generating circuit 3 and the operand negative number detecting circuit 2 for detecting the negative number of the operand detected by the operand negative number detecting circuit 2. An overflow detection circuit 4 is provided for detecting a fixed-point overflow from the combination of the final carry C ₀ and C ₁ generated in _1. and the sign S of the addition result of the addition circuit 1.

Next, the operation of the fixed-point data addition device configured as described above will be described.

A case where overflow occurs when three pieces of fixed-point data represented by 2's complements are added will be considered with a specific example. In the specific example, it is assumed that fixed-point data in 4-bit format is handled, and bit 0 is a code part.

When the data to be handled is X, the expression range of the data X is -8≤X≤7 (Equation 1).

When the number of negative operands is 0, and the input operands are A and B and C, and A, B and C are positive numbers, the range of A, B and C is 0≤A. ≦ 7,0 ≦ B ≦ 7, 0 ≦ C ≦ 7. The result of adding these in the adder circuit 1 is 0 ≦ A + B +
It is within the range of C ≦ 21.

However, since the expression range of the data is limited by the expression (1), the range of 8 ≦ A + B + C ≦ 21 ... Expression (2) cannot be expressed, resulting in overflow.

For example, the addition result F when A = 7, B = 7 and C = 7 is as follows.

[0014]

The expression (2) can be represented by the two's complement as follows.

[0016]

From this, when the upper 3 bits are "010" and "001", it can be determined that the overflow has occurred. That is, the upper 3 bits are C ₀ ,
C ₁ , S (C ₀ and C ₁ are called final carry, and S 1
Is called the sign part), and when the number of negative operands is 0, (C ₀ , C ₁ , S) = ( ₀ , ₁ , 0) and (0, 0,
In case of 1), overflow occurs.

If the operand has one negative number, then A and B and C are the input operands, A is a negative number and B and C are positive numbers.
The range of is −8 ≦ A ≦ −1, 0 ≦ B ≦ 7, 0 ≦ C
≦ 7. The result of adding these in the adder circuit 1 is within the range of −8 ≦ A + B + C ≦ 13.

However, since the expression range of data is limited by the expression (1), the range of 8 ≦ A + B + C ≦ 13 ... Expression (3) cannot be expressed and overflows.

For example, the addition result F when A = -1, B = 7, C = 7 is as follows.

[0021]

The addition result F when A = −6, B = 7, C = 7 is as follows.

[0023]

The expression (3) can be represented by the two's complement as follows.

[0025]

From these, when the number of negative operands is 1, the overflow is (011000) ₂
It can be seen that the range is from (011101) ₂ .

That is, when the number of negative operands is 1, an overflow occurs when (C ₀ , C ₁ , S) = ( ₀ , ₁ , ₁ ).

Similarly, when the number of negative operands is 2, and when the number of negative operands is 3, (C ₀ ,
The combination of C ₁ , S) can be determined.

Table 1 shows the negative numbers of the operands (C ₀ , C ₁ ,
The combination of S) is shown.

[0030]

[Table 1]

From the above results, it is possible to detect the case of overflow from the combination of the negative number of the operand and the final carry and the value of the sign part.

Next, the operation of this embodiment will be described.

The three fixed-point data A, B, and C expressed in 2's complement are input to the adder circuit 1 to perform addition, and the result is output to the final carry generation circuit 3.
The final carry generation circuit 3 generates final carries C ₀ and C ₁ from the information from the adder circuit 1 and outputs them to the overflow detection circuit 4. On the other hand, the operand negative number detection circuit 2 inputs the sign bits of the three pieces of fixed point data A, B and C, detects the negative number of the operand from them, and outputs them to the overflow detection circuit 4. The overflow detection circuit 4 inputs the final carry C ₀ and C ₁ from the final carry generation circuit 3, the negative number of the operand from the operand negative number detection circuit 2, and the sign part S of the operation result of the adder circuit 1. , The overflow is detected by referring to the combinations in Table 1.

The above operation will be described with a specific example.

Three 4-bit fixed point data A, B and C represented by 2's complement are respectively A = 7,
When B = 7 and C = 7, the addition result of these addition circuits 1 is (0101) ₂ . A + B + C
Since = 21> 7, overflow occurs. At this time, the adder circuit 1 outputs the code part S = 0 to the overflow detection circuit 4. The adder circuit 1 also provides the information necessary to generate the final carry with the final carry generation circuit 3.
To the final carry C.
Generate ₀ = 0 and C ₁ = 1. The operand negative number detection circuit 2 inputs the sign bits a ₀ = 0 and b ₀ = 0 and c ₀ = 0 of the operands A, B and C, and detects the negative number = 0 of the operand from them. The overflow detection circuit 4 receives the negative number of the operand = 0 detected by the operand negative number detection circuit 2, the final carry C ₀ = 0 and C ₁ = 1 generated by the final carry generation circuit 3, and the addition circuit 1. Output code part S =
From 0, the overflow is detected by referring to the combination of Table 1.

In the above embodiment, the data width of the input fixed-point data is 4 bits, but the present invention is also applied to the case where the data width is larger, that is, 8 bits, 16 bits or 64 bits. it can.

[0037]

As described above, the fixed-point data adding device of the present invention detects the overflow from the combination of the negative number of the operand and the final carry and the value of the sign part, and thus the conventional method is used. There is an effect that it is possible to detect an overflow when the fixed-point data is added with a smaller amount of hardware, and therefore it is possible to reduce the amount of hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 adder circuit 2 operand negative number detection circuit 3 final carry generation circuit 4 overflow detection circuit

Claims (2)

[Claims] 1. An adder circuit for adding three or more fixed-point data represented by a two's complement, an operand negative number detection circuit for detecting a negative number of operands of the three or more fixed-point data, and A final carry generation circuit connected to the addition circuit to generate a final carry; and an overflow detection circuit connected to the addition circuit, the final carry generation circuit and the operand negative number detection circuit to detect a fixed point overflow. Fixed-point data addition device. 2. An adder circuit for adding three or more fixed-point data represented by a two's complement, an operand negative number detection circuit for detecting a negative number of operands of the three or more fixed-point data, and 2 according to the information from the adder circuit
A final carry generation circuit for generating the final carry of
An overflow detection circuit for detecting a fixed-point overflow by a combination of the negative number of the operand from the operand negative number detection circuit, the two final carries from the final carry generation circuit, and the sign part from the addition circuit. A fixed-point data addition device, comprising: