JPH077342B2 - Microcomputer evaluation device - Google Patents

Description

The present invention relates to a microcomputer evaluation device, and particularly to a microcomputer evaluation suitable for confirming the access status of a memory used for evaluation. It relates to the device.

(B) Conventional Technology A case where a program evaluation is conventionally performed using an evaluation microcomputer having substantially the same function as a mass-production 1-chip microcomputer will be described.

First, when a predetermined address of an external program memory is accessed by a program counter built in the evaluation microcomputer, the program data stored in advance at the predetermined address of the program memory is read into the evaluation microcomputer. On the other hand, when a predetermined address of the external data memory is accessed by the data pointer built in the evaluation microcomputer, the data written in the predetermined address of the data memory is read by the evaluation microcomputer. As a result, the internal circuit of the evaluation microcomputer operates based on the program data and processes the fetched data.

Here, a control circuit is provided for the evaluation microcomputer. That is, the control circuit is preset with address data of a predetermined address of a program memory for which program evaluation is desired, and the control circuit stores address data by a program counter in the evaluation microcomputer together with the program memory. It is designed to be applied. Therefore, when the address data from the evaluation microcomputer is applied to the control circuit and the address data matches the predetermined data in the control circuit, a temporary stop signal is generated from the control circuit. The operation of the evaluation microcomputer will be temporarily stopped. At this time,
The program evaluation is performed by analyzing whether or not the data obtained from the evaluation microcomputer is normal data corresponding to the regular program data.

(C) Problems to be Solved by the Invention However, in the above-mentioned conventional technique, when data is written / read to / from a specified address of a data memory by an evaluation microcomputer for the purpose of program evaluation, The conventional evaluation device has no means for confirming the write / read address of the data memory, that is, there is no method for confirming which address of the data memory has been accessed to perform the program evaluation. The access status to was unclear. Therefore, even if a predetermined address of the data memory is erroneously accessed based on erroneous program data and erroneous program evaluation is performed, the error state cannot be confirmed, and there is a problem that more accurate program evaluation cannot be performed. there were.

Further, there is no means for confirming the access count of the data memory used by the program evaluation at a glance, so that there is a problem that the actual access count against the correct access count of the data memory at the time of the program evaluation cannot be confirmed promptly.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and includes a first memory in which predetermined data is stored and an address in the first memory. One-to-one correspondence, the first
A second memory having a corresponding address to which a processing code indicating that the memory address has been accessed is written, and a specific address to which access count data indicating the total access count of the first memory is written, An evaluation microcomputer which incorporates an address counter for simultaneously accessing corresponding addresses of the first memory and the second memory, and operates by reading predetermined data at a specified address of the first memory; Means for writing the processing code to a corresponding address of the second memory in the write state based on a memory drive signal for writing or reading the memory of the first memory, and the second memory In each access period of the second memory, the address from the specific address of the second memory is Operation of incrementing reads Seth count data,
And a means for performing an operation of writing the incremented access count data to a specific address of the second memory, the evaluation device of the microcomputer.

(E) Operation The present invention is a microcomputer evaluation device, wherein access frequency data indicating the access frequency of the memory (first memory) at the time of program evaluation is stored in the storage means (specific address of the second memory). The processing code indicating that the predetermined address of the first memory has been accessed corresponds to the second address corresponding to the designated address of the first memory.
Is written to the corresponding address in the memory. Therefore, it is possible to check whether or not the regular address of the memory (first memory) has been accessed, and also to confirm the number of times the memory (first memory) has been accessed, so that more accurate program evaluation can be performed quickly. It will be.

(F) Examples The details of the present invention will be specifically described with reference to the illustrated examples.

Referring to the drawings, reference numerals and configurations will be described. (1) is an evaluation chip (evaluation microcomputer), and the evaluation chip (1) has substantially the same function as a mass-production 1-chip microcomputer. , A data pointer (1 as an address counter
a) built-in. Reference numeral (2) is a RAM (memory, first memory), and the RAM (2) is in a write state by a write signal WR1 (memory drive signal) output from the evaluation chip (1) and a read signal. It becomes a read state by RD1 (memory drive signal).

Here, a general operation of the evaluation chip (1) will be described. First, when a predetermined address of an external program memory (not shown) is accessed by a program counter (not shown) built in the evaluation chip (1), it is stored in advance at a specified address of the program memory. The stored program data is read into the evaluation chip (1). Then, based on this program data, a predetermined address of the RAM (2) is accessed by the data pointer (1a) inside the evaluation chip (1), and the specified address of the evaluation chip (1) and the RAM (2) is accessed. Write signal WR1 and read signal RD1
Writing / reading of data is performed based on. Then, in the evaluation chip (1), the data read from the RAM (2) is processed based on the program data read from the program memory to analyze whether or not the processed data is regular data. By doing so, the quality of the address access program data and the data processing program data of the RAM (2) described above is checked, that is, the program evaluation is performed.

(3) is a RAM (storage means, second memory), and the RAM
(3) has a corresponding address corresponding to each address of the RAM (2) on a one-to-one basis and one specific address (3a), and the data pointer (1a) allows the RA
The corresponding addresses of the M (2) and the RAM (3) are simultaneously accessed.

A chain line (4) is a write control circuit, and the write control circuit (4) is formed by combining AND gates (5) and (6) and an OR gate (7), that is, a multiplexer. The AND gate (5) receives the write signal WR1 and the RAM (2) when it is in the write state.
A write enable signal WREN for putting the RAM (3) into a write state can be applied. Further, the AND gate (6) can be applied with the read signal RD1 and a write enable signal RDEN for putting the RAM (3) into a write state when the RAM (2) is in a read state. Then, the write signal WR3 output from the OR gate (7) puts the RAM (3) in a write state. That is, the RAM (2) is in a write state (WR1 =
In order to put the RAM (3) in the write state when "1"), the write enable signal WREN of "1" is input to the input port (8).
Is applied, and in order to put the RAM (3) in the write state when the RAM (2) is in the read state (RD1 = "1"), a write enable signal of "1" is input to the input port (9). RDEN should be applied. In other words, the RAM
The RAM (3) when the (2) is in the write / read state
Since the operation to set the write status is optional, the RA
Even if M (2) is in the write / read state, the RAM
It is of course possible not to operate (3).

Reference numeral (10) is a control circuit (control circuit), and the control circuit (10) and the pull-up resistor (11) pulled up to the power supply voltage Vdd constitute a means for writing a processing code. Then, in the state before setting the RAM (3) to the write state, the RAM
(3) is initially reset by the control output of the control circuit (10). For example, the RAM (3)
When one word for each address of 8 is composed of 8 bits, each time the address of the RAM (3) is sequentially accessed by the address data obtained from the control circuit (10), the RAM (3 "00000000" is written in the designated address of), which means that the RAM (3) is effectively reset. Also the RAM
In the case where the predetermined address in (2) is accessed to write / read data and the RAM (3) is set to the write state, the RAM (2)
The processing code "11111111" is written by the power supply voltage Vdd (= logic "1") based on the control output of the control circuit (10) to the corresponding address of the RAM (3) corresponding to the predetermined address of Has become. That is,
The address of the RAM (3) corresponding to the address written / read in the RAM (2) is “111”.
11111 "is written, and" 00000000 "is written in the remaining address of the RAM (3) which is not the case. Therefore, from the control circuit (10) to the RAM
The read signal RD2 is arbitrarily applied to (3), and the RAM
By reading the contents written in (3), the RA
It is possible to easily check which address of M (2) is used, and in particular, it is possible to check the quality of the program data for address access of the RAM (2), and correct program evaluation can be performed.

(12) is an increment circuit, and the increment circuit (12) is controlled by the control signal (CTL) generated from the control circuit (10) when the control circuit (10) is controlled by the write signal WR3. The access number data (8 bits) stored in the specific address (3a) of the RAM (3) is incremented. For details, use the data pointer (1a) to RAM
(2) When the writing of the processing code to the RAM (3) is completed during each access period for accessing the corresponding address of (3), the control circuit (10) causes the specific address (3a) of the RAM (3). Remains accessed. And the specific address (3
In the state where a) is accessed, the read signal RD2 is output from the control circuit (10), and the RAM
The access count data of the specific address (3a) of (3) is read, and the access count data is read into the increment circuit (12) and incremented by +1. Then, the write signal WR2 is output from the control circuit (10), and the +1 incremented access count data is read from the increment circuit (12) and written to the specific address (3a) of the RAM (3). . That is, during each access period of the corresponding address of the RAM (2) (3), by performing a series of operations of reading, incrementing, and writing the access count data, the access count of the RAM (2) Will be stored in the specific address (3a). Therefore, the read signal RD2 is arbitrarily applied from the control circuit (10) to the RAM (3) and the access count data at the specific address (3a) is read, thereby easily accessing the RAM (2). It is possible to check, in particular, it is possible to easily check whether or not the RAM (2) is actually accessed by the regular access number of RAM (2) at the time of program evaluation, and correct program evaluation can be quickly performed. Here, the control circuit (10) and the increment circuit (1
2) constitutes means for executing reading, incrementing, and writing of the access count data at the specific address (3a) of the RAM (3). Incidentally, the above
Since one word of the RAM (3) is 8 bits, if the address data output from the data pointer (1a) is 8 bits, the specific address (3a) may be one address,
If the address data is 16 bits, two specific addresses (3a) are required.

a, c are address buses, b, d are data buses, and data “0000000” written from the data bus d to the RAM (3) is written.
Switching between "0" and "11111111" is controlled by the control circuit (10).

Below, the RAM (2) is set to the read state and the RAM
An example of the operation of setting (3) to the write state will be described.

First, the evaluation chip (1) outputs the read signal RD1 of "1" to put the RAM (2) into the read state, and also applies the write enable signal RDEN of "1" to the input port (9) to write control circuit. The RAM (3) is set to the write state by the write signal WR3 of "1" output from (4). Before setting the RAM (3) to the write state, RA is set by the control circuit (10).
Initially reset M (3).

In this state, when predetermined address data is applied from the data pointer (1a) to the RAM (2) via the address bus a, the predetermined address of the RAM (2) is accessed and the R
Data at a predetermined address of AM (2) is read into the evaluation chip (1), and data processing is performed inside the evaluation chip (1). On the other hand, the corresponding addresses of the RAM (2) and the RAM (3) are simultaneously accessed by the address data superimposed on the address bus a, and the writing is performed in the RAM (2) by the power supply voltage Vdd connected to the data bus d. / Processed data “11111111” is written to the address of the RAM (3) corresponding to the read address.

Here, the write signal WR3 is also applied to the control circuit (10), and the access count data incremented by +1 is written to the specific address (3a) for each access period of the RAMs (2) and (3). RAM than this
After reading by (2), control circuit (10)
With the read signal RD2 from the RAM, the write contents of the RAM (3) are read and analyzed to enable accurate program evaluation.

From the above, when writing / reading data to / from the RAM (2) for the purpose of program evaluation by the evaluation chip (1),
RAM is read by reading the contents written in (3).
It is possible to easily check which address in (2) is used and also the number of times RAM (2) is accessed, which makes it possible to quickly recognize a program erroneous evaluation and ensure accurate program evaluation. Become.

(G) Effect of the Invention According to the present invention, the access status and the number of accesses of the memory used for program evaluation can be confirmed easily and quickly, and even if the program evaluation is incorrect, it is possible to quickly notice and obtain an accurate program. There is an advantage that the evaluation can be surely performed.

[Brief description of drawings]

The drawing is a block diagram showing an evaluation apparatus for a microcomputer of the present invention. (1) ... Evaluation chip, (2) (3) ...
… RAM, (3a) …… specific address, (10) …… control circuit, (11) …… pull-up resistor, (12) …… increment circuit.

Claims (1)

[Claims] 1. A first memory in which predetermined data is stored, and each address of the first memory has a one-to-one correspondence with the first memory.
A second memory having a corresponding address to which a processing code indicating that the memory address has been accessed is written, and a specific address to which access count data indicating the total access count of the first memory is written, An evaluation microcomputer which incorporates an address counter for simultaneously accessing corresponding addresses of the first memory and the second memory, and operates by reading predetermined data at a specified address of the first memory; Means for writing the processing code to a corresponding address of the second memory which is in a write state based on a memory driving signal for writing or reading the memory of the first memory, the first memory and the second memory. During each access period of the memory, access is made from a specific address of the second memory. Operation of incrementing reads count data,
And a means for performing an operation of writing the incremented access count data to a specific address of the second memory, the evaluation device of the microcomputer.