JPH077457B2 - Original image histogram data collection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image scanning reading / recording apparatus, and an apparatus for obtaining a histogram of an original image which is indispensable when performing gradation conversion of the original image in scanning recording on an image. More specifically, the present invention relates to an original image histogram data collecting apparatus that collects original image histogram data having a plurality of image areas in real time for each image area in image scanning and reading.

(Prior Art and its Problems) An example in which an image scanning / reading / recording apparatus, for example, a flatbed scanner, adopts a gradation conversion process for redistributing the density distribution of an original image as one mode of a simple image conversion process. In many cases (Japanese Patent Laid-Open No. 63-42575, etc.).

In order to perform the gradation conversion process on the original image, it is necessary to first obtain the density histogram of the original image. It is relatively easy to obtain this density histogram by using a memory device having a storage capacity corresponding to the total pixels of the original image. However, in the above flatbed scanner,
The image memory has a capacity of at most about 2 scanning lines, that is,
It is common to have only an image buffer. Therefore,
Real-time processing is required to collect density data during a read scan (pre-scan) performed prior to the read scan for recording and obtain a histogram thereof.

On the other hand, when the original image has a plurality of image areas having different specifications, the gradation conversion must correspond to each image minutely, and therefore the density histogram needs to be obtained for each image area. According to the present invention, the histogram data is processed in real time at the time of prescan without providing a large-capacity image memory, and this processing is performed for each image area of the original image. Against the background of these three conditions.

Prior arts against the background of the above three conditions are shown in FIGS.

As shown in FIG. 9, the original image (1) having the image areas (2) and (3) is photoelectrically scanned in the main scanning direction (Y) and the sub scanning direction (X). The main signals involved in this scanning are, as shown in FIG. 10, a pixel clock that gives an image data acquisition timing, pixel data that indicates the pixel signal value (density value, etc.), and an effective reading period of the pixel data. Is a pixel enable signal (hereinafter, abbreviated as a pixel ENB signal) indicating whether or not an invalid period such as a restoration period. In order to collect pixel data by histogram for each image area,
Processing is performed according to the flow shown in FIG. 11 and an outline of FIG. 12 (A) and (B).

In FIG. 11, (4) is the CP of the microcomputer
U, (5) same RAM, (6) flip-flop circuit,
(7) is a latch circuit, and (8) is a switching circuit which includes a decoder (8a) and switches between pixel data fetching processing and CPU internal processing.

If the pixel ENB signal input in synchronization with the pixel clock is active, the signal is latched by the flip-flop circuit (6) and activates the interrupt signal INT that requests the CPU (4) to perform interrupt processing. As a result, the CPU (4) executes the interrupt process of FIG. 12 (B), and first reads the pixel data latched in the latch circuit (7) in synchronization with the pixel clock.

Next, this interrupt program determines which area of the original image the pixel of the read pixel data belongs to, and which image area it belongs to. When the area is known, the memory block corresponding to the area for which the histogram is collected is obtained, the address in the block is calculated, and the RAM (5) is accessed. The memory content of the address is read, the value is updated and calculated based on it, and the updated content is written to the same address. When the rewriting is completed, the X coordinate counter and the X coordinate counter which give the current scanning position are processed and the process returns to the main routine of FIG. 12 (A).

This interrupt process is repeated every time the interrupt signal INT is input. When the scan end at which the processing of all the areas of the original image is finished is determined, a histogram corresponding to the areas is completed in the memory block of the RAM (5) at that time.

However, if real-time collection of histogram data is performed by an interrupt program in this way, the processing of pixel data greatly depends on the processing capacity of the CPU, and if the pixel data is read at high speed,
It must be replaced with an expensive CPU that can process at high speed. At present, the interrupt processing routine limits the cycle of the pixel clock, that is, this clock cycle must be longer than the maximum required time of the interrupt processing routine, resulting in a large pixel size, which is relatively large. There is a problem that the reading process becomes coarse. Also, even if the processing of the X and Y coordinate counters is removed from the interrupt processing routine (separately provided) and the clock cycle is shortened, that is, high-speed reading is performed, if the time required for the interrupt processing routine is longer than the clock cycle, pixels are thinned out. However, since data can only be collected, there is a problem that a histogram that is faithful to the original image cannot be obtained. In any case, at present, there are some problems in obtaining the histogram as the original data with high accuracy in order to obtain a highly accurate recorded image by gradation conversion, and in order to obtain an accurate recorded image. Another problem is how to obtain a highly accurate histogram that reflects this property in view of the property of the original image.

(Object of the Invention) Therefore, the present invention makes it possible to create a highly accurate histogram faithful to the original image, even if a CPU having a low processing capacity is used and pixels are read at high speed.
An object of the present invention is to provide a histogram data collection device that can obtain a more accurate recorded image according to the property of an original image (for example, a photograph).

(Structure of the Invention) The original image histogram data collecting apparatus of the present invention is provided in an image scanning reading apparatus that photoelectrically scans an original image having a plurality of image areas to obtain pixel data in synchronization with a pixel clock,
A device for creating a histogram of the pixel data for each of a plurality of regions in the original image, the region identification data previously obtained based on position coordinates defining the image region in the original image, the region is virtually A register circuit for storing a plurality of sets of continuous length data in the main scanning direction of the divided regions and weighting code data according to the divided regions, and preset data for the continuous length data output from the register circuit. A counter circuit for counting the pixel clock, a latch circuit for latching the region identification data and code data output from the register circuit,
A memory accessed by using the read pixel data as the second address and the area identification data from the latch circuit as the first address, and a weight value based on the code data from the latch circuit is added to the read data from this memory. And a timing control circuit for outputting the set data of the register circuit according to at least the count signal of the counter circuit and controlling read / write of the memory.

(Operation) When reading along the main scanning line enters another designated and virtually divided image area of the original image, the towing control circuit reads the set data from the register circuit. The area identification data latched by the latch circuit gives the first address of the memory, whereby the memory block corresponding to the area is designated. On the other hand, the pixel data input in synchronization with the pixel clock gives the second address of the memory, whereby the predetermined address in the memory block is designated. The counter circuit counts the pixel clock and indicates during which count the data of the currently read pixel belongs to which divided area. In the adder circuit, the specified address is accessed and read out. A weight value based on the code data from the latch circuit, for example, "2" is added to the contents thus obtained, and the result is written to the same address by the timing control circuit as in the case of reading, and the stored contents are updated. The operation of adding the above weight values is performed with different weight values each time the main scanning line enters a different divided area in the main scanning direction, and as these operations are advanced in the sub scanning direction, the corresponding area of the memory The weighted histogram data is accumulated in the blocks.

In order to facilitate the understanding of the examples described below, reference examples that form the basis of the examples will be given, and the outline of the present invention will first be described by the reference examples.

Reference Example A reference example will be described with reference to FIGS. FIG. 4 shows an original picture (11) having image areas A, B and C and an area Z. Prior to the scanning process, the coordinates of the image areas A, B and C are input to the reading device by the coordinate input device. If it is a rectangle as shown in FIG. 4, two diagonal points are designated as in FIG.

When the coordinate input is completed, the microcomputer (not shown) of the reading device uses the input data to draw the original image (1
The lengths of the areas A, B, C, and Z in 1) that divide the main scanning lines are calculated for each main scanning line. When the pixel size is used as a unit, its length is represented by an integer value like L. This L is used as continuous length data.

The microcomputer uses the continuous length data L obtained for each of the main scanning lines X ₁ , X ₂ , X ₃ , X ₄ , ... Xn and area identification data (ID indicating which area the continuous length data belongs to. data)
A data table as shown in FIG. 5 is created by pairing a, b, c and z. Taking the main scanning line X ₃ as an example, the area A continues for a length L ₃ from the start of effective scanning, the area B continues for a length L ₄ , then the area C continues for a length L ₅ and the last area. Z is the length
L ₆ Indicates that the end of effective scanning is reached.

FIG. 1 is a block circuit diagram of a histogram data collecting device according to a reference example and an example described later.

A RAM (21) for storing the histogram data uses an internal memory of a microcomputer (not shown) that controls the operation of the reading device.

RAM (21) CPU via CPU interface (22)
It is connected to the bus and CPU.

The data input D of the first-in first-out register circuit (23) (hereinafter referred to as the FIFO circuit) is the CPU interface (2
2) Connected to the CPU via
Is connected to the CPU via the CPU bus and can store a plurality of data pairs of the continuation length data and the area identification data of the data table shown in FIG.

The latch circuit (24) latches the region identification data among the paired data output from the FIFO circuit (23) by the output signal j of the towing control circuit (25) in synchronization with the pixel clock signal c. On the other hand, the preset counter circuit (26)
Of the output of the FIFO circuit (23), the continuous length data is loaded in synchronization with the pixel clock signal c by the output signal e of the towing control circuit (25). The counter circuit (26) counts the pixel clock signal, and when the count value becomes the load data, outputs the signal f from Dec Out.

The output g ₁ of the latch circuit (24) is input to the buffer circuit (27). On the other hand, the pixel data b is the pixel clock signal c
Is latched by the latch circuit (28) in synchronism with, and the output is input to the buffer circuit (27). The output of the buffer circuit (27) is connected to the address bus (29) of the FAM (21), and the buffer circuit (27) functions as an address buffer.

The RAM (21) directly accessed by the CPU is also accessed by the timing control circuit (25). The signal h output from the timing control circuit (25) is read-accessed to prevent the data from colliding on the bus.
Is write-accessed by the delayed signal i.

The adder circuit (30) has a data bus (3) extending from the RAM (21).
4) consists of an adder circuit (31) connected to the A input and a latch circuit (32) that latches the addition result S in synchronization with the signal h. The output of the latch circuit (32) is the RAM (21). ▲
▼ The data bus of RAM (3
4) can be put on. The addition input B of the adder circuit (31) has a predetermined value, for example, a fixed value "1" or a look-up table (3) depending on the output g ₂ of the latch circuit (24).
It is also possible to input a value other than "1" that is referenced and output in 3).

The output g ₂ and the look-up table (LUT) (33) will be described later as an embodiment of the present invention. In the reference example shown here, it is described that the adder circuit (31) simply increments by 1, that is, one piece of pixel data becomes one piece of data of the histogram.

The circuit operation of FIG. 1 will be described with reference to the flow executed by the CPU of FIG. 2 and the timing chart of FIG. Further, more specifically, the main scanning line X ₃ shown in FIG. 4 and FIG.
The case of processing is illustrated. This is the case where L ₃ = 3, L ₄ = 1 and L ₅ = 5.

First, in FIG. 2, when the main program for histogram collection starts, the histogram memory unit, that is, the corresponding area of the RAM (21) is initialized in step (S1). In the next step (S2), the continuation length data is calculated based on the coordinates of the image area that is input in advance, and the area identification data is added to create the data table shown in FIG. Set. In step (S3), the state of the FIFO circuit (23) is monitored (the wiring for this monitor is omitted in FIG. 1). If data can be input, the process proceeds to step (S4) and is already calculated. (Data of continuous length + area identification data)
Set in the FIFO circuit (23). The step (S5) determines the scan end whether the scanning is completed over the entire area. If not, return to step (S3),
The state of the FIFO circuit (23) is checked, and if the data is read from the FIFO circuit (23), the pair data next to the previously written pair data is set in step (S4), and all the data is set. Repeat until you write.

When processing the main scan line X ₃ , before the start of this scan line from the end of the scan line X ₂ , the first pair of data (L ₃ , a) is output from the FIFO circuit (23) to the counter circuit (26), respectively. It is loaded into the latch circuit (24). When the first pixel data (P0) is input in synchronization with the pixel clock c, the area identification signal g
RAM (21) that stores the histogram according to ₁ (a)
Memory block is selected, and the latch output d (P0) of the pixel data gives an address in this memory block and becomes accessible. The contents of that address are read by the ▲ ▼ signal h of the RAM (21), and the addition circuit (3
In step 0), the predetermined value "1" is added, and the subsequent ▲ ▼ signal i
Causes the cumulative data to be written to the same address.

Now, L ₃ = 3, and the above operation is repeated three times until the Dec Out signal of the counter circuit (26) is output. As the Dec Out signal is output when the count value f is 1, its numerical value is described in the timing chart of FIG.

When the Dec Out signal is output, the timing control circuit (2
The counter load signal ▲ ▼ (e) is input to this counter circuit (26) via 5) and the pixel data b (P
The next pair of data (L ₄ , b) is loaded from the FIFO circuit (23) into the counter circuit (26) and the latch circuit (24) in synchronization with the next pixel clock c corresponding to 3). And
Similar processing is repeated by the new count data and area identification data.

(Example) Next, an example will be described.

For example, a photograph is taken as an example of the image. Considering the purpose and action of taking a photograph, generally, in a photographic image, the important part is the central part, and the importance becomes lower toward the peripheral part. When this photographic image is read and recorded as gradation conversion, if the density distribution over the entire photographic image is simply obtained as a histogram, it is conceivable that the data in the unimportant peripheral portion will adversely affect the important central portion. Therefore, if one region is virtually divided into, for example, an important region, a region that is not so important, and an intermediate region between these regions, and the histogram accumulation weighting is changed in association with each region, the image It is possible to obtain a more accurate recorded image that matches the property of.

An apparatus that weights and obtains a histogram in line with the above-mentioned purpose can be realized by modifying the above-described reference example. This will be described with reference to FIGS. 6, 7, and 1.

FIG. 6 shows the image area C in the original image (11) shown in FIG. It is assumed that the image area C is a photographic image, for example. As the importance decreases in the order of the central part, the intermediate part, and the peripheral part, weighting of the histogram data is given as "3" for the central part, "2" for the intermediate part, and "1" for the peripheral part. To do. Therefore, one image C is divided into three virtual regions, the continuous length data shown in the above reference example is also applied to these virtual three regions, and weighting is associated with the continuous length data. Set with the code.

As shown in the example of the main scanning line X ₄ , the continuous length data L ₉ is L _{91 to} L _95.
As shown in FIG. 7, each continuous length data is set with a code for referring to the weight table (33) in FIG. When the code data is input from the latch circuit (24), the weighting table (33) outputs the corresponding weight data, which is used as the added value of the dar circuit (31).

Although the above weighting is performed by referring to the weighting table according to the code, the code itself may be a binary value of the weight. In this case, a simple latch circuit can be used instead of the weight table.

Further, whether or not to weight the image may be specified by inputting the coordinates of the image region after the input, and in the case of weighting, how to allocate the virtual region is pre-patterned. The standard can be created in advance, and the operator can arbitrarily specify the pattern according to the characteristics of the image, whereby the allocation can be automatically performed by the microcomputer.

In each of the reference example and the example described above, the case where the original image has a rectangular image area is shown, but the original image (41) shown in FIG.
As described above, even if the original image has a plurality of image regions of different types or the same types such as a circle, a triangle, an ellipse, a star, and an L shape in addition to a rectangle, the present invention can be similarly applied. It does not hinder.

Note that the histogram in this specification is based on a density histogram as an example, but the term “density” indicates an optical density value in a narrow sense, and also the Munsell value and the output of the original image reading device. The signal level, the signal level after shading correction, and the dot area ratio in the dot image are generally referred to as quantities corresponding to optical density values.

(Effect of the Invention) As described above, according to the present invention, since the CPU does not directly intervene in the histogram collection process of reading the image of the pixel data, an inexpensive CPU with a low processing capacity can be used,
In addition, since the restriction on the clock cycle for pixel reading is greatly relaxed, high-speed reading, that is, high-accuracy reading is possible and a highly accurate histogram can be obtained, which improves the quality of recorded images. Can be improved. Further, the apparatus according to the present invention is not limited to a small-sized and simple-type image scanning reading apparatus, but can be widely applied regardless of the large-sized, medium-sized, and reading fineness, and therefore in terms of versatility. The utility value is great. further,
According to the present invention, the inside of the image area is divided, a weight value according to the property of the image is given to the divided area, and the weighted histogram is collected using this weight value. There is an effect that a more accurate recorded image corresponding to the above can be obtained.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a reference example, a schematic flowchart of CPU processing in the embodiment, FIG. 3 is a timing chart of signals in the circuit of FIG. 1, and FIG. FIG. 5 is an explanatory diagram of original image scanning in the reference example, FIG. 5 is a conceptual diagram of a data table of the continuous length data and area identification data in the reference example, and FIG. FIG. 7, FIG. 7 is an explanatory diagram of how to set weighting data, FIG. 8 is a diagram showing forms of various images placed in an original image, and FIG. 9 is an explanatory diagram of reading and scanning an original image having a plurality of image regions, FIG. 10 is an explanatory diagram of timing of image signals, FIG. 11 is a block circuit diagram of a conventional example, and FIG. 12 is a flowchart of CPU processing of a conventional example. A, B, C …… Image area, 11 …… Original image, 23 …… First-in first-out register circuit (FIFO circuit), 26 …… Preset counter circuit, 24 …… Latch circuit, 21 …… RAM, 30 …… Adding circuit, 25 …… Timing control circuit, 31 …… Look up table (weighted table).

Claims (1)

[Claims] 1. An image scanning / reading device for photoelectrically scanning an original image having a plurality of image areas to obtain pixel data in synchronization with a pixel clock, and creating a histogram of the pixel data for each of the plurality of areas in the original image. Which is a device for predetermining region identification data based on position coordinates defining an image region in the original image, continuous data in the main scanning direction of a divided region obtained by virtually dividing the region, and the division. A register circuit that stores a plurality of set data of weighting code data according to areas, a counter circuit that counts pixel clocks by using the continuation length data output from the register circuit as preset data, and an output from the register circuit. A latch circuit for latching the region identification data and the code data, and the read pixel data as a second address. A memory accessed using the area identification data from the first address as a first address; an adder circuit that adds a weight value based on the code data from the latch circuit to the read data from the memory; and a count signal of at least the counter circuit. And a timing control circuit that controls the read / write of the memory while outputting the group data of the register circuit in response to the original data.