JPH0777263B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to manufacturing a semiconductor device in which a silicide film is selectively formed on a diffusion layer of a semiconductor substrate. It is about the method.

(B) Conventional technology In general, due to higher integration of LSIs, transistors are further miniaturized, and wiring resistance of gate electrodes, contact resistance with upper layer wiring, and diffusion resistance in source / drain diffusion layers are increased. A decrease in driving force of transistors has become a problem.

Therefore, a technique of forming a silicide film on the gate polycrystalline silicon and the diffusion layer in a self-aligned manner has been studied as a means for reducing the above resistances.

FIG. 2 shows a conventional example in which the LOCOS method is used for element isolation.

That is, as shown in FIG. 2 (a), the silicon substrate 1
A LOCOS oxide film 2a of SiO ₂ and a gate oxide film 2b are formed on the LOCOS oxide film 2a as a mask, BF ₂ ⁺ is injected to form a diffusion layer 3, and then both oxide films 2a and 2b are formed. By removing a predetermined thickness, the surface of the diffusion layer 3 is exposed [see FIG. 2 (b)], and then a Ti film 5 is formed on the entire surface [see FIG. 2 (c)]. Heat treatment is applied in the atmosphere to form the TiSi ₂ film 7 on the diffusion layer 3 [see FIG. 2 (d)].

(C) Problems to be Solved by the Invention However, when element isolation by the LOCOS method is used, the LOCOS oxide film 2a has a taper shape, and therefore, when removing the SiO ₂ film on the surface, as shown in FIG. As shown in, the junction depth is A / c at the separation edge at the LOCOS edge with respect to the overetch amount A.
It becomes shallow by osθ. Therefore, if a silicide film is formed on top of this, there is a risk of leakage of the junction,
Moreover, it is difficult to increase the thickness of the silicide film to reduce the resistance.

Further, as the surface area of the diffusion layer is reduced, when the upper layer wiring is directly contacted on the diffusion layer, the contact diameter may be reduced due to the limitation from the alignment margin.

It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing a leak of a junction from occurring at the isolation end of an element isolation film when forming a silicide film on a diffusion layer. is there.

(D) Means and Actions for Solving the Problem This invention forms a trench for element isolation on a silicon substrate when forming a silicide film in a self-aligning manner on at least an impurity diffusion layer on a silicon substrate, After embedding silicon oxide in the groove to form an element isolation part, and subsequently forming an insulating film of silicon oxide on the surface of the silicon substrate,
Impurities are implanted on the silicon substrate through the insulating film,
An impurity diffusion layer is formed around the element isolation portion, and then,
The insulating film is removed so that at least the surface of the impurity diffusion layer is exposed, and then a refractory metal film is formed on the entire surface of the silicon substrate and heat-treated in a nitrogen atmosphere to selectively expose the exposed surface of the impurity diffusion layer. A silicide film is formed on the surface of the refractory metal film, a nitride film is formed on the surface of the refractory metal film, and a part of the nitride film is patterned so as to be located on the element isolation portion, and then an interlayer insulating film is formed on the entire surface. Then, a contact hole is formed so that the nitride film is exposed, and an aluminum wiring is formed so as to be electrically connected to the nitride film.

That is, according to the present invention, when selectively forming a silicide film on an impurity diffusion layer formed on a silicon substrate, after forming a groove on the silicon substrate, an element isolation portion to be joined to the impurity diffusion layer, Since SiO ₂ is buried in the groove, the gate oxide film extending from the upper surface of the element isolation portion to the surface of the impurity diffusion layer can be formed in a horizontal laminated film. Can be removed by making the junction depth uniform, and the surface of the diffusion layer can be exposed without making the diffusion layer thickness near the separation end thinner than in the conventional method. As a result, even if a silicide film is formed on the diffusion layer, it is possible to reduce the risk of junction leakage, and it is possible to form the silicide film thick and reduce diffusion resistance.

Further, a contact region can be secured from the surface of the silicide film to the surface of the element isolation portion, and the alignment margin at the time of contact formation can be increased. Further, by heat treatment in a nitrogen atmosphere to form a nitride film on the metal film surface,
It is possible to prevent aluminum in an aluminum wiring layer to be formed later from diffusing into the silicon substrate.

In the present invention, the element isolation portion is formed by forming a groove in the element isolation portion formation region by RIE and then burying silicon oxide by the CVD method.

In the present invention, the impurity diffusion layer is formed by ion-implanting a dopant as an impurity before forming the silicide film.

Then, when forming the silicide film, for example, titanium nitride formed on the SiO ₂ film of the element isolation portion is patterned to form a contact with the upper wiring there.

Metals such as Ti, Co, Ta and Pt are used as the silicide film in the present invention.

(E) Embodiments The present invention will be described in detail based on the embodiments shown in the drawings. The present invention is not limited to this.

In FIG. 1D, a silicon substrate 1 having a high-concentration P-type impurity diffusion layer 3 of BF ₂ ⁺ and a gate electrode 4 of poly-Si.
Groove 1a formed on the surface of the substrate 1 around the diffusion layer 3
An element isolation portion 20 made of SiO ₂ buried in the trench is provided, and a TiSi ₂ silicide film 6 is provided on the surface of the diffusion layer and the gate electrode 4.

Further, the gate electrode 4 has Si on the bottom surface and side wall, respectively.
A gate oxide film 2a of O ₂ and a sidewall 2b are formed.

Then, an SiOx interlayer insulating film 8 is formed on the entire surface by a CVD method, and a contact hole with the gate electrode 4 is formed.
The upper wiring 9 of Al—Si is connected to the silicide film 6 through the contact 10, and the contact between the impurity diffusion layer 3 and the upper wiring 9 is on the surface of the element isolation portion 20 and the surface of the silicide film 6 on the impurity diffusion layer 3. This is performed through the TiN film 7 arranged in the straddling region and the contact hole 11.

The manufacturing method will be described below.

In order to manufacture an LDD type transistor, first, a groove 1a for element isolation is formed on a silicon substrate 1, silicon oxide is embedded in the groove to form an element isolation portion 20, and then the silicon substrate 1 is formed. After forming a gate oxide film 2a of silicon oxide by thermal oxidation on the surface of, a gate electrode part 4 of polysilicon covered with silicon oxide 2b is formed thereon, and then,
BF ₂ ⁺ on the silicon substrate 1 with the gate electrode part 4 as a mask
Are implanted to form the P ⁺ diffusion layer 3 and the P ⁻ diffusion layer 3a surrounded by the element isolation portion 20 [see FIG. 1 (a)], and then silicon oxide is selectively etched to diffuse impurities. The silicon oxide film on the layer 3 and the upper surface of the gate electrode portion 4 is removed [see FIG. 1 (b)], and after a Ti film is laminated on the entire surface (not shown), in a N ₂ gas atmosphere, 650 ° C
The impurity diffusion layer 3 and the gate electrode portion 4 are subjected to heat treatment at
A silicide film 6 of TiSi ₂ is formed in self-alignment on the silicon oxide film formed by the reaction of the N ₂ gas and Ti.
Of the conductive film of TiN, by patterning, only the conductive film portion 7 on the element isolation portion 20 is left so as to be connected to the silicide film 6 on the impurity diffusion layer 3 [see FIG. 1 (c)]. After the SiOx interlayer insulating film 8 is formed on the entire surface by the CVD method, the interlayer insulating film 8 on the conductive film portion 7 and the gate electrode portion 4 is opened to form the contact hole 1.
1, 10 are formed, and subsequently, an Al-Si upper layer wiring 9 is formed through the contact holes 11, 10 [see FIG. 1 (d)].

As described above, in the present embodiment, even in the diffusion layer 3 near the isolation end of the element isolation portion 20, the layer thickness is the same as that of the other diffusion layer portions,
It is possible to reduce the junction leak current when the reverse bias is applied. Further, by leaving the TiN film 7 over the diffusion layer 3 and the element isolation portion 20, it is possible to secure a contact region with the upper wiring 7 not only on the diffusion layer but also in a wide region.
When forming the contact hole 11, there is a margin for overetching in contact etching. Moreover, when the contact diameters of the same size are used, the lower contact area becomes large, so that the alignment margin at the time of contact photo can be loosened.

(F) Effect of the Invention As described above, according to the present invention, in a semiconductor device having a silicide film of a semiconductor integrated circuit, a silicide film causes a junction leak on a shallow diffusion layer that is element-isolated by a silicon oxide film. It is possible to form a thick silicide film and reduce diffusion resistance. Further, a contact can be formed on the conductive film simultaneously formed on the element isolation portion, so that the margin at the time of forming the contact can be increased. Furthermore, by heat-treating in a nitrogen atmosphere to form a nitride film on the surface of the metal film, it is possible to prevent aluminum in an aluminum wiring layer to be formed later from diffusing into the silicon substrate.

[Brief description of drawings]

FIG. 1 is a manufacturing process explanatory view for explaining an embodiment of the present invention, and FIG. 2 is a manufacturing process explanatory view showing a conventional example. 1 ... Silicon substrate, 1a ... Groove 2a ... Gate oxide film, 3 ... P ⁺ diffusion layer, 6 ... TiSi ₂ silicide film, 11 ... Contact hole, 20 ... Element isolation part.

Claims (1)

[Claims] 1. When a silicide film is formed on at least an impurity diffusion layer on a silicon substrate in a self-aligning manner, a groove for element isolation is formed on the silicon substrate, and silicon oxide is embedded in the groove to isolate the element. Part, and subsequently, after forming an insulating film of silicon oxide on the surface of the silicon substrate,
Impurities are implanted on the silicon substrate through the insulating film,
An impurity diffusion layer is formed around the element isolation portion, and then,
The insulating film is removed so that at least the surface of the impurity diffusion layer is exposed, and then a refractory metal film is formed on the entire surface of the silicon substrate and heat-treated in a nitrogen atmosphere to selectively expose the exposed surface of the impurity diffusion layer. A silicide film is formed on the surface of the refractory metal film, a nitride film is formed on the surface of the refractory metal film, and part of the nitride film is patterned so as to be located on the element isolation portion, and then an interlayer insulating film is formed on the entire surface Then, a contact hole is formed so that the nitride film is exposed, and an aluminum wiring is formed so as to be electrically connected to the nitride film.