JPH0777337B2 - Digital input device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital input device, and more particularly to a digital input device for processing a large number of input signals.

[Technical background of the invention]

FIG. 5 is a block diagram of a conventional digital input device. As shown in FIG. 5, a filter circuit (FLT _{1 to} FLT _n ) 2 is provided for each of a plurality of input signals (IN _{1 to} IN _n ) 1, and outputs from these plurality of filter circuits are selected by a select circuit 3. , Output 4 was configured.

[Problems of background technology]

In the conventional device having the above configuration, a filter circuit is required for each digital input signal, and when the circuit is mounted on the board, the number of filter circuits increases in proportion to the number of input signals. The number of input signals per substrate is limited, which also increases the cost of the substrate.

[Object of the Invention]

The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital input device in which an increase in the number of filter circuits due to an increase in the number of input signals is prevented.

[Outline of Invention]

According to the present invention, a plurality of input signals are sampled at a predetermined cycle according to an address, and each of these sampled data is sequentially stored in a plurality of RAMs at time intervals to create data with a time difference. By comparing the data collectively for each address, matching or non-matching is detected and filtering is performed.

Example of Invention

 Embodiments will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a digital input device according to the present invention. FIG. 1 illustrates a case where the number of input signals is 64, the input signal sampling period is 1 ms, and the filtering time is 4 ms. (IN _{1 to} IN ₆₄ ) 1 is an input signal, 11 is a multiplexer for inputting one of the input signals to the address bus
It is selected by the address information from 26 and is output to the selection output 27. RAM ₀ 12 to RAM ₃ 15, RAM ₂₅ are 1-bit RAMs with addresses 0 to 63, of which the input signal (IN _{1 to} IN ₆₄ ) 1 is selected for RAM ₀ 12 to RAM ₃ 15. In the meantime, the contents are stored in addresses 0 to 63. That is, for the input signal IN ₁ , first to the address ₀ of RAM ₀ at the first sampling time, to the address ₀ of RAM ₁ at the next sampling time after 1 ms, and to the address 0 of RAM ₂ at the next sampling time. At the time of the next sampling, data with a time difference of 1 ms is sequentially stored in the RAM ₃ like the address 0 of RAM _3.
When the memory of ₃ is completed, it returns to the first RAM ₀ . The same applies to the other input signals (IN _{2 to} IN ₆₄ ). In short, regarding each RAM _{0 to} RAM ₃ , all input signals (IN _{1 to} IN ₆₄ ) are ₀ to 6 of RAM _{0 at} the time of the first sampling.
It is stored in address 3, and in the next sampling cycle after 1ms, all input signals (IN _{1 to} IN ₆₄ ) at that point in time are stored with data with a time difference, such as addresses 0 to 63 in RAM _1. It
Reference numeral 16 is a decoder, 17 is an address generator, and 18 is a control circuit. Here, the decoder 16 decodes the code signals 28 and 29 from the address generator 17 and outputs the chip select signals 46 to 49 of the respective RAM _{0 to} RAM ₃ . Further, the decoder 16 receives the collective output signal 51 from the control circuit 18 and simultaneously outputs the chip select signals 46 to 49. In short, after the RAMs are sequentially selected by the chip select signals 46 to 49, the RAMs _{0 to 3} are simultaneously output by the collective output signal 51, and the stored data are compared with a time difference. 19 and 20 are logic elements, of which the logic elements 19
The RAM ₀ 12~RAM ₃ 15 output of 42 to 45 are all "1" output if the "1" Also, the logic device 20 is RAM ₀ 12~RAM ₃ 15 output of 42 to 45 are all "0 , The output is “1”.
That is, all outputs from RAM ₀ 12 to RAM ₃ 15 are “1” or “0”.
If they match with each other, they are discriminated and output. 21 is a JK flip-flop (hereinafter referred to as JKF / F), which has a preset input PR and a reset input CLR, and J = "1", K
When there is a clock signal 34 from the control circuit 18 when = "0", Q = "1", and when J = "0", K = "1" and there is a clock signal 34, Q = "0". . Furthermore J =
When "0", K = "0" and the clock signal 34 is present, Q does not change and remains in the state set by the preset input PR or the reset input CLR. 23 and 24 if "1" output 36 of the RAM ₄ 25 is when the control signal 33 from the control circuit 18 in the logic element is "1", "0" output of the logic element 24, and the addition,
If the output 36 is "0", the output of the logic element 23 is "0". RAM ₄ 25 stores a data of the filtered (IN ₁ ~IN _64). The address generator 17 is activated by the signal 50 from the control circuit 18 in a 1 ms cycle and increments the address. This address is incremented twice from 0 to 63 every 1 ms. Also, the code signal
28 and 29 are 2 bits and increment from 0 to 3 every 1 ms.

FIG. 2 is a time chart showing how each signal state is.

Address generator 1 outputs signal output 50 of 1ms cycle from control circuit 18.
When output to 7, the address generator 17 starts incrementing the address. Therefore, the data of the input signals IN _{1 to} IN ₆₄ is output to the selection output 27 of the multiplexer 11 in correspondence with the increment of the address. In addition,
In this case, the address is incremented twice within 1 ms and the input signal is output twice as a result, but only the first half is used and the second half is not used. At this time, code signals 28 and 29 from the address generator 17 are output in the form of "0" and "1" shown in the figure, and chip select signals 46 to 49 are output according to the output of the code signals 28 and 29. To be done. That is, code signal 2
RAM ₀ 12 to RAM ₃ 15 are sequentially selected and output according to _8, 29.

FIG. 3 is a detailed view of the time chart, showing 1 ms. As is clear from FIGS. 2 and 3, during the first 1 ms (t
_The chip select signal 46 becomes active from _{0 to} t ₂ ) and the RAM
₀ 12 is selected. In this case, according to the output of the write signal 30 from the control circuit 18, each selected output (IN _{1 to} IN ₆₄ ) is RAM ₀ 12
Written in. Although in the Figure 3 has a description from time t _0, the input signal to the RAM ₀ 12~RAM ₃ 15 already sample period 1ms each well at time t ₀ before it has been sequentially stored. Therefore, batch output 51 every 4 ms filtering time
Are also being output sequentially. The period from t ₁ to t _{2 in} FIG. 3 is the reading by the collective output signal 51, and the input data which has been already stored in sequence during this period is read to detect the coincidence or non-coincidence. In other words, the control circuit 18 outputs the collective output signal 51, all the chip select signals 46 to 49 of the decoder 16 become active, and the RAM ₀ 12 to RAM ₃ 15 are selected. In FIG. 3, the chip select signals 46 to 49 are RA.
From meanings set forth that M ₀ 12~RAM ₃ 15 are sequentially selected, this is not the shape becomes active all in accordance with the collective output signal 51. After that, the address generator 17 newly starts incrementing from addresses 0 to 63.

FIG. 4 is a time chart for explaining matching and non-matching for filtering. In this case, the chip select signals 46 to 49 are all activated in response to the collective output 51.

If first focus on the operation of the address 0, for JKF / F default setting, reads the data at address 0 from RAM ₄ 25, "1" of the data, preset or clear the JKF / F21 by "0" Do. Next, JK input of JKF / F21 and clock signal
34 Rewrite JKF / F21 by input. The J input is the output of the logic element 19 which detects the coincidence of the data of the outputs 42 to 45 of the RAM ₀ 12 to RAM ₃ 15, and when all the outputs are "1", J
The input becomes "1". Further, the K input is an output obtained by performing coincidence detection by the logic element 20, and when all the data are “0”,
The K input becomes "1". In the example of the time chart of FIG. 4, the 0th address and the 64th address are coincident with each other, and the outputs of the JKF / F21 are "1" and "0", respectively. And the 1st, 2nd, and 63rd addresses do not match, and the initial values set in the JKF / F remain the same. The JKF / output data 35 of the F21 is written to the RAM ₄ 25 by a write signal 31 of the control circuit 18, RAM ₄ 25
The data of is updated. In other words, always be the most recent data of the filtered is stored in the RAM ₄ 25. The input data can be filtered as described above.

In the above embodiment, the 1-bit RAM has been described, but the present invention is not limited to this. If a RAM of 2 bits or more is used and JKF / F and the like are expanded in accordance with the number of bits, a large number of bits can be set at one time. It is obvious that the efficiency can be further improved because the filtering can be performed.

〔The invention's effect〕

As described above, according to the present invention, the input signal is sampled at a predetermined sampling period and this data is converted into a plurality of RA signals.
By storing in M, data with a time difference between each other is created, and the data is compared at one place at the same time to perform coincidence detection, so the number of filters can be reduced and the mounting efficiency of the circuit board is improved. In addition, it is possible to provide a digital input device capable of reducing the circuit cost per bit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital input device according to the present invention, FIG. 2 is a time chart showing how each signal state is, and FIG. 3 is a detailed view of the time chart for 1 ms. FIG. 4 is an enlarged view of FIG. 4, and FIG. 4 is a time chart for explaining matching / mismatching for filtering.
FIG. 5 is a diagram showing a conventional filter configuration. 1 ... Input signal, 2 ... Filter circuit 3 ... Selector, 4 ... Output signal 11 ... Multiplexer, 12-15, 25 ... RAM 16 ... Decoder, 17 ... Address generation circuit 18 ... Control circuit, 19, 20, 22-24 ... Argument element 21 ... JK flip-flop 26 ... Address bus, 27 ... Select output 28, 29 ... Code signal, 30, 31 ... Write signal 32, 33 ... Control signal, 34 ... Clock signal 46 to 49 ... Chip select signal 50 … 1ms cycle output signal 51… Batch output.

Claims (1)

[Claims] 1. A digital input device for inputting and filtering a plurality of digital input signals at a predetermined sampling period, and for each input signal, data having a time difference from the first sampling time point is sequentially obtained to obtain the plurality of digital signals. A plurality of storage circuits that collectively store the plurality of digital input signals for each sampling, and data stored with a time difference in each storage circuit are collectively compared for each address, and the storage circuit Comparing circuit for outputting the same signal from the same, a logic circuit having a plurality of stable states for storing the comparison result, and each data which has been filtered to set an initial value for the logic circuit. And a control circuit that controls the timing of each circuit. Power equipment.