JPH0777452B2 - Time axis compression circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a track different from a luminance signal, which is a signal obtained by time-division-multiplexing a pair of component color signals by time-axis compression,
The present invention relates to a time axis compression circuit suitable for use in a recording apparatus that records simultaneously with this luminance signal.

[Outline of Invention]

The present invention uses the first to fourth four charge transfer elements, and in a time axis compression circuit that time-division-multiplexes a pair of component color signals by time axis compression to obtain signals that are time-division-multiplexed, the component color signals are used as the charge transfer elements. The generation of lattice defect noise is prevented by using a combination of a signal having the number of bits for one horizontal period and a signal having the number of bits for two horizontal periods so that a clock can be continuously supplied. It was done.

[Conventional technology]

As a recording device, a signal obtained by time-division-multiplexing a pair of component color signals as time-axis compression and recording it on a separate track from the luminance signal at the same time as this luminance signal is disclosed in, for example, Japanese Patent Laid-Open No. 61-2490. It is described in.

The time-axis compression circuit in such a recording apparatus has a bit number (n bits) for one horizontal period of the component color signal.
The first to fourth four charge transfer devices, for example, CCD (charge coupled device) are used.

That is, in FIG. 8, (51) to (54) are CCDs having a bit number (n bits) for one horizontal period.

The CCD (51), (53) has a red color difference signal R from the terminal (55).
-Y (shown in FIG. 9A) is input, and CCD (52), (5
4) has a blue color difference signal BY from the terminal (56) (Fig. 9B).
(Illustrated in) is input. The output signals of the CCDs (51) to (54) are supplied to the terminals a to d of the switch circuit (57), respectively, and the output signals of the switch circuit (57) are output through the low pass filter (58) to the output terminal ( 59).

Further, in two consecutive horizontal periods H ₁ and H ₂ , CCD (51) ~
A clock is supplied to the terminal (54) from terminals (60) to (63) as shown in FIGS. That is, in CCD (51) is a clock of a first frequency f _c in the horizontal period H ₁ is supplied, the clock frequency 2f _c with a second half of the horizontal period H ₂ is supplied, it is resting in its second half It In addition, CCD (5
In 2), the clock with the frequency f _c is supplied in the first horizontal period H ₁ , the clock is stopped in the first half of the _second horizontal period H ₂ , and the clock with the frequency 2f _c is supplied in the latter half. Further, in the CCD (53), the clock of frequency 2f _c is supplied in the first half of the first horizontal period H ₁ , the clock is paused in the latter half thereof, and the clock of frequency f _c is generated in the second horizontal period H _2. Supplied. In CCD (54), the first
A pause clock in the first half of the horizontal period H _1, is clocked frequency 2f _c at its latter half, the clock frequency f _c is provided in the second horizontal period H _2.

Also, the switch circuit (57) receives a control signal from the terminal (64).
The switch circuit (57) is supplied with S _SW0 , and the switch circuit (57) receives the c side, the d side, the a side, and the b side in the first half and the second half of the first horizontal period H _{1 and} the first half and the second half of the second horizontal period H ₂ , respectively. It is switched and connected to the side.

With the above configuration, in the first horizontal period H ₁ , CCD (5
1) and (52) are written with the color difference signals R-Y and B-Y for one horizontal period, respectively. In the first half of the _second horizontal period H ₂ , the color difference signal R for one horizontal period is read from the CCD (51). -Y is read and the switch circuit (57) and the low-pass filter (5
It is led out to the output terminal (59) via
The color difference signal BY for one horizontal period is read from the CD (52) and led to the output terminal (59) via the switch circuit (57) and the low-pass filter (58). In the second horizontal period H _2, the CCD (53) and (54), each writing one horizontal period of the color difference signals R-Y and B-Y is performed, first
In the first half of the horizontal period H ₁ of, the color difference signal RY for one horizontal period is read from the CCD (53) and is led to the output terminal (59) via the switch circuit (57) and the low-pass filter (58). In the latter half, the color difference signal BY for one horizontal period is read from the CCD (54) and is led to the output terminal (59) via the switch circuit (57) and the low pass filter (58).
Therefore, at the output terminal (59), the color difference signals RY and BY are time-compressed to 1/2 as shown in FIG. 9C, and the time-division multiplexed signal _Sc is obtained.

[Problems to be solved by the invention]

In the time axis compression circuit of this FIG. 8 example, CCD (51)
There is a problem that the lattice defect noise is generated because there is a clock pause period in which no clock is supplied to (54). That is, in the CCDs (51) to (54), charge defects jump in or leak due to lattice defects in the clock pause period, which becomes noise.

In view of this point, the present invention prevents the generation of lattice defect noise.

[Means for solving problems]

The present invention relates to first and third charge transfer devices having the number of bits for one horizontal period, for example CCDs (1) and (3), and second and fourth charge transfer devices having the number of bits for two horizontal periods. An element such as a CCD (2) and (4)
The first charge transfer device has two consecutive horizontal periods H ₁ and H ₂ .
Of the write clock is supplied in the horizontal period H ₁ of the second horizontal period H ₂ and the read clock of twice the frequency of the write clock is supplied in the second horizontal period H ₂ of the second horizontal period H _2. In the first horizontal period H ₁ of the period, a read clock having a frequency twice that of the write clock is supplied, and the write clock is supplied in the second horizontal period H ₂ , so that the first and third charge transfer elements are supplied to the first and third charge transfer elements. The first component color signal, for example R-Y, is input, and the second and fourth charge transfer elements receive the second component color signal, for example B.
-Y is input, and the output signals of the third and fourth charge transfer devices are output to the output terminal (9) in the first half and the second half of the first horizontal period H ₁ of the two consecutive horizontal periods H ₁ and H ₂ , respectively. In the first half and the latter half of the second horizontal period H ₂ , the first
And the output signal of the second charge transfer element is led to the output terminal (9).

[Work]

In the above-described configuration, since the clocks are continuously supplied to the first to fourth charge transfer elements, it is possible to favorably prevent the generation of lattice defect noise.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

In the figure, (1) and (3) are CCDs having the number of bits (n bits) for one horizontal period. Further, (2) and (4) are CCDs having a bit number (2n bits) for two horizontal periods. The red color difference signal RY (shown in FIG. 2A) is input to the CCD (1) and (3) from the terminal (5), and the CCD
The blue color difference signal BY from the terminal (6) is applied to (2) and (4).
(Illustrated in FIG. 2B) is input. Also, CCD (1) ~
The output signal of (4) is the terminal a of the switch circuit (7).
To d, and the output signal of the switch circuit (7) is led to the output terminal (9) through the low pass filter (8).

Further, in two consecutive horizontal periods H ₁ and H ₂ , CCD (1),
A clock is supplied to (2) from the terminal (10) as shown in FIG. 2D. That is, the frequency f _{c in the first} horizontal period H ₁
Of the frequency of 2f _{c in the second} horizontal period H ₂
Clock is supplied. Also, two consecutive horizontal periods
In H ₁ and H ₂ , the CCDs (3) and (4) are supplied with a clock from the terminal (11) as shown in FIG. 2E. That is,
A clock of frequency 2f _c is supplied in the first horizontal period H ₁ ,
A clock of frequency f _c is supplied in the second horizontal period H ₂ .

In addition, the switch circuit (7) receives a control signal from the terminal (12).
The switch circuit (7) is supplied with S _SW1 , and the switch circuit (7) receives the c side, the d side, the a side, and the b side in the first half and the second half of the first horizontal period H _{1 and} the first half and the second half of the second horizontal period H ₂ , respectively. It is switched and connected to the side.

In the above configuration, in the first horizontal period H ₁ , the frequency f _c
With the clock of, the color difference signals RY and BY for one horizontal period are respectively written in the first half of CCD (1) and CCD (2). Also, in the first half of the second horizontal period H ₂ that follows this, 1 is set from CCD (1) by the clock of frequency 2f _c.
The color difference signals RY for the horizontal period are read out, and CC
The color difference signal BY for one horizontal period written in the first half of D (2) is transferred to the second half. And CCD
The color difference signal RY read from (1) is led to the output terminal (9) via the switch circuit (7) and the low-pass filter (8). Further, in the second half of the second horizontal period H _2, the clock frequency 2f _c, the color difference signal B-Y for one horizontal period from the CCD (2) is read. Then, this color difference signal BY is led to the output terminal (9) via the switch circuit (7) and the low-pass filter (8).

In the second horizontal period H ₂ , the color difference signals R-Y and B-Y for one horizontal period are written in the first half of CCD (3) and CCD (4) by the clock of frequency f _c. . In the first half of the first horizontal period H ₁ that follows, the frequency 2f
The color difference signal RY for one horizontal period is read from the CCD (3) by the clock of _c , and the color difference signal BY for one horizontal period written in the first half portion of the CCD (4) is the second half portion. Transferred to. Then, the color difference signal RY read from the CCD (3) is led to the output terminal (9) via the switch circuit (7) and the low-pass filter (8).
Further, in the second half of the first horizontal period H _1, the clock frequency 2f _c, the color difference signal B-Y for one horizontal period from the CCD (4) is read out. Then, this color difference signal BY is led to the output terminal (9) via the switch circuit (7) and the low-pass filter (8).

Therefore, at the output terminal (9), as shown in FIG. 2C, the color difference signals RY and BY are time-compressed to 1/2, respectively, and a time-division multiplexed signal S _c is obtained.

As described above, according to this example, since the clocks are continuously supplied to the CCDs (1) to (4), it is possible to prevent the occurrence of lattice defect noise as in the conventional example.

Figure 3 is a time-division multiplexed signal S _c than the original color difference signals R
It is an example of a time axis expansion circuit for obtaining -Y, BY.

In the figure, (11) and (13) are CCDs having the number of bits (n bits) for one horizontal period. Further, (12) and (14) are CCDs having the number of bits (2n bits) for two horizontal periods. The time-division multiplexed signal S _c (shown in FIG. 4A) is input to the CCDs (11) to (14) from the terminal (15). The output signals of the CCDs (11) and (13) are supplied to the terminals a and b of the switch circuit (16), respectively, and the output signals of the switch circuit (16) are output through the low pass filter (17). It is derived in (18). Also, CCD (12)
The output signals of (14) and (14) are supplied to the terminals a and b of the switch circuit (19), respectively, and the output signal of this switch circuit (19) is output through the low pass filter (20) to the output terminal (21).
Be derived to.

Further, in two consecutive horizontal periods H ₁ and H ₂ , CCD (11),
A clock is supplied to the terminal (12) from the terminal (22) as shown in FIG. 4D. That is, in the first horizontal period H ₁ , the frequency 2f
The clock of _c is supplied, and the frequency is f _{c in the second} horizontal period H _2.
Clock is supplied. Also, two consecutive horizontal periods
In H ₁ and H ₂ , the CCDs (13) and (14) are supplied with a clock from the terminal (23) as shown in FIG. 4E. That is,
A clock having a frequency f _c is supplied in the first horizontal period H ₁ , and a clock having a frequency 2f _c is supplied in the second horizontal period H ₂ .

A control signal S _SW2 is supplied from the terminal (24) to the switch circuits (16) and (19), and the switch circuits (16) and (19)
(19) is the first horizontal period H ₁ and the second horizontal period H ₂ ,
Switching connection is made to the b side and the a side, respectively.

In the above configuration, in the first half of the first horizontal period H ₁ , the CCD (11) and the CCD (12) are driven by the clock of frequency 2f _c.
The color difference signals RY for one horizontal period are written in the first half of each. In the second half of the first horizontal period H ₁ , the frequency
With the clock of 2f _c , the color difference signal BY for one horizontal period is written in the first half of the CCD (11) and the CCD (12), and the first half of the CCD (12) is written.
The color difference signals RY for the horizontal period are transferred to the latter half. The second the horizontal period of H ₂ followed by this, the clock frequency f _c, from CCD (11) and (12), the color difference signals B-Y and R-Y of each one horizontal period is read out , Switch circuits (16) and (19), low-pass filter (1
It is led to output terminals (18) and (21) via 7) and (20).

In the second half of the horizontal period H _2, the clock frequency 2f _c, the CCD (13), the front half portion of the CCD (14), the color difference signals R-Y each one horizontal period is written. Further, in the second half of the second horizontal period H _2, the clock frequency 2f _c, the CCD (13), the front half portion of the CCD (14), with each one horizontal period of the color difference signal B-Y are written ,
The color difference signal RY for one horizontal period written in the first half of the CCD (14) is transferred to the second half. In the subsequent first horizontal period H ₁ , the color difference signals BY and RY for one horizontal period are read from the CCDs (13) and (14) by the clock of the frequency f _c. , Switch circuits (16) and (19), low-pass filters (17) and (2), respectively.
Output terminals (18) and (21) are led out via (0).

Therefore, the output terminals (18) and (21) are connected to each other as shown in FIG.
And C, the blue color-difference signal BY and the red color-difference signal R-Y are respectively doubled in the time axis and continuously obtained.

Even in the time axis expansion circuit of the example of FIG. 3, the CCD (11)
Since clocks are continuously supplied to (14) to (14), generation of lattice defect noise can be prevented.

The CCDs (1) to (4) and the switch circuit (7) in the example of FIG. 1 may be CCD blocks, and this CCD block may be used to configure as shown in FIG. That is,
Two CCD blocks (31) and (32) are provided, one C block
Inverters (3
3), (34) and (35) are arranged, and the output signal of the CCD block (31) and the output signal of the inverter (35) are added by an adder (3
It is to be added in 6). Where the first
Portions corresponding to those in the figure are denoted by the same reference numerals.

With such a configuration, it is possible to reduce fixed pattern noise, improve linearity, and reduce clock noise. For example, if the output signal of the CCD block (31) is as shown in FIG. 6A, the output signal of the CCD block (32) is as shown in FIG.
The output signal of the inverter (35) is as shown in FIG. Therefore, in the adder (36), the signal components are added and doubled, the noise components are canceled out, and the output signal of the adder (36) becomes as shown in FIG. This makes it possible to reduce noise. Further, since the output signals of the two CCD blocks (31) and (32) are added, the linearity can be improved.

Alternatively, the CCDs (11) to (14) and the switch circuits (16) and (19) in the example of FIG. 3 may be CCD blocks, and the CCD blocks may be used to configure as shown in FIG. . That is, two CCD blocks (41) and (42) are provided, and inverters (43), (44) and (45) are arranged at the front stage and the rear stage of one CCD block (42), and the CCD block (41 The output signal of 41) and the output signals of the inverters (44) and (45) are added by the adders (46) and (47). Here, parts corresponding to those in FIG. 3 are designated by the same reference numerals.

With such a configuration, it is possible to reduce fixed pattern noise, improve linearity, and reduce clock noise as in the case of FIG.

Although the above-mentioned embodiment shows the one using the CCD as the charge transfer element, the present invention is preferably applied to the one using the charge transfer element which generates the lattice defect noise similar to the CCD.

〔The invention's effect〕

According to the present invention described above, since the clock can be continuously supplied to the charge transfer element, it is possible to favorably prevent the generation of lattice defect noise due to the pause of the clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the same, FIGS. 3 and 7 are block diagrams showing a time axis expansion circuit, and FIG. FIG. 5 is a block diagram showing a time axis compression circuit, FIG. 6 is a block diagram for explaining the same, FIG. 8 is a block diagram of a conventional example, and FIG. 9 is a block diagram for explaining the same. . (1) to (4) are CCDs, (7) are switch circuits, (8)
Is a low-pass filter, and (9) is an output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masayuki Iwamoto 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-61-2490 (JP, A) JP-A-SHO 57-118490 (JP, A) JP-A-60-143091 (JP, A) JP-A-62-57170 (JP, A)

Claims (1)

[Claims] 1. A first and a third charge transfer element having a bit number for one horizontal period, and a second and a fourth charge transfer element having a bit number for two horizontal periods. And a write clock is supplied to the second charge transfer element in a first horizontal period of two consecutive horizontal periods, and a read clock having a frequency twice that of the write clock is supplied in a second horizontal period. The read clock is supplied to the third and fourth charge transfer elements in the first horizontal period of the two consecutive horizontal periods, and the write clock is supplied in the second horizontal period. The third component color signal is input to the third charge transfer element, the second component color signal is input to the second and fourth charge transfer elements, and the first horizontal signal of the two consecutive horizontal periods is input. period In the first half and the second half of the above, the output signals of the third and fourth charge transfer elements are derived to the output terminals, respectively, and in the first half and the second half of the second horizontal period, respectively, the first and second charge transfer elements are transferred. A time axis compression circuit, wherein an output signal of the element is led to the output terminal.