JPH077761B2 - Integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to a wiring structure of multilayer wiring.

[Conventional technology]

Conventionally, ultra-high speed and large scale, for example, ECL 5K gate ~ 1
In a 0K gate class logic integrated circuit device, the power consumption of the chip exceeds 10 W, and the potential drop due to the resistance of the power supply wiring on the chip cannot be ignored in order to secure a desired noise margin. For this purpose, it is necessary to reduce the wiring resistance to a desired value or less by increasing the line width of the wiring for supplying power and increasing the metal film thickness of the wiring. Therefore, for example, as shown in the layout diagram of the gate array of FIG. 2, a part of the second layer wiring and the first layer wiring are mainly used for circuit connection except for power supply, and the remaining second layer wiring portion is used. Wiring by forming a third layer wiring connected to each other through the opening of the interlayer film only on the power supply wiring and parallelizing the second layer and the third layer wiring. A method of reducing resistance is used. According to this method, the third layer wiring 3 is used only as a power source wiring, and a part of the second layer wiring is also used as a power source wiring. Therefore, a part of the first layer wiring and the second layer wiring used as the signal wiring is used. There are many parts that intersect with.

[Problems to be solved by the invention]

Here, in an ultra-high-speed and large-scale integrated circuit device, the operating speed of a basic circuit such as an inverter is very limited to several tens of psec, but since the chip is large, there is a high probability that the wiring length will increase. The operating speed including the wiring load is considerably slower than the above value due to the parasitic capacitance of the long wiring, and the delay increment due to the wiring load component in the operating speed at the whole chip level cannot be ignored. Then, in order to reduce the delay increment, it is necessary to reduce the parasitic capacitance of the signal wiring.

However, in the above-mentioned conventional integrated circuit device, it is necessary to form the power supply wiring wide in order to reduce the resistance of the power supply wiring (for example, by using the above-described method for parallelizing the second layer and third layer wirings). However, in a chip with high power consumption, the surface area covered by the power supply wiring is 35 to 55% of the total.) Therefore, the parasitic capacitance of the signal wiring intersecting with the power supply wiring becomes larger and larger, There is a drawback that it is incompatible with the reduction of the parasitic capacitance of the signal wiring.

[Means for solving problems]

The present invention solves the above-mentioned drawbacks and improves the wiring structure for reducing the parasitic capacitance between the power supply wiring resistance and the signal wiring while keeping the power supply wiring resistance below a desired value.

That is, according to the present invention, there is a multi-layer wire structure composed of the first layer, the second layer, ..., The nth layer from the main surface of the chip to the upper surface, and the nth layer wiring is the main power supply wiring. Power supply in which the n-th layer wiring and a part of the (n-1) -th layer wiring which is one layer lower than the wiring are connected to each other through an opening formed in the interlayer insulating film between them. In an integrated circuit device having a wiring for power supply, a portion of the power supply wiring which intersects a wiring channel using an n-2 layer wiring which is two layers below the nth layer wiring is the nth layer. Use only wiring.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment in which the present invention is applied to a gate array chip. The first layer wiring passes through the first layer wiring channel 1-1 and the second layer passes through the second layer wiring channel 2-1. The wiring is mainly used for connection (not shown in FIG. 1) in the functional blocks arranged in the cells in the gate array and the connection between the functional blocks, and the third layer wiring is used only for supplying power. ing. On the other hand, in particular, the second-layer power supply wiring 2-2 is connected in parallel with the third-layer wiring 3 through the opening 4 of the second layer and the third-layer insulating film, which contributes to the reduction of the power supply arrangement resistance. On the other hand, the power supply wiring on the first layer wiring channel 1-1 is only the third layer wiring 3, and the second layer wiring does not exist. That is, in the area where the first layer wiring which is the signal wiring used for the connection between the functional blocks and the third layer wiring which is the power supply wiring intersect, the first layer wiring and the third layer wiring are connected.
Since the first and second interlayer insulating films and the second and third interlayer insulating films overlap with the layer wiring 3, the parasitic capacitance per unit area between the first layer wiring and the third layer wiring is reduced. It On the other hand, since the third layer wiring does not require fine pattern formation and the metal film thickness can be increased, even if the third layer wiring is not partially parallelized with the second layer wiring, the wiring below the desired value The width of the third-layer wiring that must be expanded to suppress the resistance is not so large, and as a result, the parasitic capacitance value between the first-layer wiring and the third-layer wiring is reduced. Further, the intersection 7 between the third layer wiring and the first layer wiring in which the first to second interlayer insulating films and the second to third interlayer insulating films which are formed by such a method are overlapped with each other, a wiring layer short circuit due to a pinhole or the like occurs. The probability is reduced and the yield is improved.

〔The invention's effect〕

As described above, according to the present invention, the number of intersections between signal wirings and power supply wirings is reduced, and the interlayer insulating film at the intersections is thickened to reduce the parasitic capacitance generated between the signal wirings and the power supply wirings. There is an effect of reducing. Especially, the effect is great in an ultra-high speed and large scale integrated circuit device. Further, there is an effect that it is possible to reduce the probability of short circuit between wiring layers due to a pinhole between the power supply wiring and the signal wiring, and to improve the yield.

[Brief description of drawings]

FIG. 1 is a layout diagram of an embodiment in which the present invention is applied to a gate array, and FIG. 2 is a layout diagram of a conventional gate array.

Claims (1)

[Claims] 1. A first layer and a second layer, which face upward from the main surface of the chip.
A layer having a multi-layer wiring structure including an nth layer,
While using the layer wiring as the main power supply wiring,
A power supply wiring is formed by interconnecting the n-th layer wiring and a part of the (n-1) th layer wiring which is one layer lower than the wiring through an opening formed in the interlayer insulating film between them. In the integrated circuit device, the nth wiring among the power supply wirings.
An integrated circuit device characterized in that a portion intersecting with a wiring channel using an (n−2) th layer wiring two layers below the layer wiring is composed of only the nth layer wiring.