JPH077797B2 - Dielectric isolation substrate - Google Patents
Dielectric isolation substrateInfo
- Publication number
- JPH077797B2 JPH077797B2 JP59238402A JP23840284A JPH077797B2 JP H077797 B2 JPH077797 B2 JP H077797B2 JP 59238402 A JP59238402 A JP 59238402A JP 23840284 A JP23840284 A JP 23840284A JP H077797 B2 JPH077797 B2 JP H077797B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- silicon
- dielectric isolation
- isolation substrate
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体集積回路装置に係り、特に、高耐圧大電
流化に好適な半導体集積回路装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device suitable for high withstand voltage and large current.
第２図は一般に行なわれている誘電体分離基体の製造方
法を示す。FIG. 2 shows a commonly used method for manufacturing a dielectric isolation substrate.
先ず、（ａ）に示すシリコン単結晶ウエハ１の片側の面
を異方性エツチング法によつて（ｂ）のように分離溝２
を形成した後、全面に誘電体分離用の二酸化シリコン膜
３を被着させる。次いで、この二酸化シリコン膜３上に
シリコン塩化物等の気相反応によつて支持体となるシリ
コン多結晶層４を形成する。次に、単結晶層側を（ｃ）
のα−αで示した位置まで、また、多結晶層側をβ−β
で示した位置まで研磨すれば（ｄ）に示すように互いに
二酸化シリコン膜３で分離された単結晶島領域５をもつ
誘電体分離基体６が得られる。その後、公知の選択拡散
法により、単結晶島内に所望の不純物を拡散し、素子保
護用絶縁膜、Al配線、ダイシング等の工程を経て、半導
体集積回路装置が形成される。First, the surface of one side of the silicon single crystal wafer 1 shown in (a) is separated by the anisotropic etching method as shown in (b).
After forming, the silicon dioxide film 3 for dielectric isolation is deposited on the entire surface. Then, a silicon polycrystal layer 4 serving as a support is formed on the silicon dioxide film 3 by a gas phase reaction of silicon chloride or the like. Next, the single crystal layer side (c)
Up to the position indicated by α-α, and β-β on the polycrystalline layer side.
By polishing to the position shown by (4), a dielectric isolation substrate 6 having single crystal island regions 5 separated from each other by a silicon dioxide film 3 is obtained as shown in (d). After that, a desired impurity is diffused in the single crystal island by a known selective diffusion method, and a semiconductor integrated circuit device is formed through steps such as an element protection insulating film, Al wiring, and dicing.
このような誘電体分離基体による半導体集積回路装置
（以下ICと略す）は、現有のpn接合分離型ICに比較して
電流リークや素子間の寄生効果がないので、制御用小電
力素子とスイツチ用パワー素子との混在が可能である。
しかし、誘電体分離型ICも、特に、パワー素子のパワー
アップ化及び制御用素子の高集積化を考えた場合、技術
的に困難な課題が多い。A semiconductor integrated circuit device (hereinafter abbreviated as IC) using such a dielectric isolation substrate has no current leakage or parasitic effect between elements as compared with the existing pn junction isolation type IC, so a small power element for control and a switch are used. It is possible to mix with the power element for use.
However, the dielectric isolation type IC also has many technically difficult problems, especially when considering power-up of the power element and high integration of the control element.
（イ）第２図に示す構造の誘電体分離型ICは金属ステム
に蝋材で接着固定されているのが通例である。この場
合、単結晶島５内に形成されるパワー素子の放熱は誘電
体分離用二酸化シリコン膜３及びシリコン多結晶層４の
比較的熱伝導の悪い物質を通して行なわれる。このた
め、通常の縦型の単体素子に比べ、大電流化が難かし
い。(A) The dielectric isolation type IC having the structure shown in FIG. 2 is usually adhered and fixed to the metal stem with a wax material. In this case, the heat dissipation of the power element formed in the single crystal island 5 is carried out through the dielectric isolation silicon dioxide film 3 and the silicon polycrystal layer 4 which have relatively poor heat conduction. For this reason, it is difficult to increase the current as compared with a normal vertical single element.
（ロ）従来の誘電体分離基体によるICの耐圧は単結晶島
の厚さによつて決まつている。すなわち、パワー素子に
印加される高電圧によつて拡がる空乏層幅以上の厚さの
単結晶層が必要である。しかし、これまでの誘電体分離
基体の製造技術から考えると、ICの大部分の面積を占め
る制御用小電力素子の単結晶島も、同時に厚くしなけれ
ばならない。異方性エツチング法によつて分離溝２を形
成するには分離溝の主表面上での占める面積は、分離溝
深さの二乗に比例して大きくなる。このため、集積度が
極度に小さくなつてしまう。(B) The withstand voltage of an IC using a conventional dielectric isolation substrate is determined by the thickness of the single crystal island. That is, a single crystal layer having a thickness equal to or larger than the width of the depletion layer that expands due to the high voltage applied to the power element is required. However, considering the conventional technology for manufacturing the dielectric isolation substrate, the single crystal island of the control small power element, which occupies most of the area of the IC, must be thickened at the same time. In order to form the separation groove 2 by the anisotropic etching method, the area occupied by the separation groove on the main surface increases in proportion to the square of the separation groove depth. For this reason, the degree of integration becomes extremely small.
以上の理由からこれまでの誘電体分離基体によるICでは
発明者等の経験上単結晶島厚さは約70μｍ、その耐圧は
300V程度、電流容量は200mA程度が限界であつた。For the above reasons, in the IC using the conventional dielectric isolation substrate, the experience of the inventors is that the single crystal island thickness is about 70 μm, and the withstand voltage is
The limit was about 300V and the current capacity was about 200mA.
これらの欠点を補う考え方として、最近、特開昭55−63
840号公報にその発明が示された。第３図にその構造を
示し概要を説明する。As a way of making up for these drawbacks, recently, JP-A-55-63
The invention was shown in Japanese Patent No. 840. The structure is shown in FIG. 3 and the outline will be described.
誘電体分離基体11はシリコン多結晶層４及び一部の単結
晶領域12、シリコン多結晶層４と分離するための二酸化
シリコン膜３及びシリコン単結晶島５から構成されてい
る。この発明は、前述のように、小電力素子は単結晶島
５内に、大電流・高耐圧素子を単結晶領域12に形成後、
鑞財13でステム14にダイボンドし、大電流素子の発熱を
ステムから放散させようという試みである。The dielectric isolation substrate 11 is composed of a silicon polycrystal layer 4, a part of the single crystal region 12, a silicon dioxide film 3 for separating from the silicon polycrystal layer 4, and a silicon single crystal island 5. According to the present invention, as described above, the small power element is formed in the single crystal island 5, and the large current / high breakdown voltage element is formed in the single crystal region 12.
This is an attempt to die-bond the stem 14 with the solder 13 and dissipate the heat generated by the high-current element from the stem.
この場合、次に述べるような不具合な点がある。In this case, there are problems as described below.
鑞財13は一般には二酸化シリコン膜３等の非金属部に
はぬれない。従つて、このステム14に接着固定されてい
る部分は高耐圧、大電流素子領域の内のPE部のみであ
る。通常のICでは制御用の小電力素子がチップ全体の占
有面積のほとんどを占めるのでステム14への熱の放散効
果が小さい。The solder 13 is generally not wet with the non-metal part such as the silicon dioxide film 3. Therefore, the portion fixedly adhered to the stem 14 is only the PE portion in the high withstand voltage and large current element region. In a normal IC, a small power element for control occupies most of the area occupied by the entire chip, so that the effect of heat dissipation to the stem 14 is small.
部分的に熱の発生があることより、同一基体内に膨張
係数の異なる二種（シリコン単結晶とシリコン多結晶）
の物質が接して共存するため熱発生時の歪が発生し易
い、文献等によるとシリコン多結晶の膨張係数は常温で
もシリコン単結晶の約３倍と言われ、大電流高電圧印加
による歪は極度に大きくなり、素子特性に悪影響を及ぼ
し、さらに、ひどい場合は熱疲労によるチップのクラツ
クや割れも生じることが予想される。Due to partial heat generation, there are two types with different expansion coefficients in the same substrate (silicon single crystal and silicon polycrystal).
Since the above substances coexist in contact with each other, strain is likely to occur when heat is generated. According to literature and the like, the coefficient of expansion of silicon polycrystal is said to be about three times that of silicon single crystal even at room temperature. It becomes extremely large, adversely affects the device characteristics, and in severe cases, cracking or cracking of the chip due to thermal fatigue is expected to occur.
本発明の目的は高耐圧、大電流容量化の可能な誘電体分
離基体を使つた半導体集積回路装置を提供することにあ
る。An object of the present invention is to provide a semiconductor integrated circuit device using a dielectric isolation substrate capable of achieving high breakdown voltage and large current capacity.
本発明誘電体分離基体の特徴とするところは、一対の主
表面を有し、両主表面に隣接するシリコン単結晶の支持
体と、一方の主表面側に露出し誘電体膜を介して支持体
に複数個支持されたシリコン単結晶の島領域とを有し、
支持体において両主表面に露出し複数の接合を有する機
能素子が形成され、機能素子の１個の接合は一方の主表
面側に露出し、他の１個の接合は他方の主表面と機能素
子に隣接する島領域の底部との間に延びている構成とし
た点にある。The feature of the dielectric isolation substrate of the present invention is that it has a pair of main surfaces, a silicon single crystal support adjacent to both main surfaces, and a support exposed through one main surface side through a dielectric film. A plurality of silicon single crystal island regions supported by the body,
A functional element having a plurality of junctions exposed on both main surfaces is formed on the support, one junction of the functional elements is exposed on one main surface side, and the other one junction functions with the other main surface. The point is that it extends between the bottom of the island region adjacent to the element.
以下、本発明の一実施例を第１図（ａ），（ｂ）および
第４図（ａ）〜（ｆ）により詳述する。An embodiment of the present invention will be described below in detail with reference to FIGS. 1 (a) and (b) and FIGS. 4 (a) to (f).
先ず、シリコン単結晶ウエハ１の片側の面を異方性エツ
チング法によつて第１図（ａ）のように分離溝２を形成
した後、（ｂ）に示すように、全面に窒化シリコン膜15
を被着させる。次いで、単結晶島を形成すべき領域８の
窒化シリコン膜をホトエツチングにより除去し、（ｃ）
のように、一方表面全域にわたつて酸素をイオン打込機
により所定のエネルギで打込み、シリコン表面上より一
定の内側へO2イオン領域９を形成する。この時、シリコ
ン単結晶領域となるべき部分７は窒化シリコン膜15で保
護されているので、この下の層にはO2イオンは打込まれ
ない。次に高温中でシリコンウエハを熱処理すると
（ｄ）に示すようにイオン打込時のエネルギにより決定
される深さの場所に二酸化シリコン膜10が形成される。
その後、例えば、熱リン酸等によりシリコン単結晶領域
となるべき部分７の窒化シリコン膜を除去すると（ｄ）
に示すような一方表面全面にシリコンが露出する。この
状態で、シリコン塩化物等による気相反応で、支持体と
なるべき層17を形成する。その支持体層17は下地がシリ
コンであるため当然全域にわたつてシリコン単結晶層と
なる。そして（ｅ）に示すように、Ａ−Ａ′およびＢ−
Ｂ′の位置まで研磨すれば（ｆ）に示す単結晶島領域８
及び単結晶領域７が同一基体内に形成できる。なお、点
線16は気相成長層17とシリコンウエハ１との架空境界線
であり、実際の基体には形成されない。First, an isolation groove 2 is formed on one surface of a silicon single crystal wafer 1 by an anisotropic etching method as shown in FIG. 1A, and then a silicon nitride film is formed on the entire surface as shown in FIG. 15
Put on. Then, the silicon nitride film in the region 8 where the single crystal island is to be formed is removed by photoetching, and (c)
As described above, oxygen is implanted with a predetermined energy by using an ion implanter over the entire surface of one side to form an O 2 ion region 9 on the silicon surface to a constant inner side. At this time, since the portion 7 to be the silicon single crystal region is protected by the silicon nitride film 15, O 2 ions are not implanted into the layer below this. Next, when the silicon wafer is heat-treated at a high temperature, a silicon dioxide film 10 is formed at a depth determined by the energy at the time of ion implantation as shown in (d).
After that, for example, when the silicon nitride film in the portion 7 to be the silicon single crystal region is removed by hot phosphoric acid or the like (d)
Silicon is exposed on the entire one surface as shown in FIG. In this state, a layer 17 to be a support is formed by a gas phase reaction with silicon chloride or the like. Since the base layer 17 is made of silicon, the support layer 17 naturally becomes a silicon single crystal layer over the entire area. Then, as shown in (e), A-A 'and B-
By polishing to the position B ', the single crystal island region 8 shown in (f) is formed.
And the single crystal region 7 can be formed in the same substrate. The dotted line 16 is an imaginary boundary line between the vapor phase growth layer 17 and the silicon wafer 1, and is not formed on the actual substrate.
この基体を形成、公知の選択拡散法により所望の不純物
を拡散形成すれば、第１図に示す構造の新規な誘電体分
離型ICチップが得られる。この図では、例としてシリコ
ン単結晶領域７に、主表面側からnE−pB−nB−pEなるサ
イリスタを示している。By forming this substrate and diffusing desired impurities by a known selective diffusion method, a novel dielectric isolation type IC chip having the structure shown in FIG. 1 can be obtained. In this figure, as an example, a thyristor of n E −p B −n B −p E from the main surface side is shown in the silicon single crystal region 7.
本発明によればシリコン単結晶の支持体を有する誘電体
分離基体が得られ、放熱効果は従来の３倍程度に向上す
る。また、基体チップの他方主表面全面がシリコン面で
あるため臘財は全面に行きわたり、ステムへの完全接着
固定が可能となる。According to the present invention, a dielectric isolation substrate having a silicon single crystal support can be obtained, and the heat radiation effect is improved to about three times that of the conventional one. In addition, since the other main surface of the base chip is entirely silicon, it is possible to spread the entire product and completely adhere and fix it to the stem.
更に、本発明によれば、支持体に形成された複数の接合
を有する機能素子の１個の接合が、他方の主表面と機能
素子に隣接する島領域の底部との間に延びているため、
機能素子の他方の主表面側における通電面積が広くなり
オン電圧の低減及びオフ動作の高速化が図れる。また、
機能素子をサイリスタにすることにより、更にオン電圧
を低減できる。Furthermore, according to the invention, one bond of the functional element having a plurality of bonds formed in the support extends between the other main surface and the bottom of the island region adjacent to the functional element. ,
The current-carrying area on the other main surface side of the functional element is increased, so that the ON voltage can be reduced and the OFF operation can be speeded up. Also,
By using the functional element as a thyristor, the on-voltage can be further reduced.
第１図（ａ）は本発明による誘電体分離基体の断面図、
第１図（ｂ）は本発明による誘電体分離基体の平面図、
第２図，第３図は従来の誘電体分離基体の断面図、第４
図は本発明による誘電体分離基体の製造工程を示す断面
図である。 １…シリコン単結晶ウエハ、２…分離溝、３及び10…二
酸化シリコン膜、４…シリコン多結晶層、５…シリコン
単結晶島、７…単結晶領域、８…単結晶島領域、14…ス
テム、15…窒化シリコン膜。FIG. 1 (a) is a sectional view of a dielectric isolation substrate according to the present invention,
FIG. 1 (b) is a plan view of a dielectric isolation substrate according to the present invention,
2 and 3 are sectional views of a conventional dielectric isolation substrate, FIG.
The drawings are cross-sectional views showing a process for manufacturing a dielectric isolation substrate according to the present invention. 1 ... Silicon single crystal wafer, 2 ... Separation trenches, 3 and 10 ... Silicon dioxide film, 4 ... Silicon polycrystal layer, 5 ... Silicon single crystal island, 7 ... Single crystal region, 8 ... Single crystal island region, 14 ... Stem , 15 ... Silicon nitride film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 建治 東京都千代田区神田駿河台４丁目６番地 株式会社日立製作所内 (56)参考文献 特開 昭52−45275（ＪＰ，Ａ) 特開 昭59−69944（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Suzuki, Kenji Suzuki 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside Hitachi, Ltd. (56) References JP-A-52-45275 (JP, A) JP-A-59- 69944 (JP, A)
Claims (2)
シリコン単結晶の支持体と、一方の主表面側に露出し誘
電体膜を介して支持体に複数個支持されたシリコン単結
晶の島領域とを有し、支持体において両主表面に露出し
複数の接合を有する機能素子が形成され、機能素子の１
個の接合は一方の主表面側に露出し、他の１個の接合は
他方の主表面と機能素子に隣接する島領域の底部との間
に延びていることを特徴とする誘電体分離基体。1. A silicon single crystal support having a pair of main surfaces and being adjacent to both main surfaces, and a plurality of silicons exposed on one main surface side and supported on the support through a dielectric film. A functional element having a single crystal island region and exposed on both main surfaces of the support and having a plurality of junctions is formed.
One junction is exposed on the one main surface side, and the other one junction is extended between the other main surface and the bottom of the island region adjacent to the functional element. .
素子がサイリスタであることを特徴とする誘電体分離基
体。2. The dielectric isolation substrate according to claim 1, wherein the functional element is a thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59238402A JPH077797B2 (en) | 1984-11-14 | 1984-11-14 | Dielectric isolation substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59238402A JPH077797B2 (en) | 1984-11-14 | 1984-11-14 | Dielectric isolation substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61117848A JPS61117848A (en) | 1986-06-05 |
| JPH077797B2 true JPH077797B2 (en) | 1995-01-30 |
Family
ID=17029665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59238402A Expired - Lifetime JPH077797B2 (en) | 1984-11-14 | 1984-11-14 | Dielectric isolation substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077797B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245275A (en) * | 1975-10-08 | 1977-04-09 | Hitachi Ltd | Mis type semiconductor device |
| JPS5621341A (en) * | 1979-07-28 | 1981-02-27 | Oki Electric Ind Co Ltd | Manufacture of dielectric insulating separation substrate |
| JPS5969944A (en) * | 1982-10-14 | 1984-04-20 | Sanken Electric Co Ltd | Manufacture of integrated circuit from which bottom insulator is isolated |
-
1984
- 1984-11-14 JP JP59238402A patent/JPH077797B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61117848A (en) | 1986-06-05 |
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