JPH0778865A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] The resist does not peel off during the manufacturing process and interferes with the manufacturing process. Moreover, the metal wiring on the SiO ₂ film and the electrodes formed on the base and emitter are peeled off. To provide a high-quality semiconductor device that does not wear. [Structure] A base portion, a channel stopper portion, and an emitter portion are formed on a predetermined surface layer of the base portion on a surface layer of a silicon substrate, and a SiO ₂ film is formed on the substrate.
Contact holes reaching the base portion, the emitter portion, and the channel stopper portion are formed in the iO ₂ film, and a base electrode and an emitter electrode are formed in the contact holes immediately above the base portion and the emitter portion, respectively. The semiconductor device has a metal wiring formed on the silicon oxide film, and has a configuration in which the sidewall of the contact hole and its peripheral portion and the PSG layer immediately below the metal wiring are removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view schematically showing a sectional structure of a conventional general transistor.

[0003] surface layer of the silicon substrate 41, P ⁺ layer is selectively diffused into the base over the scan unit 43, also the emitter section 44 and the channel stopper 45 N ⁺ layer is selectively diffused There is. Further, a SiO ₂ film 42 is formed on the silicon substrate 41 excluding a part of each of the base portion 43, the emitter portion 44 and the channel stopper portion 45, and the SiO ₂ film 42 is selectively formed on the SiO ₂ film 42. The Al wiring 50 is formed. A phosphorus silicate glass (hereinafter referred to as a PSG layer) 46 is uniformly formed on the SiO ₂ film 42. A collector electrode 51 is formed on the back surface of the silicon substrate 41.

The above-mentioned PSG layer 46 is formed as a passivation film, and has an important function of gettering metal ions such as Na ⁺ and K ⁺ in the oxide film which give various obstacles to various characteristics of the transistor. It is an essential element for semiconductor devices. That is,
This passivation film can prevent moisture from entering the device and harmful impurities from entering the device, and can prevent corrosion of the wiring and deterioration of the device.

FIG. 5 shows a method of manufacturing such a conventional transistor. First, the base portion 43 is formed by selectively diffusing the P ⁺ layer in the surface layer of the silicon substrate 41. Further, the SiO ₂ film 42 is formed on the silicon substrate 41.
Are formed [FIG. 5 (a)].

Next, the base portion 43 and the silicon substrate 4
By selectively diffusing the N ⁺ layer into the first surface layer, the emitter portion 44 and the channel stopper portion 45 are formed, respectively. Normally, in the manufacturing process of an NPN type transistor, PS is formed on the SiO ₂ film 42 during the diffusion of the emitter.
The G layer 46 is simultaneously formed [FIG. 5 (b)].

Next, a resist 47 is formed by a photolithography process in order to form contact holes for taking out the base electrode and the emitter electrode [FIG.
(C)]. Then, the SiO ₂ film 42 is etched to open the emitter portion 44, the base portion 43, and the channel stopper portion 45 to form an emitter electrode 49 and a base electrode 48, and at the same time, on the SiO ₂ film 42. The Al wiring 50 is formed on a predetermined portion. Finally, when the collector electrode 51 is formed, the transistor shown in FIG. 4 is completed.

[0008]

By the way, the PSG layer formed during the diffusion of the emitter has a function of gettering Na ions and metal ions, but on the other hand, the adhesion between the PSG layer 46 and the resist 47 is weak. In the manufacturing process of 1), there is often a problem that the resist 47 is peeled off when the SiO ₂ film 42 is etched at the time of forming the contact hole shown in FIG. 5C, for example. Also, this PSG
The layer 46 also has weak adhesion to the emitter electrode 49, the base electrode 48, and the Al wiring 50, which are Al electrodes to be formed later, and therefore the emitter electrode 49, the base electrode 48, and A
l wiring 50 is peeled off from the surface of the SiO ₂ film 42, also, the problem or the state of being floated from the surface of the SiO ₂ film 42 has occurred. This deteriorates various characteristics of the transistor and lowers the reliability of the device.

The present invention has been made in order to solve these problems, and the resist is not peeled off in the manufacturing process to hinder the manufacturing process. Moreover, the metal wiring on the SiO ₂ film and the base portion are prevented. It is an object of the present invention to provide a high quality semiconductor device in which the electrodes formed in the emitter portion are not peeled off.

[0010]

In order to achieve the above object, the semiconductor device of the present invention is such that a base portion and a channel stopper portion are selectively formed in a surface layer of a silicon substrate and the base portion thereof is formed. An emitter portion is formed on a predetermined surface layer of the base portion, a silicon oxide film is formed on the substrate, and the silicon oxide film reaches the base portion, the emitter portion and the channel stopper portion. Contact holes are formed, a base electrode and an emitter electrode are formed in the contact holes directly above the base portion and the emitter portion, and metal wiring is selectively formed on the silicon oxide film. In the formed semiconductor device, a rinse is formed on the silicon oxide film except the side wall of the contact hole and its peripheral portion and immediately below the metal wiring. Characterized by Kate glass is formed.

[0011]

The PSG has weak adhesion to the Al wiring, the Al electrode, and the resist used in the manufacturing process.

In the present invention, since the PSG layer is formed under the emitter electrode, the base electrode, and the metal wiring, except for the side wall of the contact hole and its periphery, the PSG layer is formed in the removed portion. The formed electrodes and wirings do not float or peel off.

Also in the manufacturing process, the resist can be formed in a state where the PSG layer around the contact hole to be formed is removed, the adhesion between the resist and the silicon oxide film becomes high, and the silicon oxide film is formed. The resist does not come off during the etching.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of an embodiment of the present invention.

The base layer 3 is formed on the surface layer of the silicon substrate 1.
The P ⁺ layer is selectively diffused, also, the emitter portion 4 formed on the base over the scan unit 3, the channel stopper 5 N ⁺
The layers are selectively diffused. Further, a SiO ₂ film 2 is formed on the silicon substrate 1, and contact holes 12a, 12b, 12c reaching the emitter portion 4, the base portion 3 and the channel stopper portion 5 are formed. An emitter electrode 9 and a base electrode 8 are formed in the contact holes 12a and 12b, respectively. Also, S
An Al wiring 10 is selectively formed on the iO ₂ film 2. Immediately below the Al wiring 10 on the SiO ₂ film 2,
The PSG layer 6 for gettering and blocking is formed just below the emitter electrode 9 and the base electrode 3 and on the SiO ₂ film 2 except the sidewalls of the contact holes 12a, 12b and 12c and their peripheral portions. There is. A collector electrode 11 is formed on the back surface of the silicon substrate 1.

The manufacturing process of the embodiment of the present invention having the above construction will be described below with reference to FIG. First, the silicon substrate 1
The base portion 3 is formed by selectively diffusing the P ⁺ layer into the surface layer of. Furthermore, on this silicon substrate 1, S
The iO ₂ film 2 is formed [FIG. 5 (a)].

Next, by selectively diffusing the N ⁺ layer into the base portion 3 and the surface layer of the silicon substrate 1, the emitter portion 4 and the channel stopper portion 5 are formed, respectively. During this emitter diffusion, the PSG layer 6 is replaced with the SiO ₂ film 2
Simultaneously formed on top [FIG. 5 (b)]. The steps so far are the same as the conventional one.

Next, in order to remove the PSG layer 6 on the SiO ₂ film 2 on which the emitter electrode 9, the base electrode 8 and the Al wiring 10 will be formed in the subsequent steps, a resist is formed by using a photolithography process. Patterning is performed with 7a. Then, only the PSG layer 6 is etched using a predetermined etching solution. At this time, since only the PSG layer 6 is etched, the etching time is short, and the adhesiveness of the resist during etching is not a particular problem here [FIG. 5 (c)].

Next, after removing the resist 7a, a patterning for forming the contact holes 12a, 12b, 12c is performed by the resist 7b by using the photolithography process again. After that, the contact hole 12 is formed by etching the SiO ₂ film 2.
a, 12b, 12c are formed. At this time, since the PSG layer 6 around the contact hole has already been removed,
The adhesion between the resist 7b and the SiO ₂ film 2 at this location is
It is almost the same as the adhesion between a normal SiO ₂ film and a resist,
There is no peeling of the resist [FIG. 5 (d)].

Further, as shown in FIG.
And the contact hole 12 formed on the base portion 3
An emitter electrode 9 and a base electrode 8 are formed on a and 12b, respectively. Further, the Al wiring 10 is formed on a predetermined portion of the SiO ₂ film 2 where the PSG layer 6 has been removed in advance. Then, finally, the collector electrode 11 is formed on the back surface side of the silicon substrate 1 to complete this embodiment.

The PSG layer 6 is, as described above,
Although it has an action of gettering metal ions such as Na ⁺ and K ⁺ in the oxide film, in the process of manufacturing the embodiment of the present invention, the PSG layer 6 is formed once on the entire surface of the wafer and then selectively formed. This gettering is sufficiently performed because it is removed.

Further, FIG. 2 is a schematic sectional view of another embodiment of the present invention. In this embodiment, in addition to the structure of the previous embodiment, the PSG / CVD film 12 is formed on the PSG layer 6. This is because PSG is
Since it also has a function of blocking a ⁺ ions and metal ions, the emitter electrode 9, the base electrode 8 and the Al wiring 1
It is formed so that 0 also serves as protection. In this manufacturing process, after the electrodes 8 and 9 and the Al wiring 10 are formed, the Al wiring 10 and the PSG previously formed are formed.
The PSG / CVD film 12 is formed on the film 6 by the CVD method.

Therefore, in the embodiment of this structure, Al
Wiring can be protected and is less susceptible to mechanical damage. Therefore, the quality and reliability of the device are further improved.

Although the embodiment of the present invention has been described by taking a transistor chip as an example, it goes without saying that the present invention can be applied to other semiconductor elements.

[0025]

As described above, according to the present invention,
Since the configuration is such that the side wall of the contact hole and its peripheral portion and the phosphosilicate glass immediately below the metal wiring are removed, the metal wiring on the SiO ₂ film and the electrodes formed on the base portion and the emitter portion are considered to be floating. In addition, the resist does not peel off or peel off, and the resist is not peeled off during the manufacturing process of the SiO ₂ film for the contact hole as in the conventional case, which hinders the manufacture. As a result, a semiconductor device with high quality and high reliability can be realized. In addition, the manufacturing process can be performed smoothly and efficiently.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of the present invention.

FIG. 2 is a schematic sectional view of another embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing method of the embodiment of the present invention with time.

FIG. 4 is a schematic sectional view of a conventional example.

FIG. 5 is a schematic cross-sectional view showing a manufacturing method of a conventional example over time.

[Explanation of symbols]

 1 ... Silicon substrate 2 Silicon oxide film 3 Base 4 Emitter 5 Channel topper 6 Phosphorus silicate glass 8 ..Base electrode 9 .... Emitter electrode 10 ... Al wiring

Claims (1)

[Claims] 1. A base portion and a channel stopper portion are selectively formed on a surface layer of a silicon substrate, and an emitter portion is formed on a predetermined surface layer of the base portion. Is formed with a silicon oxide film, and
Contact holes reaching the base portion, the emitter portion, and the channel stopper portion are formed in the silicon oxide film, and a base electrode and an emitter are formed in the contact holes immediately above the base portion and the emitter portion, respectively. In a semiconductor device in which an electrode is formed and a metal wiring is selectively formed on the silicon oxide film, on the side wall of the contact hole and its peripheral portion and on the silicon oxide film except directly under the metal wiring. A semiconductor device, wherein a phosphosilicate glass is formed.