JPH0779408B2 - Fever recorder - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat recording apparatus, and more particularly to a heat recording apparatus for generating gradation in recorded image (pixel) density.

In the heat recording, the expression of the density change of the recorded image can be realized by controlling the energization amount (current magnitude or energization time width) of the heating resistor that generates the recording heat for each recording pixel. As the energization amount control, a timer is provided corresponding to each heating resistor in the energization control circuit of each heating resistor,
It is conceivable to set the operating time width of each timer according to the recording density. However, in a heat generation recording device such as Facsimile, since the number of heat generation resistors whose energization is controlled simultaneously reaches 128 or 256, 128 or 256 timers are used according to the above timer control. There must be. Further, if the number of gradation steps of the density change to be expressed is increased, the operation time width setting circuit of each timer also increases. In the case of the digital control circuit method, a counter is used as a timer and a shift register is used as an operation time width setting circuit, but there is a drawback that it becomes large if a large number of counters or shift registers are provided in a recording head or a control device. .

FIG. 1 is a block diagram showing an example of such a conventional heat generating recording apparatus. In order to simplify the explanation, nine heat generating resistors are divided into three blocks of three and the recording density of each recording pixel is divided into three blocks. It is simplified to be controlled by a 3-bit gradation information signal.

The analog image signal S is converted by the A / D converter 1 for each recording pixel into a 3-bit binary number (which can represent 8 steps) gradation information signal corresponding to the density, and then stored in the line memory 2. Remembered. As the line memory 2, for example, a random access memory (RAM) is used, and in order to make the gradation information signal correspond to the recording pixel position, the heating resistors 3a to 3i of the heating recording head 3 corresponding to the recording pixel position. To the address signal B formed by the outputs of the signal counter 4 and the block counter 5 for counting the numbers corresponding to the signal lines 3s ₀ , 3s ₁ , 3s ₂ and the block lines 3b ₀ , 3b ₁ , 3b ₂ Therefore, the storage or read address is determined. Information of each digit (each bit) in each recording pixel read from the line memory 2 is stored in each digit shift register 6a, 6b, 6c. The output of each digit shift register 6a-6c is output to each signal line 3s ₀
Up to 3s ₂ timer counters 7a, 7b, and 7c are loaded with a carry signal that is output each time 3 pixels are read out, and each counter 7a to 7c is a number corresponding to the loaded gradation information signal. The switch elements 8s ₀ , 8s ₁ and 8s ₂ of the signal switch 8 are turned on for a period of time for counting the energization control clocks, and the voltage of the power source 9 is applied to the signal lines 3s _{0 to} 3s ₂ . The output of the block counter 5 is decoded by the decoder 10 so that the switch elements 11a, 11b, 11c of the block switch 11 are sequentially selectively turned on every three pixel recording, and the switch 8 is used to control the energization of the heating resistor 3a. Block lines 3b ₀ , 3b ₁ ,, to which ~ 3i are connected
Select 3b ₂ .

According to such a heat recording apparatus, the number of bits of the gradation information signal for each recording pixel is increased, so that the shift register
If the number of 6a ~ increases, and the number of heating resistors 3a ~ whose energization is controlled simultaneously in each block increases, the counter 7a ~
It is easy to understand that the number of

SUMMARY OF THE INVENTION It is an object of the present invention to provide a thermal recording apparatus capable of realizing thermal recording with gradation by controlling the energization time width of the heating resistor of the thermal recording head with a simple circuit configuration.

A feature of the present invention is that a heating recording head having a plurality of blocks, which is a set of a plurality of heating resistors, is provided, and a plurality of heating resistors corresponding to each of the plurality of pixels are provided according to gradation information of the plurality of pixels to be recorded. In a heat generation recording apparatus that controls the energization time to each to generate heat, and records by using this heat generation, a memory circuit that stores the recording density of pixels to be recorded as gradation information and a read address is output to the memory circuit. And a reading means for reading the gradation information from the memory circuit,
Comparing the gradation information and the gradation level with a unit for repeating the read operation of the gradation information of the pixel corresponding to the heating resistor in the block a plurality of times corresponding to the number of gradation steps while updating the gradation level, An energization information generation unit that generates a binary signal as energization information for controlling energization of the heating resistor a plurality of times, and the energization information that has been generated for a plurality of pixels and is converted into a parallel signal to convert the signals into a plurality of pixels. Of the plurality of heating resistors corresponding to each of the shift register that outputs in parallel as energization information to each, and the parallel signal output from the shift register is input and stored, and the parallel signal is output to the plurality of heating resistors. A latch circuit that outputs as energization information, a second drive circuit that selects a specific block from a plurality of blocks, and a heating resistor in the selected block that corresponds to a parallel signal from the latch circuit are provided. In heating a recording apparatus that includes a first driving circuit for driving electricity.

An embodiment of the present invention will be described below with reference to the block diagram shown in FIG. 2 and the timing chart shown in FIG.
In order to simplify the explanation, this embodiment is divided into three blocks of nine heating resistors and divided into three blocks, and the recording density of each recording pixel is controlled in three steps.

In FIG. 2, the analog image signal S is recorded pixel by pixel.
It is converted into a binary gradation information signal corresponding to the density by the A / D converter 1 and stored in the line memory 2. A RAM is used as the line memory 2 as described above, and a storage or read address is determined by an address signal B formed by the outputs of the address counter 4 and the block counter 5 as described above. The block switch 11 controls each heating resistor of the heating recording head 3 by the decoder 10.
Also, the structure for selectively connecting to the power source 9 by means of the address switch 8 for energization and heat generation is the same as that of the conventional heat recording apparatus shown in FIG. Threshold level generation counter
The reference numeral 12 changes the level of the threshold signal D each time the control of energization to a predetermined heating resistor is executed for a predetermined time. The switch hold signal D is compared. The output signal E of the comparator 13 is high level when the level of the gradation information signal C is higher than the level of the threshold signal D, and is low level otherwise. The shift register 14 serial-parallel converts the output signal E from the comparator 13 and outputs the serial-parallel converted signal to the latch circuit 15.
The reference numeral 15 latches this signal to the address switch 8 for recording signals G ₀ , G ₁ ,
Give G ₂ . The flip-flop 16 is for delaying the generation of the recording start signal H from the recording command signal K by one latch time, and is triggered by the carrier signal I of the address counter 4 and output from the block counter 5 at the end of recording one line. It is cleared by the stop signal M. The latch circuit 17 holds the block address output from the block counter 5 for a plurality of times of energization control for a predetermined time.

The operation of the heat-generating recording apparatus having the above structure will be described with reference to the timing chart of FIG. The gradation information signal indicating the recording density of the pixel to be recorded in the 0th block is such that the 0th pixel is “0”, the 1st pixel is “1”, and the 2nd pixel is “2”. Now, the reproducing / recording operation will be described on the assumption that the gradation information signal is stored in the addresses "0", "1", "2" of the line memory 2.

First, the address counter 4, the block counter 5, and the threshold value generation counter 12 are initialized by the recording command signal K generated for each recording line, and the read address B of the line memory 2 is output as address 0. The gradation information signal C is "0", and the threshold signal D is "0". Therefore, the output signal E of the comparator 13 is low level, and this output signal E is stored in the shift register 14 as the first clock signal A. The first clock signal A increments the address counter 4 and uses the read address B as the first address to read "1" of the gradation information signal C stored at that address. At this time, since the threshold signal D remains "0", the output signal E of the comparator 13 becomes high level, and this output signal E is stored in the shift register 14 as the second clock signal A. Further, the second clock signal A increments the address counter 4 and uses the read address B as the second address to read "2" of the gradation information signal C stored in the address. Also at this time, the threshold signal D is "0", so that the output signal E of the comparator 13 is at a high level.
Is stored in the shift register 14 with the third clock signal A. The address counter 4 outputs a carry signal I when the third clock signal A is input, and the content of the shift register 14 is latched by the latch circuit 15 by this signal I. Since the recording mode signal L is at the high level in the reproducing / recording operation mode, the flip-flop is set by the carrier signal I.
The recording start signal H from the output Q of 16 becomes high level, the recording signal G ₀ corresponding to the pixel at address ₀ is low level, the recording signal G ₁ corresponding to the pixel at address ₁ is high level, and the second
The recording signal G ₂ corresponding to the pixel of the address becomes high level,
Address switch 8 corresponding to high-level recording signals G ₁ and G ₂
Conducts. At this time, the latch circuit 17 latches the block address for selecting the 0th block, and the decoder
Block 10 selects block switch 11 corresponding to block 0. Therefore, in this case, energization for a predetermined time is performed on the heating resistors 3b and 3c in the heating recording head 3 shown in FIG.

At the third clock signal A, the output of the address counter 4, that is, the read address signal B for the line memory 2 is returned to the address 0, and the threshold level generating counter 12 is incremented by the carrier signal I to obtain the threshold signal D. Becomes "1". As a result, the gradation information signal C corresponding to the pixel at address 0 read out from the line memory 2 becomes "0" and the threshold signal D becomes "1", so that the output signal E of the comparator 13 is at a low level. And the output signal E is stored in the shift register 14 as the fourth clock signal A. The fourth clock signal A increments the address counter 4 and uses the read address B as the first address to read "1" of the gradation information signal C stored at that address. At this time as well, the threshold signal D is "1", so the output signal E of the comparator 13 remains at the low level, and this output signal E is stored in the shift register 14 as the fifth clock signal A. . The fifth
The second clock signal A increments the address counter 4 and uses the read address B as the second address to read "2" of the gradation information signal C stored at that address. At this time also, the threshold signal D is "1", so that the comparator 13
Output signal E becomes high level, and this output signal E is stored in the shift register 14 as the sixth clock signal A. The address counter 4 outputs the carry signal I when the sixth clock signal A is input, so that the contents of the shift register 14 are latched by the latch circuit 15. At this time, the contents latched from the shift register 14 to the latch circuit 15 are that the 0th address and the 1st address are low level, the 2nd address is high level, and after the 6th clock signal A is generated, Only the recording signal G ₂ corresponding to the pixel at the second address becomes high level. Since the latch circuit 17 remains latching the block address for selecting the 0th block, the heating resistance is not generated in the heating recording head 3 shown in FIG. 1 for a predetermined time after the generation of the 6th clock signal A. Only body 3c. When the threshold hold level generation counter 12 receives the second carrier signal I of the address counter 4, it outputs the carrier signal J and the threshold signal D returns to "0". The block counter 5 uses this carrier signal J
Is incremented by 1 to make the block address the first block.

As a result, the read address B for the line memory 2
Becomes the third address (the first address of the first block), and the gradation information signals C of the third to fifth addresses are read and stored in the shift register 14 in the same manner as described above. Then, the latch circuit 17 latches the first block address by the carrier signal I output from the address counter 4 when the first reading of the first block is completed, and the heating resistor of the first block is generated. Switching to energization control for 3d to 3f for a predetermined time. Therefore, until this point, the power supply to the heating resistor 3c at the second address in the 0th block is continued.

After the energization control for the final predetermined time for the final block is finished, a carrier signal is output from the block counter 5, which is inverted by the inverter 18 to reset the flip-flop 16 as the stop signal M, and the counters 4, 5 and
Stop 12 functions.

According to the energization control for the heating resistor as described above, the energization time width for the heating resistor corresponding to the pixel at address 0 is "0", and the energization time width for the heating resistor corresponding to the pixel at address 1 is Is "1", and the energization time width for the heating resistor corresponding to the pixel at the second address is "2", so that the energization time width corresponding to the previously assumed recording density of the pixel to be recorded can be obtained.

Comparing the configurations of the conventional apparatus shown in FIG. 1 and the apparatus according to the present invention shown in FIG. 2, a timer counter is required for each heating resistor of the heating recording head in the conventional apparatus. The invention device does not need this, and conventionally, when the number of gradations of the recording density is increased, the number of shift registers proportional to the number of digits when it is converted into a binary number is required. Since the number of digits of the level generation counter is increased, the structure is correspondingly simplified.

As described above, according to the present invention, a memory circuit that stores the recording density of a pixel to be recorded as gradation information, a reading unit that reads the gradation information from the memory circuit, and a floor of a pixel corresponding to a heating resistor in a block. A means for repeating the read operation of the tone information a plurality of times corresponding to the number of tone steps while updating the tone level, compares the tone information and the tone level, and energizes the heating resistor with a binary signal. Energization information generating means for generating a plurality of times as energization information for controlling, and the energization information generated is input to a plurality of pixels and converted into a parallel signal, which is output in parallel as energization information to each of a plurality of heating resistors. Shift register, a latch circuit that inputs and stores a parallel signal output from the shift register, and outputs the parallel signal as energization information to a plurality of heating resistors, and a specific block in a plurality of blocks. A second driving circuit for selecting a click,
1st which energizes and drives the heating resistor in the selected block
And the drive circuit of, to control the energization time to the heating resistor,
For a given recording pixel, the gradation level is updated a plurality of times while updating the gradation level, and the heat generation amount of each heating resistor is controlled by the sum of the energization times of a plurality of times. There is an effect that it is possible to realize heat recording with tonality.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional heat recording apparatus, FIG. 2 is a block diagram of a heat recording apparatus according to the present invention, and FIG. 3 is its operation timing chart. 2 ... Line memory, 3 ... Heat recording head, 4 ... Address counter, 5 ... Block counter, 8 ... Address switch, 12 ... Threshold level generation counter,
13 …… Comparator, 14 …… Shift register.

Claims (1)

[Claims] 1. A heat generating recording head having a plurality of blocks, each of which is a set of a plurality of heat generating resistors, and the plurality of heat generating resistors corresponding to each of the plurality of pixels according to gradation information of a plurality of pixels to be recorded. In a heat generation recording apparatus that controls the energization time to each of the elements to generate heat and records by utilizing this heat generation, a memory circuit that stores the recording density of the pixel to be recorded as gradation information, and a read address to the memory circuit. Is output to read the gradation information from the storage circuit, and the reading operation of the gradation information of the pixel corresponding to the heating resistor in the block is performed while updating the gradation level. Means for repeating a plurality of times corresponding to the above, and a plurality of times as the energization information for comparing the gradation information and the gradation level and controlling the energization of the heating resistor with the binary signal. A plurality of energization information generating means, and the generated energization information is input to a plurality of pixels and converted into a parallel signal, and energization information to each of the plurality of heating resistors corresponding to each of the plurality of pixels. A parallel output shift register, a latch circuit that inputs and stores the parallel signal output from the shift register, and outputs the parallel signal as energization information to the heating resistors, A second drive circuit that selects a specific block from among the blocks; and a first drive circuit that energizes and drives a heating resistor in the selected block corresponding to the parallel signal from the latch circuit. A heat generating recording device characterized by being provided.