JPH078015B2 - Vertical sync signal detection circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a vertical synchronizing signal detecting circuit for a television receiver, and more particularly to a synchronizing signal which can be obtained from a digitized television signal.

[Technical background of the invention]

In an analog television receiver, the vertical synchronizing signal detection circuit has a time constant circuit, and when integrated, external parts are required, which is an obstacle to reducing the number of pins of the integrated circuit. . Recently, a digital television receiver has been developed, and a circuit capable of separating a vertical synchronizing signal from a digitized television signal is desired.

In this case, it may be considered that the vertical sync detection circuit detects the digital sync signal by integrating it. However, by simply integrating the digital composite sync signal,
If a noise signal is input, it may malfunction. Recently, digital video tape recorders and video disc players have also been developed, and the vertical synchronization signals of these may not necessarily match the format of the vertical synchronization signal obtained from the broadcast signal. Therefore, there is a demand for a vertical sync signal detection circuit capable of coping with a change in the format of the vertical sync signal.
Furthermore, when the vertical synchronization detection circuit is combined with the digital circuit of the next stage, a circuit that can easily synchronize the vertical synchronization signal with the basic clock of the digital circuit of the next stage is desired.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and provides a vertical synchronization signal detection circuit that can be easily integrated into a circuit, does not require external parts, and can switch time constants in integration processing. To aim.

[Outline of Invention]

In the present invention, in order to detect a digital vertical synchronizing signal, as shown in FIG. 1, a digital integrating circuit is composed of two complement type adder circuits 13, a gate control circuit 16 and a latch circuit 17. . With this, the time constant of the integrating circuit can be switched by the output of the NAND circuit 15. Therefore, it is possible to deal with the case where there is a large difference in the format of the synchronization signal and the lack of the synchronization signal. More specifically, the vertical synchronizing signal detecting circuit of the present invention further includes a synchronizing means for synchronizing the input digital composite synchronizing signal with the first clock and outputting the synchronized digital composite synchronizing signal, and at least a sign bit input. Section (corresponding to the input section A8 of the embodiment), upper side data bit input section (corresponding to the input section A3 to A7 of the embodiment) to which the same signal as the sign bit is input, lower side data bit input section (of the embodiment example) (Corresponding to the input unit A1), a middle-order data bit input unit to which a data bit higher than the lower data bit input unit and lower than the upper data bit input unit is input (input of the embodiment) Department
Corresponding to A2) and a signal to be added, and a 2's complement type adder circuit in which "1" is supplied to at least one bit of the middle data bit input section, and the synchronized digital Means for supplying the sign bit input section of the adder circuit after inverting the composite synchronization signal, and the same signal as the signal supplied to the sign bit input section,
A means for supplying to the upper data bit input section, a NAND operation of the synchronized digital composite sync signal and the time constant switching signal, and a result of the operation is at least one bit of the lower data bit input section. Means for supplying the output of the latch circuit as an added signal to the added signal input unit, overflow and underflow are detected from the calculation result of the adder circuit, and predetermined for overflow and underflow, respectively. And a control means for outputting the value of 1 from the gate control circuit, and a value of the output of the latch circuit is set to a first value in the reset state, and a value of the output of the latch circuit is set to the first value in the set state. Means for outputting a signal according to a vertical synchronizing signal, which is reset by a second value smaller than the value; And a second synchronization means for synchronizing a signal corresponding to a linear synchronous signal at a second clock.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which the digital composite synchronizing signal CS is supplied to the shift register 11. The composite sync signal CS is separated from the digital television signal, and is a signal of a level higher than the separation level when compared with the data of the separation level.

The composite synchronization signal CS is shifted by the block φ1 in the shift register 11, passes through the gate circuit 12, and is commonly input to the A3 to A8 input sections that are the input ends of the adder circuit 13.
The gate circuit 12 has an inverter 14 and a NAND circuit 15,
The output of the inverter 14 is commonly supplied to the previous A3 to A8 input sections. The output of the NAND circuit 15 is supplied to the A1 input section of lower bits than the A3 to A8 input sections and the A2 input section. The NAND circuit 15 performs a logical operation on the output of the shift register 11 and the switching signal SW.

Since the value of the A1 input section of the adder circuit 13 which is the output of the NAND circuit 15 can be fixed by the switching signal SW, the time constant of the integrating circuit composed of the adder circuit 13, the gate control circuit 16 and the latch circuit 17 can be switched. it can.

The outputs Σ1 to Σ7 of the adder circuit 13 are supplied to the input units D1 to D7 of the latch circuit 17 via the gate control circuit 16. The outputs Q1 to Q7 of the latch circuit 17 are supplied to the other input ends of the adder circuit 13, which are the B1 to B7 input sections.

The output of the gate control circuit 16 is controlled by the overflow detection output HL and the underflow detection output LL.
The overflow detection output HL is obtained by calculating a logical product of a signal obtained by inverting the output Σ7 of the adder circuit 13 by the inverter 18 and the output Σ8 by the AND circuit 19. The underflow detection output LL is obtained by calculating the outputs Σ7 and Σ8 in the NAND circuit 20.

The adder circuit 13 is a circuit for performing addition by taking the complement of 2, and the output increases when the output of the shift register 11 is continuous at "1" and decreases when the output of the shift register 11 is continuous at "0". .

It is now assumed that the switching signal SW has been set to 1. In this case, the output of the NAND circuit 15, that is, the value of the A1 input part of the least significant bit of the adder circuit 13 is the output of the shift register 11 being “1”.
When it is, it is “0”, and when it is 0, it is “1”. Therefore, the output of the latch circuit 17 of the integrating circuit has a smaller slope when the phenomenon occurs than when it increases. Further, when the switching signal SW is fixed to "0", the output of the NAND circuit 15 is always 1, and the inclination when the output of the latch circuit 17 decreases is the same as before.
The slope when increasing becomes steeper than before.

FIG. 2 shows operation waveforms when the switching signal SW is "1".

When the composite synchronizing signal CS extracted from the broadcast wave shown in FIG. 2 (the drawing shows a waveform, but actually the digital data representing the level) is input, the output of the latch circuit 17 is
It is regulated by the overflow level HL1 and underflow level LL1 shown in FIG.

The outputs Q2 to Q7 of the latch circuit 17 are supplied to the NAND circuit 21, and the NAND circuit 21 is also supplied with the clock φ1 via the inverter 22. The output of the NAND circuit 21 is used as the set input of the flip-flop circuit 23. Further, as the reset input of the flip-flop circuit 23, the upper bit output Q7 in the latch circuit 17 is used.

The output Q23 of the flip-flop circuit 23 becomes high level when the output level of the latch circuit 17 becomes level S1, and becomes low level when the output level of the latch circuit 17 becomes level S2. The output Q23 is supplied to the shift register 25 driven by the floc φ2 (shown in FIG. 2). Output Q of one stage of shift register 25
The inverted output (1) of the first and second stages and the signal obtained by inverting the clock φ2 by the inverter 26 are supplied to the NAND circuit 27.

Therefore, each signal φ2, Q1-25, ▲ ▼ of this circuit section
-25 becomes as shown in FIG. 2, and the rising detection signal Vmi of the vertical synchronizing signal can be obtained.

The clock φ2 may be the same as the previous clock φ1, but when the detection signal Vmi is used in the digital circuit of the next stage, it is better to synchronize it with the basic clock of the circuit of the next stage. Therefore, it is better to use the clock frequency used in the next stage or a multiple thereof as the clock φ2.

The detection signal Vmi may be further input to the gate circuit 30 of the next stage in order to facilitate matching with the circuit of the next stage and to prevent erroneous output. Gate circuit 30
After deriving its output DVmi for a period of time (eg about 20
Horizontal scanning period) The output is prohibited. This prohibition operation is obtained by the gate control operation by the prohibition pulse generation circuit 31 that outputs the prohibition pulse EH in response to the output DVmi of the gate circuit 30. This is effective in completely eliminating the noise NS when it is mixed in the detection signal Vmi as shown in FIG. After the rise of the vertical synchronizing signal, noise may be mixed in due to a waveform change due to a ghost, which is also effective in preventing malfunction in such a case. In addition, the noise caused by disturbance due to some cause is detected signal NS
It is also effective as a countermeasure when mixed in.

FIG. 4 shows operation waveforms when the above circuit obtains a detection signal when the format of the vertical synchronizing signal is different from the normal one. Since the vertical synchronizing signal has a narrow pulse width, it takes time for the output level of the integrating circuit to reach a predetermined level. Therefore, in this case, the switching signal SW
Is set to 0 and the time constant of the integrating circuit is made small,
The rising edge is made steep to ensure the detection of the sync signal.

According to the above embodiment, when the switching signal SW is set to "1",
The rising slope of the integration operation can be set to "2" and can be set to "3" when the switching signal SW is set to "0". The falling slope is "1" in all cases.

If the period of "1" of the vertical synchronizing signal is about 48 μsec or more, the output Q23 can be obtained even with the inclination 2, but if it is about 48 μsec or less, the output Q23 cannot be obtained with the inclination 2. Therefore, as described above, the vertical sync signal "1"
In the case of a special signal with a short period of, it can be dealt with by switching the slope. Such a vertical sync signal "1"
The one having a short period is set as a tape format for preventing diving, for example.

For a signal of a special format as described above, a sampling clock φ1 having a frequency of 2/1 of the subcarrier frequency, that is, a period of about 560 nsec is suitable. This depends on the number of bits of the integrating circuit and the length of the "1" period of the vertical synchronizing signal. Also, the clock φ
As 2 is used 8 μsec, for example. This is to facilitate the operation of Japanese Patent Application Laid-Open No. 55-159674, which was filed by the present inventor.

〔The invention's effect〕

As described above, according to the present invention, it is easy to form an integrated circuit, and external parts are unnecessary. Further, by using the 2's complement type adder circuit, the integration time constant can be easily switched, and the synchronization detection in the special format and the synchronization detection in the weak electric field are also accurate.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2, 3, and 4 are operation waveform diagrams of the circuit of FIG. 1, respectively. 11 ... Shift register, 12 ... Gate circuit, 16 ... Adding circuit,
14 ... Inverter, 15 ... NAND circuit, 16 ... Gate control circuit, 17 ... Latch circuit, 21 ... NAND circuit, 23 ... Flip-flop circuit, 25 ... Shift register, 26 ... Inverter, 27
... AND circuit, 30 ... Gate circuit, 31 ... Inhibit pulse generation circuit.

Claims (1)

[Claims] 1. Synchronizing means for synchronizing an input digital composite synchronizing signal with a first clock and outputting a synchronized digital composite synchronizing signal, and at least a sign bit input section, and a signal the same as the sign bit is inputted. Upper side data bit input section, lower side data bit input section, middle side to which lower side data bit input section and higher side data bit than the lower side data bit input section are input 2 has a data bit input section and an added signal input section, and "1" is supplied to at least one bit of the middle data bit input section 2
Complement type adder circuit, means for inverting the synchronized digital composite sync signal, and then supplying the sign bit input part of the adder circuit, and the same signal as the signal supplied to the sign bit input part. To
A means for supplying to the upper data bit input section, a NAND operation of the synchronized digital composite synchronizing signal and the time constant switching signal, and a result of the operation is at least one bit of the lower data bit input section. Means for supplying a calculation result of the adder circuit to a latch circuit via a gate control circuit; a means for supplying an output of the latch circuit to the addable signal input unit as an added signal; Overflow and underflow are detected from the calculation result of the adder circuit, and control means for outputting a predetermined value from the gate control circuit at the time of overflow and underflow respectively, and a value of the output of the latch circuit when the reset state is the first value. Value is set, and the value of the output of the latch circuit is smaller than the first value in the set state. And a second synchronizing means for synchronizing the signal according to the vertical synchronizing signal with a second clock, the means being for resetting at a second value and outputting a signal according to the vertical synchronizing signal. A vertical synchronization signal detection circuit characterized by: