JPH0793696B2 - Vertical sync separation circuit - Google Patents

Description

The present invention relates to a vertical sync separation circuit.

[Outline of Invention]

According to the present invention, in a circuit for separating a vertical sync pulse from a composite sync pulse, a counter for measuring the time from the sync edge and a counter for measuring the sync level time are provided.
The vertical synchronizing pulse is separated by detecting the output order of both counters.

[Conventional technology]

If the vertical sync pulse is separated from the composite sync pulse by analog processing, the number of external parts will increase when integrated into an IC, which is not suitable for downsizing or cost reduction.

Therefore, it is considered that the vertical sync pulse is separated by digital processing. As a method for this, a method of separating the vertical sync pulse by discriminating the waveform of the vertical sync pulse, or an "H" level of the composite sync pulse is used. Also, a method of separating the vertical synchronizing pulse by making the "L" level correspond to up-counting and down-counting of the counter has been considered.

[Problems to be solved by the invention]

However, with the former method, when noise is mixed in the vertical sync pulse, such as during special playback in a VTR or video disc player, the waveform of the vertical sync pulse cannot be determined, so the vertical sync pulse can be separated correctly. I can not do it. Also, in the latter method, when noise with a duty ratio other than 50%, such as white noise, is mixed, the count of the counter is biased to up-count or down-count, so overflow or underflow occurs and the vertical sync pulse is also generated. It becomes impossible to separate correctly. Moreover, the circuit scale becomes large in any method.

The present invention has been made in view of the above problems, and it is an object of the present invention to eliminate noise in the vertical sync pulse during vertical sync separation by digital processing, such as during special reproduction in a VTR or a video disc player. The vertical sync pulse can be reliably separated from the composite sync pulse when mixed, or even when noise with a duty ratio of not 50%, such as white noise, is mixed. It is an object of the present invention to provide a vertical sync separation circuit capable of achieving sync separation.

[Means for solving problems]

First counting means for counting the time from the leading edge of these pulse components in a composite synchronizing pulse including at least a horizontal synchronizing pulse component and a vertical synchronizing pulse component, and second counting means for counting the pulse width of each pulse component. And the first
Outputs a first reset instruction signal when the counting means counts the horizontal synchronization pulse component determination period, and outputs a second reset instruction signal when the first counting means counts the vertical synchronization pulse component determination period. Based on the period setting circuit that outputs and outputs the third reset instruction signal when the first counting unit counts the forced reset period and the input of each reset instruction signal from the period setting circuit, Resetting means for resetting the count values of the first and second counting means, and the first means when the count value of the second counting means reaches the first predetermined value within the horizontal synchronizing pulse component determination period. Invalidating the reset instruction signal of No. 1 and invalidating the second reset instruction signal when the count value of the second counting means reaches the second predetermined value within the vertical synchronization pulse component determination period. And a vertical synchronization pulse generation circuit for outputting a pulse having a predetermined pulse width as a vertical synchronization pulse from the time when the count value of the second counting means reaches the second predetermined value. Configure.

[Action]

In the vertical sync separation circuit according to the present invention, first, the first counting means counts the time from the leading edge of these pulse components in the composite sync pulse including at least the horizontal sync pulse component and the vertical sync pulse component, In the second counting means, the pulse width period of each pulse component is counted.

In the subsequent period setting circuit, the first counting means outputs the first reset instruction signal when the first counting means counts the horizontal synchronization pulse component determination period, and the first counting means determines the vertical synchronization pulse component determination period. The second reset instruction signal is output at the time of counting, and the third reset instruction signal is output at the time of counting the forced reset period by the first counting means.

The reset means resets the count values of the first and second counting means based on the input of each reset instruction signal from the period setting circuit. In this case, the counting operation by the first and second counting means is performed from the beginning.

Here, when a pulse component having a short pulse width, for example, a horizontal synchronizing pulse component is input to the second counting device from the start of counting by the first counting device, even when the horizontal synchronizing pulse component determination period elapses. Since the count value of the second counting means is not the first count value, the period setting circuit outputs the first reset instruction signal, and the count value of each counting means is reset. Will be
The first counting means again starts the operation of counting the horizontal synchronization pulse component determination period.

On the other hand, when the vertical synchronizing pulse component is input to each counting means, the pulse width of the pulse component is long, so that the count value of the second counting means is equal to the first predetermined value within the horizontal synchronizing pulse component determination period. As a result, the first reset instruction signal from the period setting circuit is invalidated by the vertical synchronizing pulse detection circuit, and the counting by each counting means is continued.

Then, within the next vertical synchronization pulse component determination period,
The count value of the second counting means becomes the second predetermined value, whereby the second reset instruction signal from the period setting circuit is invalidated, and the counting of each counting means is continued.

In this case, the vertical synchronizing pulse generating circuit outputs a pulse having a predetermined pulse width having a leading edge when the count value of the second counting means reaches the second predetermined value as a vertical synchronizing pulse. become. Then, the count value in each counting means is reset by the third reset instruction signal based on the counting of the forced reset period from the period setting circuit, and the counting in the counting means is restarted from the beginning.

If the count value of the second counting means does not reach the second predetermined value even after the vertical synchronization pulse component determination period has elapsed, the second reset signal output from the period setting circuit is output. Since the instruction signal is not invalidated by the vertical synchronizing pulse detection circuit, the count value in each counting means is reset by the second reset instruction signal, and the counting in each counting means is restarted from the beginning.

That is, in the present invention, the pulse width of the pulse component to be counted is short with reference to the vertical synchronizing pulse determination period, and the count value of the counting means is the second predetermined value even after the period has elapsed. If not, the pulse component of the counting target is not recognized as the vertical synchronizing pulse component, the count value of the counting means is reset and the arrival of the next pulse component is awaited, while the count value within the above period When the pulse width is long enough to reach the second predetermined value, the pulse component to be counted is recognized as the vertical synchronizing pulse component, and the vertical synchronizing pulse is separated.

As a result, in vertical synchronization separation by digital processing,
For example, the pseudo vertical sync pulse component may be generated when noise is mixed in the vertical sync pulse, such as during special playback on a VTR or video disc player, or when noise whose duty ratio is not 50%, such as white noise, is mixed. Even if it occurs, it is not separated as a normal vertical sync pulse, but it can be separated as a vertical sync pulse only when a pulse component having a pulse width within the allowable range as a vertical sync pulse component arrives. Becomes

Moreover, since all digital processing is possible, reliable vertical synchronization separation can be achieved without increasing the circuit scale.

〔Example〕

In FIG. 1, Ps indicates a composite synchronizing pulse, and this pulse Ps has a positive polarity as shown in FIG. 3A, for example. In this pulse Ps, Ph is a horizontal synchronizing pulse component, Pv is a vertical synchronizing pulse component, and Pe is an equalizing pulse component.

Then, this pulse Ps is supplied to the detection circuit (1), the rising edge (leading edge) of the pulse Ps is detected, and its detection output is supplied to the set input S of the RS flip-flop (2), and its output Q ₂ Are supplied to the count enable input EN of the counter (3). This counter (3) has pulse Ps
The clock pulse Pc having a frequency sufficiently higher than that of the pulse Ps is supplied to the clock input (count input) CK, and Q ₂
When = H, the pulse Pc is counted. Then, the count value Q ₃ of the counter (3) is supplied to the decoder (4), Q ₃ = when "m _1" - "m _4", the output M ₁ ~M ₄ each decoder (4) " H "level.

In this case, the number of pulses Pc in one horizontal period is H
For example, 0 <“m ₁ ” <1 / 2H ... (i) “m ₁ ” <“m ₂ ” <“m ₃ ” <“m ₄ ”.

Further, the pulse Ps is supplied to the count enable input EN of the counter (6), and the clock pulse Pc is supplied to the clock input (count input) CK of the counter (6). This counter (6) measures the period of Ps = “H”, and its count value Q ₆ is supplied to the decoder (7), and when Q ₆ = “n ₁ ”, “n ₂ ”, Decoder (7)
The outputs N ₁ and N _{2 of} are set to the “H” level. In this case, if the number of pulses Pc in the pulse width period of the pulse Ph is h [cycle], for example, h <“n ₁ ” <“m ₁ ” <“n ₂ ” <“m ₂ ” ... … (Ii).

If the number of clock pulses Pc in the input period of the vertical synchronizing pulse component Pv is V [cycle], “m ₂ ” <V From the arrival time t ₄ of the vertical synchronizing pulse component Pv to t ₈ corresponding to “m ₂ ”. Let N be the number of equalizing pulses Pe included in the period
Further, when the number of pulses of the clock pulse Pc in the pulse width period of the equalizing pulses Pe and E [cycle], and "n _2" = "m _2" -N × E-D. Here, D is a value that determines the margin of vertical sync pulse detection, and is determined as follows.

Although there is a vertical sync pulse, a similar signal may be generated due to dropout or the like. In that case, the count value Q ₃ will increase due to dropout or the like. Then,
Since its value may reach "n ₂ ",
I want to make "n ₂ " larger.

The conflicting conditions above are the target system, the VTR
And obtain the optimum value by experimenting with a video disc player.

FIG. 3 shows an example of constants suitable for a video disc player, which satisfies the above conditions. This number is G [cycle]
Then, “m ₂ ” = 2G “n ₂ ” = “m ₂ ” −2 × E−D D = E.

Then, the decode outputs M ₁ and N ₁ are supplied to the detection circuit (5), and when the output M ₁ becomes “H” level before the output N ₁ , the detection output Q ₅ of the detection circuit (5) Is set to "H" level. Further, when the decode outputs M ₂ and N ₂ are supplied to the detection circuit (8) and the output M ₂ becomes “H” level before the output N ₂ , the output Q ₈ of the detection circuit (8) becomes “H”. H "level. Further, the decode output M ₄ is supplied to the reset input R of the detection circuits (5) and (8).

The outputs Q ₅ , Q ₈ and the decode output M ₄ are supplied to the reset input R of the circuits (2), (3), (6) through the OR circuit (9). Also, decode outputs N ₂ and M ₃ are RS
It is supplied to the set input S and the reset input R of the flip-flop (10), and its Q output is taken out as a separated vertical synchronizing pulse Pu.

In such a configuration, in the period before the arrival time t ₄ of the vertical synchronizing pulse component Pv in the composite synchronizing pulse Ps, the third
As shown in FIG. A, the horizontal synchronization pulse Ph causes Ps at the time point t ₁ .
= "H" becomes, this is detected by the detection circuit (1), since the flip-flop (2) is set by the detection output, as shown in FIG. B, Q from the time t _{1 2} =
It becomes “H”. Therefore, counting from the counter (3) is permitted from the time point t ₁ , and as shown in FIG.
Q ₃ increases from “0” at time t ₁ .

Further, at a Ps = "H" at time t _1, since thereby allowed even count of the counter (6), increases from as shown in FIG. D, the count value Q ₆ is the time t ₁ '0 " I will do it.

Then, at Ps = "L" at time t _2, is inhibited count of the counter (6) is, the count value Q ₆ is held to the value of the time t _2.

Then, when Q ₃ = “m ₁ ” at time t ₃ , the decoded output M ₁
With but becomes M ₁ = "H", since the time t ₃ previously not been N ₁ = "H", i.e., became so M ₁ = "H" above the point t _3, which is detected Q ₅ detected by circuit (5)
= "H". Therefore, this signal Q ₅ resets the circuits (2), (3), and (6), and from time t ₃ to Q ₂
= “L”, Q ₃ = “0”, Q ₆ = “0”.

Then, such an operation is repeated before the arrival time t ₄ of the vertical synchronizing pulse component Pv. Note that the same operation is repeated even if there is the equalization pulse Pe according to the equation (i).

Then, at the time point t ₄ , Ps = “H” due to the vertical synchronization pulse component Pv.
Then, as in time t ₁ , Q ₂ becomes “H” and the count values Q ₃ and Q ₆ increase from “0”.

Then, since the period of the “H” level is long in the vertical synchronizing pulse Pv, Q ₆ = “n ₁ ” at time t ₅ , and then Q ₃ = at time t _6.
It becomes "m ₁ ". Therefore, in this case, since the decode output N ₁ becomes “H” level before the decode output M ₁ , the detection output Q ₅ remains “L” level, and the circuits (2), ( 3), (never reset to 6) is applied, the counter (3), (count 6) is followed, the count value Q _3, Q ₆ is increases further. It should be noted that the time points t ₅ and t ₆ are not reversed by the equation (ii).

Then, at time t _7, when Q ₆ = “n ₂ ”, N ₂ = “H”, so the flip-flop (10) is set, and Pu = “H”, as shown in FIG. .

However, at this time t ₇ , Q ₃ <“m ₂ ”, and the detection circuit (8) detects the detection output only when the decode output M ₂ becomes “H” before the decode output N _2. since Q ₈ is become "H", the by comprising a Q ₆ = "n _2" at time t _7, that is, the decoded output n ₂ at time t ₇ is earlier than the decode output M ₂ "H" by now, also remains of Q ₈ = "L" thereafter. Therefore, the circuits (2), (3) and (6) are not reset, and the counter (3) and
The count of (6) continues.

Then, Q ₃ = “m ₂ ” at time t ₈ , and further at time t ₃ .
When Q ₃ = “m ₃ ”, flip-flop (1
0) is reset and Pu becomes “L” from time t ₉ .

Further, when Q ₃ = “m ₄ ” at time t ₁₀ , M ₄ =
Since it becomes "H", the circuit (2), (3),
(6) is reset, thereafter, until the next vertical sync pulse Pv arrives, the operation of the time t ₁ ~t ₃ are repeated.

Therefore, when the vertical synchronizing pulse component Pv arrives, the pulse Pu can be obtained from the output terminal of the flip-flop (10), that is, the vertical synchronizing pulse Pv can be separated, as shown in FIG.

Thus, according to the present invention, the vertical synchronizing pulse Pv can be separated from the composite synchronizing pulse Ps. In this case, in particular, according to the present invention, since it is all digital processing, it can be easily integrated into an IC and no external parts are required. Therefore, the effect of IC conversion is great.

Also, before the time point t ₈ when Q ₃ = “m ₂ ” (time point t ₇ ).
, If Q ₆ = “n ₂ ”, that is, if N ₂ = “H” is not satisfied (before M ₂ = “H”) within the specified time, then Q ₈ =
Since the circuits (2), (3) and (6) are reset to “H” and reset, even if a pseudo vertical sync pulse is generated due to dropout or the like, it can be separated as a normal vertical sync pulse Pv. Few. Further, the position of the vertical sync pulse Pv with respect to the horizontal sync pulse Ph is shifted by 1/2 horizontal period between the odd field period and the even field period and the even field period and the odd field period. You can get Pu.

Further, since the leading edge of the pulse Pu (time point t ₇ ) is always constant with respect to the starting time point t ₄ of the original vertical synchronization pulse Pv, when performing signal processing with the vertical synchronization pulse Pv as the time reference, For example, when a signal such as a frame number multiplexed in the vertical blanking period is taken out in a video disc player, a part of the circuit can be shared and the processing can be easily performed.

In the above description, the detection circuits (5) and (8) can be composed of an RS flip-flop (11) and an AND circuit (12), for example, as shown in FIG.

〔The invention's effect〕

According to the vertical sync separation circuit of the present invention, in vertical sync separation by digital processing, even when noise is mixed in the vertical sync pulse, such as during special reproduction in a VTR or a video disc player, white noise is eliminated. The vertical sync pulse can be reliably separated from the composite sync pulse even if noise whose duty ratio is not 50% is mixed in, such as, and moreover, reliable vertical sync separation can be achieved without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a vertical sync separation circuit according to the present invention, and FIG. 2 is a circuit showing another configuration of detection circuits (5) and (8) in the vertical sync separation circuit according to the embodiment. FIG. 3 and FIG. 3 are time charts showing the signal processing of the vertical sync separation circuit according to the embodiment. (1), (5) and (8) are detection circuits, (3) and (6) are counters, (4) and (7) are decoders, (2) and (10).
Is a flip-flop.

Claims (1)

[Claims] 1. A first counting means for counting a time from a leading edge of these pulse components in a composite sync pulse including at least a horizontal sync pulse component and a vertical sync pulse component, and a pulse width of each pulse component. The second counting means and the first counting means output a first reset instruction signal when the horizontal synchronizing pulse component determination period is counted, and the first counting means counts the vertical synchronizing pulse component determination period. A period setting circuit that outputs a second reset instruction signal at the time point and a third reset instruction signal when the first counting unit counts the forced reset period, and each reset from the period setting circuit. Reset means for resetting the count values of the first and second counting means based on the input of the instruction signal; and the second means within the horizontal synchronizing pulse component determination period. The first reset instruction signal is invalidated when the count value of the second count means reaches the first predetermined value, and the count value of the second count means is set to the first reset instruction signal within the vertical synchronization pulse component determination period. A vertical synchronizing pulse detection circuit for invalidating the second reset instruction signal when the predetermined value of 2 is reached, and a predetermined value from the time when the count value of the second counting means reaches the second predetermined value. And a vertical sync pulse generation circuit for outputting a pulse having a pulse width as a vertical sync pulse.