JPH0783065B2 - Method for manufacturing semiconductor non-volatile memory - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor nonvolatile memory.

[Conventional technology]

A channel injection type non-volatile memory is mainly used as the non-volatile memory.

Conventionally, in a semiconductor memory device having this kind of channel injection structure, the source and drain regions are formed in a self-aligned manner with respect to the control gate, and further, in order to reduce the memory cell size, the junction depth of the source and drain regions is increased. The structure has been adopted in which the hole is made shallow to prevent punch-through and the efficiency of injecting charges into the floating gate is increased by hot electron injection at the drain junction. However, this structure has a drawback that the source resistance increases and the cell write characteristics deteriorate because the junction depth of the source is shallow. Especially, the influence is great in the cell array. In order to eliminate such a defect, there is known a semiconductor nonvolatile memory having a channel injection structure in which a drain side junction is shallow and a source side junction is deeply formed.

2 (a) to 2 (f) are cross-sectional views of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor nonvolatile memory.

As shown in FIG. 2A, a field insulating film 2 for element isolation is selectively provided on the main surface of a P-type silicon substrate 1 to partition an element formation region, and the element formation region is provided with a first
The gate insulating film 3 is formed. Then, a polycrystalline silicon layer 4 is deposited on the entire surface and selectively etched to cover the floating gate electrode and drain formation regions.

Next, as shown in FIG. 2B, the polycrystalline silicon layer 4
The surface of is thermally oxidized to form the second gate insulating film 5.
Next, a polycrystalline silicon layer 6 is deposited on the entire surface, and a photoresist film 7 having a gate electrode forming pattern is selectively formed on the polycrystalline silicon layer 6 in the element forming region.

Next, as shown in FIG. 2C, the polycrystalline silicon layer 6 is etched by using the photoresist film 7 as a mask to form a control gate electrode 8, and then the photoresist film 7 is again formed.
Using the as a mask, the first and second gate insulating films 3 and 5 and the polycrystalline silicon layer 4 are sequentially etched to form the floating gate electrode 11, and the photoresist film 7 is removed.

Next, as shown in FIG. 2D, a photoresist film 14 is applied on the entire surface and patterned to mask the drain forming region of the element forming region. Next, photoresist film
N-type impurities are ion-implanted by using 14 and the control gate electrode 8 and the field insulating film 2 as a mask to form a source region 9 in the element forming region.

Next, as shown in FIG. 2E, the photoresist film 14 is removed, and N-type impurities are ion-implanted using the control gate electrode 8 and the field insulating film 2 as a mask to form a drain region 10 shallower than the source region 9. Form.

Next, as shown in FIG. 2 (f), the interlayer insulating film 13 is formed on the entire surface.
Are deposited and selectively etched to provide contact openings in the source region 9 and the drain region 10. next,
Electrode wirings 13 are provided selectively in contact with the source region 9 and the drain region 10 of the opening.

[Problems to be solved by the invention]

In the conventional method for manufacturing a semiconductor nonvolatile memory described above, since a mask made of a photoresist film is used to form a shallow drain region and a diffusion region having different depths of a deep source region, an alignment process is required. However, there is a problem that the process is complicated.

An object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory, which has a simplified process.

[Means for solving problems]

According to a method of manufacturing a semiconductor nonvolatile memory of the present invention, a field insulating film for element isolation is selectively formed on a main surface of a one-conductivity-type semiconductor substrate to partition an element formation region, and a first area is formed on the surface of the element formation region. Forming a gate insulating film, and depositing and patterning a first polycrystalline silicon layer on a surface including the first gate insulating film, and forming a floating gate electrode and a drain forming region on the first gate insulating film. Covering the top, forming a second gate insulating film on the surface of the first polycrystalline silicon layer, and forming a second polycrystalline silicon on the surface including the first and second gate insulating films. Selectively depositing a photoresist film having a gate electrode forming pattern on the second polycrystalline silicon layer on the device forming region after depositing a layer, and using the photoresist film as a mask A step of etching the polycrystalline silicon layer to form a control gate electrode, and ion implantation of an impurity of opposite conductivity type by using the photoresist film and the field insulating film as a mask to form a deep source region and a shallow drain region in the element region. And a step of sequentially etching the second gate insulating film and the first polycrystalline silicon layer on the drain region using the photoresist film as a mask to form a floating gate electrode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1 (a), a field insulating film 2 for element isolation is selectively provided on the main surface of a P-type silicon substrate 1 to partition an element formation region, and the first element formation region is formed on the surface of the element formation region.
The gate insulating film 3 is formed. Next, the first polycrystalline silicon layer 4 is deposited and patterned on the surface including the gate insulating film 3 to cover the floating gate electrode and the drain formation region.

Next, as shown in FIG. 1B, the polycrystalline silicon layer 4
The surface of is thermally oxidized to form the second gate insulating film 5.
Next, a second polycrystalline silicon layer 6 is deposited on the surface including the first and second gate insulating films 3 and 5, and a gate electrode forming pattern is formed on the polycrystalline silicon layer 6 in the element forming region. The photoresist film 7 it has is selectively formed.

Next, as shown in FIG. 1C, the polycrystalline silicon layer 6 is etched using the photoresist film 7 as a mask to form the control gate electrode 8. Next, using the photoresist film 7 and the field insulating film 2 as a mask, N-type impurities are ion-implanted to form a deep source region 9 and a shallow drain region 10.

Next, as shown in FIG. 1D, the gate insulating film 3 on the source region 9, the gate insulating film 5 on the drain region 10 and the polycrystalline silicon layer 4 are etched using the photoresist film 7 as a mask. And removed to form the floating gate electrode 11.

Next, as shown in FIG. 1 (e), the interlayer insulating film 12 is formed on the entire surface.
Is deposited and selectively etched to form contact openings in the source region 9 and the drain region 10, and electrodes 13 are formed to selectively contact the source region 9 and the drain region 10 in the opening. Configure a non-volatile memory.

〔The invention's effect〕

As described above, according to the present invention, the shallow drain region and the deep source region are once formed by performing the ion implantation to form the drain / source region with the first polycrystalline silicon layer left on the drain formation region. Since it can be formed simultaneously by the ion implantation, the photoresist film for the ion implantation which is required in the conventional method is not required, so that the process can be simplified.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are views of a conventional semiconductor nonvolatile memory. FIG. 9 is a cross-sectional view of the semiconductor chip in the order of steps for explaining the manufacturing method. 1 ... P-type semiconductor substrate, 2 ... field insulating film, 3 ...
... gate insulating film, 4 ... polycrystalline silicon layer, 5 ... gate insulating film, 6 ... polycrystalline silicon layer, 7 ... photoresist film, 8 ... control gate electrode, 9 ... source region, 10 ...
… Drain region, 11 …… Floating gate electrode, 12 …… Interlayer insulating film, 13 …… Electrode wiring, 14 …… Photoresist film.

Claims (1)

[Claims] 1. A field insulating film for element isolation is selectively formed on a main surface of a one-conductivity-type semiconductor substrate to define an element forming region, and a first gate insulating film is formed on the surface of the element forming region. Depositing a first polycrystalline silicon layer on the surface including the first gate insulating film and patterning the floating gate electrode and the drain forming region on the first gate insulating film to cover the region; Forming a second gate insulating film on the surface of the first polycrystalline silicon layer; and depositing a second polycrystalline silicon layer on the surface including the first and second gate insulating films, and then the device. A step of selectively forming a photoresist film having a gate electrode forming pattern on the second polycrystalline silicon layer on the formation region; and etching the second polycrystalline silicon layer using the photoresist film as a mask Forming a control gate electrode by using the photoresist film and the field insulating film as a mask to implant impurities of opposite conductivity type to form a deep source region and a shallow drain region in the element region, and the photoresist film Using the mask as a mask to sequentially etch the second gate insulating film and the first polycrystalline silicon layer on the drain region to form a floating gate electrode.