JPH0784006A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] To obtain a semiconductor integrated circuit including an A / D conversion means or a D / A conversion means having a storage means therein and capable of efficiently performing a pass / fail test for the storage means. [Structure] The clock selector 8 includes an internal clock signal S.
6 and the DSP clock signal S5, the internal clock signal S6 is output to the memory 71 as the selected clock signal S8 when the internal clock signal S6 is normally received, and when the test mode signal for instructing the test of the memory 71 is received. DS
When P2 receives the test mode signal for instructing the test of the memory 71, it outputs the read / write control signal S9 for controlling the write operation and read operation of the memory 71 to the memory 71, and reads / writes to / from the memory 71 via the digital data bus 4. Then, the test for the internal memory 21 is diverted as it is, and the memory test for the memory 71 is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit comprising an A / D converter or a D / A converter having a storage device therein and a digital signal processing means for performing various signal processing on a digital signal. Regarding

[0002]

2. Description of the Related Art FIG. 9 shows an example of a conventional semiconductor integrated circuit for digital signal processing in which analog and digital are mixed. Figure 9
As shown in FIG. 1, the semiconductor integrated circuit 1 includes an A / D & D / A converter 11 and a DSP 2.

The A / D & D / A converter 11 fetches an analog signal from the outside through an analog signal input terminal 112, A / D-converts it, and then uses an internal memory 7 to perform oversampling processing and the like. A digital signal is output from the input / output terminal 102 to the digital data bus 4, or a digital signal on the digital data bus 4 is D / A converted and an analog signal is output to the analog signal output terminal 113.

At this time, it operates in synchronization with the internal clock signal output from the clock signal generation circuit 6. The clock signal generation circuit 6 generates an internal clock signal based on the external clock signal obtained via the external clock input terminal 107 and outputs it to the memory 7 or the like.

The memory 7 operates in synchronization with the internal clock signal obtained from the clock signal generation circuit 6. Further, at the time of test, by giving a read control signal from the external data read signal input terminal 108, a read operation can be performed from the outside through the external data input / output terminal 105 and the selector 18, which will be described later, and from the external data write signal input terminal 109. By applying the write control signal, a write operation can be performed from the outside via the external data input / output terminal 105 and the selector 18, which will be described later.

On the other hand, the DSP 2 performs various digital signal processes such as an encoding process and a decoding process on a digital signal on the digital data bus 4 transmitted and received via the input / output terminal 101 and the external data input / output terminal 105.
At this time, it operates in synchronization with the internal clock signal generated from the clock signal generation circuit 5. The clock signal generation circuit 5 generates an internal clock signal based on the external clock signal obtained from the external clock input terminal 106. In addition,
103 is a fail flag terminal to which Fail information, which is the test result of the self-diagnostic test of the DSP 2, is output,
Reference numeral 104 is an external address terminal.

The digital data bus 4 is A / D & D.
Connected to the input / output terminal 102 of the A / A converter 11, the input / output terminal 101 of the DSP 2 and the selector 18,
/ A converter 11 memory 7 and digital section and DSP
Sending and receiving digital signals with 2.

The selector 18 normally connects the DSP 2 and the external data input / output terminal 105. During the test, a digital signal is exchanged between the memory 7 and the digital section in the A / D & D / A converter 11 and the outside of the semiconductor integrated circuit 1 by a test mode signal given through the test mode signal line 111. to enable.

The test mode signal line 111 is A / D & D /
It is connected to the A converter 11, the DSP 2, the D / A converter 12, and the test mode terminal 110.

In such a configuration, the A / D & D / A
Digital signals are exchanged between the converter 11 and the DSP 2 via the digital data bus 4. That is, the analog signal input via the analog signal input terminal 112 is converted into a digital signal by the A / D & D / A converter 11 and subjected to oversampling processing, and then the digital signal is transferred via the digital data bus 4 to the DSP 2 Send to.

The DSP 2 performs various digital signal processing on the digital signal. Then, the digital signal resulting from the signal processing is A / D &
Output to the D / A converter 11 and external data input / output terminal 10
Output to 5.

The A / D & D / A converter 11 D / A converts the digital signal received from the DSP 2 and outputs an analog signal from the analog signal output terminal 113.

When testing a semiconductor integrated circuit with a built-in DSP in the conventional mixed analog-digital mode as shown in FIG. 9, the analog part test, the digital part test and the DSP2 test of the A / D & D / A converter 11 are performed. It is necessary to perform three tests. However, the order of testing does not matter.

Now, consider a test of the memory 7 inside the A / D & D / A converter 11. Since the digital signal inside the A / D & D / A converter 11 is a hard wired logic, that is, a logic circuit having no instruction decoding function, D
If SP2 has an instruction decoding function, it cannot perform an executable self-diagnosis test. For this reason,
Conventionally, when the A / D & D / A converter 11 was tested, the memory 7 was directly accessed from the outside to perform the test.

Hereinafter, as an example, the memory 7 shown in FIG. 9 is a RAM.
The test operation in the case of will be described. When testing the memory 7, an external clock signal is applied from the external clock input terminal 107, a test mode signal is applied to the test mode terminal 110, and the selector 18 connects the digital data bus 4 to the external data input / output terminal 105. Then, the input digital data is set to the external input / output terminal 105. Then, writing and reading are repeatedly performed on the memory 7 to perform a test. Switching between writing and reading is performed in accordance with a control signal input to the external data reading signal input terminal 108 and the external data writing signal input terminal 109 with the test mode terminal 110 activated. At this time, the address of the memory 7 is incremented by one address according to the clock signal.

At present, several types of test methods for RAM have been proposed, but here, consider the case where writing and reading of "1" and "0" of all bits are performed. Assuming that the memory 7 is 4 kW RAM,
"0" write "0" read "1" write "1" read 4kWord x 4 = 16k times, it is necessary to access the memory. That is, 16 k test vectors are required to test the memory 7.

[0017]

As described above, the analog / digital mixed semiconductor integrated circuit in which the A / D conversion means or the D / A conversion means having the storage means therein is formed together with the digital signal processing means such as the DSP. In the circuit, A / D
The storage means inside the conversion means or the D / A conversion means is tested from outside the semiconductor integrated circuit.

Since this test is performed separately from the test of the digital signal processing means, there is a problem that the time required for the test and the number of test vectors become enormous.

The present invention has been made in order to solve the above problems, and it is possible to efficiently test the A / D conversion means or the storage means inside the D / A conversion means.
It is an object of the present invention to obtain a semiconductor integrated circuit having an A / D conversion means having a storage means inside or a D / A conversion means.

[0020]

A semiconductor integrated circuit according to a first aspect of the present invention is an analog signal input terminal for receiving an analog signal from the outside, a test mode terminal for receiving a test mode signal from the outside, and a digital data bus. And A for A / D converting the analog signal obtained through the analog signal input terminal to output a digital signal.
And a digital signal processing means for receiving the digital signal and performing various digital signal processing on the digital signal, the digital signal processing means generating a first clock signal. A first clock signal generating means is provided, the first clock signal is also output to the outside of the digital signal processing means, and a first storage means capable of reading and writing in synchronization with the first clock signal is further provided. A storage means test function for determining pass / fail of the first storage means, wherein the A / D conversion means includes second clock signal generation means for generating a second clock signal, and the first clock. A signal and the second clock signal, and based on the test mode signal, the first and second clock signals.
The clock signal selecting means for outputting one of the clock signals as the selected clock signal, and the second memory means capable of reading and writing in synchronization with the selected clock signal. The clock signal selection means of the A / D conversion means is readable / writable connected to the digital signal processing means via the digital data bus, and the test mode signal instructs the pass / fail judgment test of the second storage means. Output the first clock signal as the selected clock signal, and otherwise outputs the second clock signal as the selected clock signal, and the digital signal processing means outputs the test mode signal as the selected signal. When instructing the pass / fail judgment test of the second storage means, the storage means test function is used to transmit the data via the digital data bus. By executing writes to the second storage unit Te, performs quality determination test for the second storage means.

According to a second aspect of the present invention, a semiconductor integrated circuit has an analog signal output terminal, a test mode terminal for receiving a test mode signal from the outside, a digital data bus, and a digital signal which is D / A converted into an analog signal. The digital signal processing means includes a D / A conversion means for outputting a signal to the analog signal output terminal and a digital signal processing means for performing various digital signal processing on the digital signal. First to generate a clock signal
Said clock signal generating means, said first clock signal is output to the outside of said digital signal processing means, and said first storage means is further readable and writable in synchronization with said first clock signal. The D / A conversion unit has a second clock signal generation unit for generating a second clock signal, the first clock signal, and the storage unit test function for determining the quality of the first storage unit. Clock signal selecting means for receiving the second clock signal and outputting one of the first and second clock signals as a selected clock signal based on the test mode signal, and synchronizing with the selected clock signal And a readable / writable second storage means, the second storage means being readable / writable connected to the digital signal processing means via the digital data bus. The clock signal selection means of the D / A conversion means outputs the first clock signal as the selected clock signal when the test mode signal instructs a pass / fail judgment test of the second storage means. Otherwise, the second clock signal is output as the selected clock signal, and the digital signal processing means, when the test mode signal indicates a pass / fail judgment test of the second storage means, the storage means By using the test function, reading / writing is performed on the second storage unit via the digital data bus to perform a pass / fail judgment test on the second storage unit.

According to a third aspect of the present invention, a semiconductor integrated circuit has an analog signal input terminal for receiving an externally input analog signal from the outside, an analog signal output terminal, a test mode terminal for receiving a test mode signal from the outside, and a digital signal. A / D for data bus and external input analog signal
A / D / D / A conversion means for converting and outputting a digital signal, D / A converting the digital signal and outputting a D / A converted analog signal to the analog signal output terminal, and the digital signal. Received, to the digital signal,
Digital signal processing means for performing various digital signal processing, the digital signal processing means includes first clock signal generating means for generating a first clock signal, and the first clock signal is the A first storage means that is output to the outside of the digital signal processing means and is readable and writable in synchronization with the first clock signal is further provided, and has a storage means test function for determining the quality of the first storage means. And the A / D / D / A conversion means receives second clock signal generation means for generating a second clock signal, the first clock signal and the second clock signal,
A clock signal selecting unit that outputs one of the first and second clock signals as a selected clock signal based on the test mode signal, and a second memory that can read and write in synchronization with the selected clock signal. Means, the second storage means is connected to the digital signal processing means via the digital data bus so as to be readable and writable, and the clock signal selection means of the A / D / D / A conversion means, The first clock signal is output as the selected clock signal when the test mode signal indicates a pass / fail judgment test of the second storage means, and otherwise the second clock signal is output as the selected clock signal. When the test mode signal indicates a pass / fail judgment test of the second storage means, the digital signal processing means outputs the Using 憶 means test function by executing writes to the second storage unit via said digital data bus, performs quality determination test for the second storage means.

Preferably, as in the semiconductor integrated circuit according to claim 4, the digital signal processing means has a self-diagnosis test function for judging internal performance, and the self-diagnosis test function is the storage means test function. May be included.

Preferably, as in the semiconductor integrated circuit according to the fifth aspect, the digital signal processing means further comprises a pass / fail determination terminal that can be monitored from the outside, and the pass / fail determination result for the second storage means is determined. Information may be output to the quality determination terminal.

Preferably, as in the semiconductor integrated circuit according to the sixth aspect, a first clock input terminal for receiving a first external clock signal from the outside and a second clock for receiving a second external clock signal from the outside. An input terminal is further provided, the first clock signal generating means generates the first clock signal based on the first external clock signal, and the second clock signal generating means causes the second external clock signal. The second clock signal may be generated based on a signal.

A semiconductor integrated circuit according to a seventh aspect of the present invention is an analog signal input terminal for receiving an analog signal from the outside, an analog signal output terminal, a test mode terminal for receiving a test mode signal from the outside, and a digital data bus. And A / D conversion means for A / D converting the analog signal obtained through the analog signal input terminal to output a digital signal, and D / A converting the digital signal for converting the analog signal to the analog signal. The digital signal processing means includes: a D / A conversion means for outputting to an output terminal; and a digital signal processing means for receiving the digital signal and performing various digital signal processing on the digital signal. A first clock signal generating means for generating a clock signal of the digital signal processing means. Further includes a first storage unit that is output to the outside of the storage unit and is readable and writable in synchronization with the first clock signal, and has a storage unit test function for determining pass / fail of the first storage unit. The / D conversion means receives second clock signal generation means for generating a second clock signal, the first clock signal and the second clock signal, and based on the test mode signal, the first and second clock signal generation means. First clock signal selection means for outputting one of the second clock signals as a first selection clock signal, and second storage means capable of reading and writing in synchronization with the first selection clock signal. The second storage means is readable / writable connected to the digital signal processing means via the digital data bus, and the D / A conversion means generates a third clock signal. Receiving a clock signal generating means, said first clock signal and the third clock signal, based on said test mode signal,
Second clock signal selecting means for outputting one of the first and third clock signals as a second selected clock signal, and a third readable / writable synchronous with the second selected clock signal. Storage means, the third storage means is readable / writable connected to the digital signal processing means via the digital data bus, and the third storage means
The first clock signal selection means of the D conversion means outputs the first clock signal to the first clock signal when the test mode signal instructs a pass / fail judgment test of the second storage means.
Of the D / A conversion means, and the second clock signal selection means of the D / A conversion means outputs the second clock signal as the first selection clock signal. The first clock signal is output as the second selected clock signal when the mode signal directs the pass / fail judgment test of the third storage means, and otherwise the third clock signal is output as the second clock signal.
The digital signal processing means outputs the selected clock signal via the digital data bus using the storage means test function when the test mode signal indicates a pass / fail test of the second storage means. By executing reading and writing with respect to the second storage means,
When a pass / fail judgment test is performed on the second storage means, and when the test mode signal instructs a pass / fail judgment test of the third storage means, the storage means test function is used to execute the pass / fail test via the digital data bus. By executing reading and writing to the third storage means, a pass / fail judgment test is performed on the third storage means.

Preferably, as in the semiconductor integrated circuit according to claim 8, the digital signal processing means has a self-diagnosis test function for judging internal performance, and the self-diagnosis test function is the storage means test function. May be included.

Preferably, as in the semiconductor integrated circuit according to claim 9, the digital signal processing means further comprises a pass / fail determination terminal that can be monitored from the outside, and a determination result of a pass / fail determination test for the second storage means. Information or the judgment result information of the quality judgment test for the third storage means may be output to the quality judgment terminal.

Preferably, as in the semiconductor integrated circuit according to claim 10, a first clock input terminal for receiving a first external clock signal from the outside and a second clock for receiving a second external clock signal from the outside. An input terminal and a third clock input terminal for receiving a third external clock signal from the outside are further provided, and the first clock signal generation means is based on the first external clock signal, and the first clock signal is generated. And the second clock signal generation means generates the second clock signal based on the second external clock signal, and the third clock signal generation means based on the third external clock signal. The third clock signal may be generated.

[0030]

In the semiconductor integrated circuit according to the first aspect and the fourth to sixth aspects of the present invention, the A / D conversion is performed when the test mode signal obtained from the outside directs the pass / fail judgment test of the second storage means. The clock signal selecting means of the means outputs the first clock signal as the selected clock signal, and the digital signal processing means uses the storage means testing function provided in itself to output the second clock signal via the digital data bus.
By executing reading and writing with respect to the storage means, the pass / fail judgment test for the second storage means is performed.

Therefore, the test mode signal for instructing the pass / fail judgment test of the second storage means is externally applied without applying any test signal from the outside, and the second mode of the A / D conversion means is supplied. A pass / fail test can be performed on the storage means.

Claims 2 and 4 of the present invention
7. The semiconductor integrated circuit according to claim 6, wherein when a test mode signal obtained from the outside instructs a pass / fail judgment test of the second storage means, the clock signal selection means of the D / A conversion means outputs the first clock signal. The digital signal processing unit outputs the selected clock signal, and the digital signal processing unit uses the storage unit test function provided in itself to read and write the second storage unit via the digital data bus, and thereby the second storage unit is read. Perform a pass / fail test.

Therefore, the test mode signal for instructing the pass / fail judgment test of the second storage means is externally applied without applying any test signal from the outside, and the second D / A conversion means is supplied. A pass / fail test can be performed on the storage means.

In the semiconductor integrated circuit according to any one of claims 3 to 6 of the present invention, when a test mode signal obtained from the outside directs a pass / fail judgment test of the second storage means, A / D / D / A conversion is performed. The clock signal selecting means of the means outputs the first clock signal as the selected clock signal, and the digital signal processing means uses the storage means testing function provided in itself to output the second clock signal via the digital data bus.
By executing reading and writing with respect to the storage means, the pass / fail judgment test for the second storage means is performed.

Therefore, the A / D / D / A converting means can be provided only by externally applying a test mode signal for instructing a pass / fail judgment test of the second storage means, without externally applying a test signal. It is possible to perform a pass / fail test for the second storage means.

In the semiconductor integrated circuit according to any one of claims 7 to 10 of the present invention, when the test mode signal obtained from the outside directs the pass / fail judgment test of the second storage means, the first of the A / D conversion means is used. Of the clock signal selecting means outputs the first clock signal as the first selected clock signal, and the digital signal processing means uses the storage means testing function provided in itself to output the second clock signal via the digital data bus. By executing reading and writing to the storage means, a pass / fail judgment test is performed on the second storage means.

When a test mode signal obtained from the outside directs the quality judgment test of the third storage means, D
The second clock signal selection means of the / A conversion means outputs the first clock signal as a second selection clock signal,
The digital signal processing means performs a pass / fail judgment test on the third storage means by executing reading / writing from / to the third storage means via the digital data bus using the storage means test function provided in itself. Therefore, without applying a test signal from outside,
The quality test of the second storage means of the A / D conversion means can be performed only by externally providing a test mode signal for instructing the quality determination test of the second storage means, and the quality of the third storage means can be determined. The third D / A conversion means can be provided only by externally applying a test mode signal instructing a judgment test.
It is possible to perform a pass / fail test for the storage means.

[0038]

【Example】

<First Embodiment> FIG. 1 is a block diagram showing a structure of a semiconductor integrated circuit according to a first embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit 1 includes an A / D converter 3 and a D / D converter 3.
It is composed of SP2.

The A / D converter 3 takes in an analog signal from the outside through the analog signal input terminal 112 and outputs A / D.
After D conversion, the internal memory 71 is utilized to perform oversampling processing and the like.

The A / D converter 3 executes the above processing in synchronization with the internal clock signal S6 output from the clock signal generation circuit 6. The clock signal generation circuit 6 generates the internal clock signal S6 based on the external clock signal obtained via the external clock input terminal 107.

The internal clock signal S6 of the clock signal generation circuit 6 is input to the clock selector 8. The clock selector 8 takes in the DSP clock signal S5 obtained from the clock signal line 114 together with the internal clock signal S6, and outputs the internal clock signal S6 and the DSP clock signal S.
5, the internal clock signal S6 is normally output to the memory 71 as the selected clock signal S8, and the test mode signal for instructing the test of the memory 71 is received from the test mode terminal 110 via the test mode signal line 10. ,
The DSP clock signal S5 is output to the memory 71 as the selected clock signal S8.

The memory 71 in the A / D converter 3 operates in synchronization with the selected clock signal S8 obtained from the clock selector 8 to perform read and write operations. Further, the memory 71 is connected to the input / output terminal 102, and can perform input / output with a digital signal on the digital data bus 4 via the input / output terminal 102.

On the other hand, the DSP 2 encodes and decodes the digital signal on the digital data bus 4 input / output via the input / output terminal 101 and the digital signal input / output via the external data input / output terminal 105. Various digital signal processing such as processing is performed. At this time, the clock signal generation circuit 5 operates in synchronization with the DSP clock signal S5 which is an internal clock signal. The clock signal generation circuit 5 uses the DSP clock signal S5 based on the external clock signal obtained from the external clock input terminal 106.
To occur.

When the DSP 2 receives a test mode signal instructing a self-diagnosis test from the test mode terminal 110 via the test mode signal line 10, the DSP 2 executes the self-diagnosis test of the internal circuit such as the memory 21. In addition, from the test mode terminal 110 via the test mode signal line 10, A
When receiving the test mode signal for instructing the test of the memory 71 of the / D converter 3, the read / write control signal S9 for controlling the write operation and the read operation of the memory 71 is output to the memory 71 via the memory control signal line 9. , Memory 71
Test the memory against.

The test procedure of this memory is previously written in the program storage memory inside the DSP 2,
The test for the internal memory 21 for self-diagnosis of SP2 is diverted as it is. In addition, 103 is a fail flag terminal for outputting Fail information which is a test result, and 104 is an external address terminal.

FIG. 2 is a flow chart showing the test operation of the semiconductor integrated circuit of the first embodiment.

Then, in step S12, the result of the self-diagnosis test of the DSP 2 is determined. If the result is Fail, Fail information is output to the fail flag terminal 103 in step S15, and the process is terminated. On the other hand, if the result of the self-diagnosis test is Pass, the process proceeds to step S13.

In step S13, a test mode signal for instructing the test of the memory 71 of the A / D converter 3 is externally applied to the DSP 2 and the clock selector 8 of the A / D converter 3 via the test mode terminal 110. Then, the clock selector 8 outputs the DSP clock signal S5 to the memory 71 as the selected clock signal S8. As a result, the memory 71 can perform the read / write operation in synchronization with the DSP clock signal S5 which is the operation clock of the DSP 2.

Under this circumstance, the DSP 2 gives a read or write control signal to the memory 71 via the memory control signal line 9 according to the memory test procedure stored in the internal memory, and the input / output terminal 102 and the digital data bus. The test for the memory 71 of the A / D converter 3 is executed by performing the writing and reading operations of the digital data with respect to the memory 71 via the 4 and the input / output terminal 101.

The memory test of the memory 71 of the A / D converter 3 is the same memory test as the memory test of the internal memory 21 of the DSP 2, and its specific method is known such as pseudo random number generation and data compression. Method, so it is not described here.

Then, in step S14, the result of the memory test is determined, and if the result is Fail, Fail information is output to the fail flag terminal 103 in step S15, and the process ends. On the other hand, the result of the self-diagnosis test is Pas.
If s, the process ends without doing anything.

After the above test is performed, the test result information can be obtained externally by externally monitoring the presence or absence of Fail information from the Fail flag terminal 103.
The state of Fail can be known from the outside as a Fail address and data by the external address terminal 104 and the external data terminal 105. As the output method, a software-like process described in the self-diagnosis program and a hardware-like process for allowing the DSP 2 to output through are considered.

As described above, in the semiconductor integrated circuit of the first embodiment, the test for the memory 71 of the A / D converter 3 is performed by the D test.
Since the test for the memory 21 inside the SP2 is diverted and made executable, it is only necessary to externally give a test mode signal instructing execution of the memory test of the memory 71 of the A / D converter 3, The test can be efficiently performed without preparing a test vector according to the capacity.

<Second Embodiment> FIG. 3 is a block diagram showing a structure of a semiconductor integrated circuit according to a second embodiment of the present invention. As shown in FIG. 3, the semiconductor integrated circuit 1 has a D / A
It is composed of a converter 12 and a DSP 2.

The D / A converter 12 D / A-converts the digital signal obtained from the memory 72, performs analog filtering processing, etc., and then outputs the analog signal to the outside via the analog signal output terminal 113.

The D / A converter 12 executes the above processing in synchronization with the internal clock signal S6 'output from the clock signal generating circuit 6'. Clock signal generating circuit 6'generates internal clock signal S6 'based on the external clock signal obtained through external clock input terminal 107'.

The internal clock signal S6 'of the clock signal generating circuit 6'is input to the clock selector 8'. The clock selector 8'takes in the DSP clock signal S5 obtained from the clock signal line 114 together with the internal clock signal S6 '. Of the internal clock signal S6' and the DSP clock signal S5, the internal clock signal S
6'is output to the memory 72 as the selected clock signal S8 ', and the test mode signal line 1 is output from the test mode terminal 110.
When the test mode signal for instructing the test of the memory 72 is received via 0, the DSP clock signal S5 is output to the memory 72 as the selected clock signal S8 '.

The memory 72 in the D / A converter 12 operates in synchronization with the selected clock signal S8 'obtained from the clock selector 8', and performs read and write operations. The memory 72 is connected to the input / output terminal 102 ', and the digital data bus 4 is connected via the input / output terminal 102'.
Input and output can be performed with the above digital signal.

On the other hand, the DSP 2 encodes and decodes a digital signal on the digital data bus 4 input / output via the input / output terminal 101 and a digital signal input / output via the external data input / output terminal 105. Various digital signal processing such as processing is performed. At this time, the clock signal generation circuit 5 operates in synchronization with the DSP clock signal S5 which is an internal clock signal. The clock signal generation circuit 5 uses the DSP clock signal S5 based on the external clock signal obtained from the external clock input terminal 106.
To occur.

When receiving the test mode signal instructing the self-diagnosis test from the test mode terminal 110 via the test mode signal line 10, the DSP 2 executes the self-diagnosis test of the internal circuit such as the memory 21. In addition, D from the test mode terminal 110 via the test mode signal line 10
When receiving the test mode signal instructing the test of the memory 72 of the A / A converter 12, the memory control signal line 9
The read / write control signal S9 for controlling the write operation and read operation of the memory 72 is output to the memory 72, and the memory 7
Test memory for 2.

The test procedure of this memory is written in advance in the program storage memory inside the DSP 2,
The test for the internal memory 21 for self-diagnosis of SP2 is diverted as it is. In addition, 103 is a fail flag terminal for outputting Fail information which is a test result, and 104 is an external address terminal.

FIG. 4 is a flow chart showing the test operation of the semiconductor integrated circuit of the second embodiment.

Referring to FIG. 4, first, step S21.
Then, from the outside through the test mode terminal 110, the DSP2
The test mode signal that directs the self-diagnosis test of the DSP
2, the self-diagnosis of DSP2 is made,
The internal circuit of the DSP 2 such as the memory 21 is tested. The program showing the self-diagnosis procedure is already written in the DSP 2 as in the first embodiment.

Then, in step S22, the result of the self-diagnosis test of the DSP 2 is determined. If the result is Fail, Fail information is output to the fail flag terminal 103 in step S25, and the process ends. On the other hand, if the result of the self-diagnosis test is Pass, the process proceeds to step S23.

In step S23, a test mode signal for instructing the test of the memory 72 of the D / A converter 12 is externally supplied via the test mode terminal 110 to the DSP 2 and the D / A.
It is given to the clock selector 8'of the converter 12. Then,
The clock selector 8 ′ outputs the DSP clock signal S5 to the memory 72 as the selected clock signal S8 ′. As a result, the memory 72 is D, which is the operation clock of the DSP 2.
A read / write operation can be performed in synchronization with the SP clock signal S5.

Under this circumstance, the DSP 2 gives a read or write control signal to the memory 72 via the memory control signal line 9 in accordance with the memory test procedure stored in the internal memory, and the input / output terminal 102 'and the digital data are supplied. A test of the D / A converter 12 with respect to the memory 72 is executed by performing digital data writing and reading operations with respect to the memory 72 via the bus 4 and the input / output terminal 101.

The memory test for the memory 72 of the D / A converter 12 is the same as the memory test for the internal memory 21 of the DSP 2 as in the first embodiment.

Then, in step S24, the result of the memory test is determined. If the result is Fail, Fail information is output to the fail flag terminal 103 in step S25, and the process ends. On the other hand, the result of the self-diagnosis test is Pas.
If s, the process ends without doing anything.

After performing the above-mentioned test, by externally monitoring the presence or absence of Fail information from the Fail flag terminal 103, the test result information can be obtained externally.
Also, as in the first embodiment, the state of Fail is determined by the external address terminal 104 and the external data terminal 105.
It can be known from the outside as an address and data.

As described above, in the semiconductor integrated circuit of the second embodiment, the test for the memory 72 of the D / A converter 12 can be executed by diverting the test for the memory 21 inside the DSP 2, so that it can be executed from the outside. A test mode signal for instructing execution of a memory test of the memory 72 of the D / A converter 12 need only be given, and it is not necessary to prepare a test vector according to the capacity of the memory 72, and the test can be performed efficiently. You can

<Third Embodiment> FIG. 5 is a block diagram showing a structure of a semiconductor integrated circuit according to a third embodiment of the present invention. As shown in FIG. 5, the semiconductor integrated circuit 1 has an A / D
It is composed of a converter 3, a D / A converter 12 and a DSP 2.

The A / D converter 3 takes in an analog signal from the outside through the analog signal input terminal 112, and
After D conversion, the internal memory 71 is utilized to perform oversampling processing and the like.

The A / D converter 3 executes the above processing in synchronization with the internal clock signal S6 output from the clock signal generation circuit 6. The clock signal generation circuit 6 generates the internal clock signal S6 based on the external clock signal obtained via the external clock input terminal 107.

The internal clock signal S6 of the clock signal generation circuit 6 is input to the clock selector 8. The clock selector 8 takes in the DSP clock signal S5 obtained from the clock signal line 114 together with the internal clock signal S6, and outputs the internal clock signal S6 and the DSP clock signal S.
5, the internal clock signal S6 is normally output to the memory 71 as the selected clock signal S8, and the test mode signal for instructing the test of the memory 71 is received from the test mode terminal 110 via the test mode signal line 10. ,
The DSP clock signal S5 is output to the memory 71 as the selected clock signal S8.

The memory 71 in the A / D converter 3 operates in synchronization with the selected clock signal S8 obtained from the clock selector 8 to perform read and write operations. Further, the memory 71 is connected to the input / output terminal 102, and can perform input / output with a digital signal on the digital data bus 4 via the input / output terminal 102.

Further, the D / A converter 12 D / A converts the digital signal obtained from the memory 72, performs analog filtering processing, etc., and then outputs the analog signal output terminal 1
An analog signal is output to the outside via 13.

The D / A converter 12 executes the above processing in synchronization with the internal clock signal S6 'output from the clock signal generating circuit 6'. Clock signal generating circuit 6'generates internal clock signal S6 'based on the external clock signal obtained through external clock input terminal 107'.

The internal clock signal S6 'of the clock signal generating circuit 6'is input to the clock selector 8'. The clock selector 8'takes in the DSP clock signal S5 obtained from the clock signal line 114 together with the internal clock signal S6 '. Of the internal clock signal S6' and the DSP clock signal S5, the internal clock signal S
6'is output to the memory 72 as the selected clock signal S8 ', and the test mode signal line 1 is output from the test mode terminal 110.
When the test mode signal for instructing the test of the memory 72 is received via 0, the DSP clock signal S5 is output to the memory 72 as the selected clock signal S8 '.

The memory 72 in the D / A converter 12 operates in synchronization with the selected clock signal S8 'obtained from the clock selector 8', and performs read and write operations. The memory 72 is connected to the input / output terminal 102 ', and the digital data bus 4 is connected via the input / output terminal 102'.
Input and output can be performed with the above digital signal.

On the other hand, the DSP 2 encodes and decodes a digital signal on the digital data bus 4 input / output via the input / output terminal 101 and a digital signal input / output via the external data input / output terminal 105. Various digital signal processing such as processing is performed. At this time, the clock signal generation circuit 5 operates in synchronization with the DSP clock signal S5 which is an internal clock signal. The clock signal generation circuit 5 uses the DSP clock signal S5 based on the external clock signal obtained from the external clock input terminal 106.
To occur.

When the DSP 2 receives the test mode signal instructing the self-diagnosis test from the test mode terminal 110 via the test mode signal line 10, the DSP 2 executes the self-diagnosis test of the internal circuit such as the memory 21.

Further, the memory 7 of the A / D converter 3 is connected from the test mode terminal 110 via the test mode signal line 10.
When the test mode signal for instructing the test of No. 1 is received, the read / write control signal S9 for controlling the write operation and the read operation of the memory 71 is output to the memory 71 through the memory control signal line 9, and the memory test for the memory 71 is performed. I do. Then, the memory 7 of the D / A converter 12 is passed from the test mode terminal 110 via the test mode signal line 10.
When the test mode signal instructing the test of No. 2 is received, the read / write control signal S9 for controlling the write operation and the read operation of the memory 72 is output to the memory 72 via the memory control signal line 9, and the memory test for the memory 72 is performed. I do.

The memory test procedure for the A / D converter 3 and the D / A converter 12 is written in advance in the program storage memory inside the DSP2.
The test for the internal memory 21 for self-diagnosis is diverted as it is. In addition, 103 is a test result F
Fail flag terminal for outputting ail information, 10
Reference numeral 4 is an external address terminal.

FIG. 6 is a flow chart showing the test operation of the semiconductor integrated circuit of the third embodiment.

Referring to FIG. 6, first, step S31.
Then, from the outside through the test mode terminal 110, the DSP2
The test mode signal that directs the self-diagnosis test of the DSP
2, the self-diagnosis of DSP2 is made,
The internal circuit of the DSP 2 such as the memory 21 is tested. The program showing the self-diagnosis procedure is already written in the DSP 2 as in the first and second embodiments.

Then, in step S32, the result of the self-diagnosis test of the DSP 2 is determined. If the result is Fail, Fail information is output to the fail flag terminal 103 in step S37, and the process is terminated. On the other hand, if the result of the self-diagnosis test is Pass, the process proceeds to step S33.

In step S33, a test mode signal for instructing the test of the memory 71 of the A / D converter 3 is externally applied to the DSP 2 and the clock selector 8 of the A / D converter 3 via the test mode terminal 110. Then, the clock selector 8 outputs the DSP clock signal S5 to the memory 71 as the selected clock signal S8. As a result, the memory 71 can perform the read / write operation in synchronization with the DSP clock signal S5 which is the operation clock of the DSP 2.

Under this circumstance, the DSP 2 gives a read or write control signal to the memory 71 through the memory control signal line 9 in accordance with the memory test procedure stored in the internal memory, and the input / output terminal 102 and the digital data bus. The test for the memory 71 of the A / D converter 3 is executed by performing the writing and reading operations of the digital data with respect to the memory 71 via the 4 and the input / output terminal 101.

The memory test for the memory 71 of the A / D converter 3 is the same as the memory test for the internal memory 21 of the DSP 2 as in the first and second embodiments.

Then, in step S34, the result of the memory test is determined, and if the result is Fail, Fail information is output to the fail flag terminal 103 in step S37, and the process ends. On the other hand, the result of the self-diagnosis test is Pas.
If s, the process proceeds to step S35.

In step S35, a test mode signal for instructing a test of the memory 72 of the D / A converter 12 is externally supplied via the test mode terminal 110 to the DSP 2 and the D / A.
It is given to the clock selector 8'of the converter 12. Then,
The clock selector 8 ′ outputs the DSP clock signal S5 to the memory 72 as the selected clock signal S8 ′. As a result, the memory 72 is D, which is the operation clock of the DSP 2.
A read / write operation can be performed in synchronization with the SP clock signal S5.

Under this circumstance, the DSP 2 gives a read or write control signal to the memory 72 via the memory control signal line 9 according to the memory test procedure stored in the internal memory, and the input / output terminal 102 'and the digital data are supplied. A test of the D / A converter 12 with respect to the memory 72 is executed by performing digital data writing and reading operations with respect to the memory 72 via the bus 4 and the input / output terminal 101.

The memory test for the memory 72 of the D / A converter 12 is performed by the DSP 2 as in the first and second embodiments.
The memory test has the same contents as the memory test for the internal memory 21 of the.

Then, in step S36, the result of the memory test is determined, and if the result is Fail, Fail information is output to the fail flag terminal 103 in step S37, and the process ends. On the other hand, the result of the self-diagnosis test is Pas.
If s, the process ends without doing anything.

After the above-mentioned test, the test result information can be obtained externally by externally monitoring the presence or absence of Fail information from the Fail flag terminal 103.
Further, as in the first and second embodiments, the state of Fail can be known from the outside as a Fail address and data by the external address terminal 104 and the external data terminal 105.

As described above, the semiconductor integrated circuit of the third embodiment has the memory 71 of the A / D converter 3 and the D / A converter 1.
Since the test for the memory 72 of No. 2 can be executed by diverting the test for the memory 21 inside the DSP 2,
From the outside, the memory 71 of the A / D converter 3 or the D / A
All that is required is to provide a test mode signal instructing execution of a memory test of the memory 72 of the converter 12.
It is not necessary to prepare a test vector according to the capacity of
The test can be performed efficiently.

<Fourth Embodiment> FIG. 7 is a block diagram showing a structure of a semiconductor integrated circuit according to a fourth embodiment of the present invention. As shown in FIG. 7, the semiconductor integrated circuit 1 has an A / D
It is composed of an & D / A converter 13 and a DSP 2.

The A / D & D / A converter 13 fetches an analog signal from the outside through the analog signal input terminal 112, performs A / D conversion, and then utilizes the internal memory 73 to perform oversampling processing and the like. In addition, A / D &
The D / A converter 13 D / A converts the digital signal obtained from the memory 73 or the like to perform analog filtering processing, and then outputs the analog signal to the outside via the analog signal output terminal 113.

The A / D & D / A converter 13 executes the above processing in synchronization with the internal clock signal S6 output from the clock signal generation circuit 6. The clock signal generation circuit 6 generates the internal clock signal S6 based on the external clock signal obtained via the external clock input terminal 107.

The internal clock signal S6 of the clock signal generation circuit 6 is input to the clock selector 8. The clock selector 8 takes in the DSP clock signal S5 obtained via the clock signal line 114 together with the internal clock signal S6, and normally selects the internal clock signal S6 from the internal clock signal S6 and the DSP clock signal S5. When it is output to the memory 73 as S8 and the test mode signal for instructing the test of the memory 73 is received from the test mode terminal 110 via the test mode signal line 10, the DSP clock signal S5 is output to the memory 73 as the selected clock signal S8. .

Memory 73 in A / D & D / A converter 13
Is the selected clock signal S obtained from the clock selector 8.
It operates in synchronism with 8 to perform read and write operations. The memory 73 is connected to the input / output terminal 102, and the digital data bus 4 is connected via the input / output terminal 102.
Input and output can be performed with the above digital signal.

On the other hand, the DSP 2 encodes and decodes a digital signal on the digital data bus 4 input / output via the input / output terminal 101 and a digital signal input / output via the external data input / output terminal 105. Various digital signal processing such as processing is performed. At this time, the clock signal generation circuit 5 operates in synchronization with the DSP clock signal S5 which is an internal clock signal. The clock signal generation circuit 5 uses the DSP clock signal S5 based on the external clock signal obtained from the external clock input terminal 106.
To occur.

When receiving the test mode signal instructing the self-diagnosis test from the test mode terminal 110 through the test mode signal line 10, the DSP 2 executes the self-diagnosis test of the internal circuit such as the memory 21.

Further, the A / D & D / A converter 13 is connected from the test mode terminal 110 via the test mode signal line 10.
When a test mode signal for instructing a test of the memory 73 is received, a read / write control signal S9 for controlling a write operation and a read operation of the memory 73 is output to the memory 73 via the memory control signal line 9, and the memory 73 Test.

The memory test procedure for the A / D & D / A converter 13 is written in advance in the program storage memory inside the DSP 2, and the test for the internal memory 21 for self-diagnosis of the DSP 2 is used as it is. . In addition, 103 is a fail flag terminal for outputting Fail information which is a test result, and 104 is an external address terminal.

FIG. 8 is a flow chart showing the test operation of the semiconductor integrated circuit of the fourth embodiment.

Referring to FIG. 8, first, step S41.
Then, from the outside through the test mode terminal 110, the DSP2
The test mode signal that directs the self-diagnosis test of the DSP
2, the self-diagnosis of DSP2 is made,
The internal circuit of the DSP 2 such as the memory 21 is tested. The program showing the self-diagnosis procedure is already written in the DSP 2 as in the first to third embodiments.

Then, in step S42, the result of the self-diagnosis test of the DSP 2 is determined, and if the result is Fail, Fail information is output to the fail flag terminal 103 in step S45, and the process ends. On the other hand, if the result of the self-diagnosis test is Pass, the process proceeds to step S43.

In step S43, the test mode signal for instructing the test of the memory 73 of the A / D & D / A converter 13 is externally supplied via the test mode terminal 110 to the DSP 2 and the clock selector 8 of the A / D & D / A converter 13. Give to. Then, the clock selector 8 outputs the DSP clock signal S5 to the memory 73 as the selected clock signal S8. As a result, the memory 73 can perform the read / write operation in synchronization with the DSP clock signal S5 which is the operation clock of the DSP2.

Under this circumstance, the DSP 2 gives a read or write control signal to the memory 73 via the memory control signal line 9 in accordance with the memory test procedure stored in the internal memory, and the input / output terminal 102 and the digital data bus. The test of the memory 73 of the A / D & D / A converter 13 is executed by performing the writing and reading operations of the digital data with respect to the memory 73 via the 4 and the input / output terminal 101.

The memory test for the memory 73 of the A / D & D / A converter 13 is performed by the DS test as in the first to third embodiments.
This is the same memory test as the memory test for the internal memory 21 of P2.

Then, in step S44, the result of the memory test is determined. If the result is Fail, Fail information is output to the fail flag terminal 103 in step S45, and the process ends. On the other hand, the result of the self-diagnosis test is Pas.
If s, the process ends without doing anything.

After the above test is performed, it is possible to obtain test result information externally by externally monitoring the presence or absence of Fail information from the Fail flag terminal 103.
As in the first to third embodiments, the state of Fail is F by the external address terminal 104 and the external data terminal 105.
It can be known from the outside as an aile address and data.

As described above, in the semiconductor integrated circuit of the fourth embodiment, the test for the memory 73 of the A / D & D / A converter 13 can be executed by diverting the test for the memory 21 inside the DSP 2. From A / D & D /
All that is required is to add a test mode signal instructing execution of the memory test of the memory 73 of the A converter 13.
The test can be efficiently performed without the need to prepare a test vector corresponding to the capacity of 3.

<Others> It goes without saying that the memories 71 to 73 described in the first to fourth embodiments are not limited to RAM, ROM and the like. If the memories 71 to 73 are ROMs, the DSP clock signal S5 from the DSP2 causes
It is also possible to perform the test by incrementing the address of the ROM by 1 and sequentially reading the stored data to the DSP 2 and compressing all the data read by the DSP 2.

[0116]

As described above, in the semiconductor integrated circuit according to the first aspect and the fourth to sixth aspects of the present invention, the test mode signal obtained from the outside is used for the pass / fail judgment test of the second storage means. When instructing, the clock signal selection means of the A / D conversion means outputs the first clock signal as the selected clock signal, and the digital signal processing means uses the storage means test function provided in itself to output the digital data bus. By executing reading and writing with respect to the second storage means via the, the pass / fail judgment test for the second storage means is performed.

As a result, a test mode signal for instructing a pass / fail judgment test of the second storage means is externally applied without externally applying a test signal.
Since the pass / fail test can be performed on the second storage unit, the pass / fail test on the second storage unit of the A / D conversion unit can be efficiently performed.

Claims 2 and 4 of the present invention
7. The semiconductor integrated circuit according to claim 6, wherein when a test mode signal obtained from the outside instructs a pass / fail judgment test of the second storage means, the clock signal selection means of the D / A conversion means outputs the first clock signal. The digital signal processing unit outputs the selected clock signal, and the digital signal processing unit uses the storage unit test function provided in itself to read and write the second storage unit via the digital data bus, and thereby the second storage unit is read. Perform a pass / fail test.

As a result, a test mode signal for instructing a pass / fail judgment test of the second storage means is externally applied without externally applying a test signal.
Since the pass / fail test for the second storage means can be performed, the pass / fail test for the second storage means of the D / A conversion means can be efficiently performed.

In the semiconductor integrated circuit according to any one of claims 3 to 6 of the present invention, when a test mode signal obtained from the outside directs a pass / fail test of the second storage means, A / D / D / A conversion is performed. The clock signal selecting means of the means outputs the first clock signal as the selected clock signal, and the digital signal processing means uses the storage means testing function provided in itself to output the second clock signal via the digital data bus.
By executing reading and writing with respect to the storage means, the pass / fail judgment test for the second storage means is performed.

As a result, a test mode signal for instructing the pass / fail judgment test of the second storage means is externally applied without externally applying a test signal.
Since the pass / fail test can be performed on the second storage unit, the pass / fail test on the second storage unit of the A / D / D / A conversion unit can be efficiently performed.

In the semiconductor integrated circuit according to any one of claims 7 to 10 of the present invention, when the test mode signal obtained from the outside instructs the pass / fail judgment test of the second storage means, the first of the A / D conversion means is used. Of the clock signal selecting means outputs the first clock signal as the first selected clock signal, and the digital signal processing means uses the storage means testing function provided in itself to output the second clock signal via the digital data bus. By executing reading and writing to the storage means, a pass / fail judgment test is performed on the second storage means.

Further, when the test mode signal obtained from the outside directs the pass / fail judgment test of the third storage means, D
The second clock signal selection means of the / A conversion means outputs the first clock signal as a second selection clock signal,
The digital signal processing means performs a pass / fail judgment test on the third storage means by executing reading / writing from / to the third storage means via the digital data bus using the storage means test function provided in itself.

As a result, a test mode signal for instructing the pass / fail judgment test of the second storage means is externally applied without externally applying a test signal.
It is possible to perform a pass / fail test for the second storage means,
Since the pass / fail test for the third storage means can be performed only by externally applying the test mode signal for instructing the pass / fail judgment test of the third storage means, the second storage means of the A / D conversion means and The pass / fail test for each of the third storage units of the D / A conversion unit can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

2 is a flowchart showing a test operation of the semiconductor integrated circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

4 is a flowchart showing a test operation of the semiconductor integrated circuit of FIG.

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

6 is a flowchart showing a test operation of the semiconductor integrated circuit of FIG.

FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

8 is a flowchart showing a test operation of the semiconductor integrated circuit of FIG.

FIG. 9 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 2 DSP 3 A / D converter 5 Clock signal generation circuit 6 Clock signal generation circuit 8 Clock selector 12 D / A converter 13 A / D & D / A converter 21 Memory (in DSP2) 71 Memory (A / D converter 3) 72 memory (in the D / A converter 12) 73 memory (in the A / D & D / A converter 13)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/06 H03M 1/10 CD

Claims (10)

[Claims] 1. An analog signal input terminal for receiving an analog signal from the outside, a test mode terminal for receiving a test mode signal from the outside, a digital data bus, and an analog signal input via the analog signal input terminal A / D that D-converts and outputs a digital signal
A semiconductor integrated circuit comprising: a conversion unit; and a digital signal processing unit that receives the digital signal and performs various kinds of digital signal processing on the digital signal, wherein the digital signal processing unit is a first clock signal. A first clock signal generating means for generating the first clock signal, the first clock signal being output to the outside of the digital signal processing means, and being readable and writable in synchronization with the first clock signal.
Storage means for determining whether the first storage means is good or bad, and the A / D conversion means includes a second clock signal generation means for generating a second clock signal. A clock signal selecting means for receiving the first clock signal and the second clock signal and outputting one of the first and second clock signals as a selected clock signal based on the test mode signal. And a second storage unit capable of reading and writing in synchronization with the selected clock signal, the second storage unit being readable and writable connected to the digital signal processing unit via the digital data bus, The clock signal selection means of the A / D conversion means, when the test mode signal indicates a pass / fail judgment test of the second storage means, the first clock Signal is output as the selected clock signal, otherwise the second clock signal is output as the selected clock signal, and the digital signal processing means determines whether the test mode signal is good or bad in the second storage means. When instructing the test,
A semiconductor integrated circuit characterized by performing a pass / fail judgment test on the second storage means by performing reading / writing from / to the second storage means via the digital data bus using the storage means test function. . 2. An analog signal output terminal, a test mode terminal that receives a test mode signal from the outside, a digital data bus, and a D / A that converts the digital signal to D / A and outputs the analog signal to the analog signal output terminal. A semiconductor integrated circuit comprising: an A conversion means; and a digital signal processing means for performing various digital signal processing on the digital signal, wherein the digital signal processing means generates a first clock signal. First clock signal is output to the outside of the digital signal processing means, and the first clock signal is readable and writable in synchronization with the first clock signal.
Storage means for determining whether the first storage means is good or bad, and the D / A conversion means is a second clock signal generation means for generating a second clock signal. A clock signal selecting means for receiving the first clock signal and the second clock signal and outputting one of the first and second clock signals as a selected clock signal based on the test mode signal. And a second storage unit capable of reading and writing in synchronization with the selected clock signal, the second storage unit being readable and writable connected to the digital signal processing unit via the digital data bus, The clock signal selection means of the D / A conversion means, when the test mode signal instructs a pass / fail judgment test of the second storage means, the first clock Signal is output as the selected clock signal, otherwise the second clock signal is output as the selected clock signal, and the digital signal processing means determines whether the test mode signal is good or bad in the second storage means. When instructing the test,
A semiconductor integrated circuit characterized by performing a pass / fail judgment test on the second storage means by performing reading / writing from / to the second storage means via the digital data bus using the storage means test function. . 3. An analog signal input terminal for receiving an external input analog signal from the outside, an analog signal output terminal, a test mode terminal for receiving a test mode signal from the outside, a digital data bus, and an external input analog signal A / D / D / A conversion means for D-converting and outputting a digital signal, D / A converting the digital signal and outputting a D / A-converted analog signal to the analog signal output terminal, and the digital signal. And a digital signal processing means for performing various digital signal processing on the digital signal, wherein the digital signal processing means comprises a first clock for generating a first clock signal. Signal generating means, the first clock signal is also output to the outside of the digital signal processing means, the first clock signal The first that can be read and written in synchronization with the No. 1
Storage means for determining whether the first storage means is good or bad, and the A / D / D / A conversion means has a second clock for generating a second clock signal. A signal generating means, receiving the first clock signal and the second clock signal, and outputting one of the first and second clock signals as a selected clock signal based on the test mode signal A clock signal selection unit and a second storage unit capable of reading and writing in synchronization with the selected clock signal are provided, and the second storage unit is readable and writable to the digital signal processing unit via the digital data bus. When the test mode signal is connected, the clock signal selection means of the A / D / D / A conversion means outputs the test result of the second storage means. Outputting a first clock signal as the selected clock signal, and otherwise outputting the second clock signal as the selected clock signal, wherein the digital signal processing means causes the test mode signal to be the second storage When instructing the quality judgment test of the means,
A semiconductor integrated circuit characterized by performing a pass / fail judgment test on the second storage means by performing reading / writing from / to the second storage means via the digital data bus using the storage means test function. . 4. The digital signal processing means has a self-diagnosis test function for judging internal performance, and the self-diagnosis test function includes the storage means test function. The semiconductor integrated circuit according to item. 5. The digital signal processing means further comprises a quality determination terminal that can be monitored from the outside, and outputs determination result information of a quality determination test to the second storage means to the quality determination terminal. Semiconductor integrated circuit. 6. A first clock input terminal for receiving a first external clock signal from the outside, and a second clock input terminal for receiving a second external clock signal from the outside, the first clock signal The generating means generates the first clock signal based on the first external clock signal, and the second clock signal generating means generates the second clock signal based on the second external clock signal. Item 5. The semiconductor integrated circuit according to item 5. 7. An analog signal input terminal for receiving an analog signal from the outside, an analog signal output terminal, a test mode terminal for receiving a test mode signal from the outside, a digital data bus, and the analog signal input terminal. A / D for A / D converting the analog signal and outputting a digital signal
Conversion means; D / A conversion means for D / A converting the digital signal to output an analog signal to the analog signal output terminal; and receiving the digital signal, performing various digital signal processing on the digital signal. And a digital signal processing means for performing the digital signal processing means, wherein the digital signal processing means includes a first clock signal generating means for generating a first clock signal, and the first clock signal is the digital signal. A first readable / writable first signal that is output to the outside of the signal processing means and is synchronized with the first clock signal.
Storage means for determining whether the first storage means is good or bad, and the A / D conversion means includes a second clock signal generation means for generating a second clock signal. Receiving the first clock signal and the second clock signal and outputting one of the first and second clock signals as a first selected clock signal based on the test mode signal, One clock signal selection means and a second storage means capable of reading and writing in synchronization with the first selection clock signal, wherein the second storage means is readable and writable via the digital data bus. The D / A conversion means is connected to digital signal processing means, and the D / A conversion means generates third clock signal, third clock signal generation means, the first clock signal and the third clock signal. A second clock signal selecting means for receiving a clock signal and outputting one of the first and third clock signals as a second selected clock signal based on the test mode signal; And a third storage means capable of reading and writing in synchronization with the selected clock signal, the third storage means being readable and writable connected to the digital signal processing means via the digital data bus. The first clock signal selection means of the D conversion means outputs the first clock signal as the first selected clock signal when the test mode signal instructs a pass / fail judgment test of the second storage means. In the other cases, the second clock signal is output as the first selected clock signal, and the second clock signal selection means of the D / A conversion means is The test mode signal outputs the first clock signal as the second selected clock signal when the quality judgment test of the third storage means is instructed. Otherwise, the third clock signal is output. Outputting as a second selection clock signal, the digital signal processing means, when the test mode signal indicates a pass / fail judgment test of the second storage means,
By using the storage unit test function, a read / write operation is performed on the second storage unit via the digital data bus to perform a pass / fail judgment test on the second storage unit, and the test mode signal indicates No. 3 storage means is instructed, the storage means test function is used to read / write from / to the third storage means via the digital data bus to thereby read / write to the third storage means. A semiconductor integrated circuit characterized by performing a pass / fail judgment test. 8. The semiconductor integrated circuit according to claim 7, wherein the digital signal processing means has a self-diagnosis test function for judging internal performance, and the self-diagnosis test function includes the storage means test function. 9. The digital signal processing means further comprises a pass / fail judgment terminal that can be monitored from the outside, and the judgment result information of the pass / fail judgment test for the second storage means or the pass / fail judgment test for the third storage means. The semiconductor integrated circuit according to claim 8, wherein the determination result information is output to the quality determination terminal. 10. A first clock input terminal for receiving a first external clock signal from the outside, a second clock input terminal for receiving a second external clock signal from the outside, and a third external clock signal from the outside. And a third clock input terminal for receiving the first clock signal, wherein the first clock signal generating means generates the first clock signal based on the first external clock signal,
The second clock signal generating means generates the second clock signal based on the second external clock signal, and the third clock signal generating means performs the third clock signal based on the third external clock signal. 10. The semiconductor integrated circuit according to claim 9, which generates a clock signal.