JPH0786330A - Semiconductor device and semiconductor device mounting method - Google Patents

Semiconductor device and semiconductor device mounting method

Info

Publication number
JPH0786330A
JPH0786330A JP5250032A JP25003293A JPH0786330A JP H0786330 A JPH0786330 A JP H0786330A JP 5250032 A JP5250032 A JP 5250032A JP 25003293 A JP25003293 A JP 25003293A JP H0786330 A JPH0786330 A JP H0786330A
Authority
JP
Japan
Prior art keywords
semiconductor device
substrate
flip chip
bonding
mounting surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5250032A
Other languages
Japanese (ja)
Other versions
JP3334816B2 (en
Inventor
Hiroki Koshiro
宏樹 小城
Masayoshi Iida
眞義 飯田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25003293A priority Critical patent/JP3334816B2/en
Publication of JPH0786330A publication Critical patent/JPH0786330A/en
Application granted granted Critical
Publication of JP3334816B2 publication Critical patent/JP3334816B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】本発明は、実装面に複数の第1の接合部がそれ
ぞれ設けられ、各第1の接合部を、それぞれ基板の所定
面に設けられた対応する第2の接合部に所定の接合手段
を用いて接合することにより基板に実装する半導体装置
の信頼性を向上させようとするものである。 【構成】半導体チツプの実装面の全面に渡つて分布する
ように配置された第1の接合部を設け、当該各第1の接
合部を基板の対応する第2の接合部に接合するようにし
たことにより、温度変化等に起因する当該半導体チツプ
の歪みを抑制することができ、かくして信頼性を向上さ
せ得る半導体装置及び半導体装置の実装方法を実現でき
る。
(57) [Abstract] An object of the present invention is to provide a plurality of first joint portions on a mounting surface, and to arrange each of the first joint portions on a predetermined surface of a substrate. The reliability of the semiconductor device mounted on the substrate is improved by bonding the bonding portion with a predetermined bonding means. A first bonding portion arranged so as to be distributed over the entire mounting surface of a semiconductor chip is provided, and each first bonding portion is bonded to a corresponding second bonding portion of a substrate. By doing so, it is possible to realize the semiconductor device and the mounting method of the semiconductor device, which can suppress the distortion of the semiconductor chip due to the temperature change or the like and thus improve the reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及び半導体装
置の実装方法に関し、例えばフリツプチツプ型のICチツ
プ(以下これをICフリツプチツプと呼ぶ)及び当該ICフ
リツプチツプの実装方法に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for mounting the semiconductor device, and is suitable for application to, for example, a flip-chip type IC chip (hereinafter referred to as an IC flip-chip) and a mounting method for the IC flip-chip. is there.

【0002】[0002]

【従来の技術】従来図5及び図6に示すように、基板1
にICフリツプチツプ2を実装してなるICフリツプチツプ
実装基板3では、ICフリツプチツプ2の下側面(以下こ
れを実装面と呼ぶ)に複数設けられた各接合部2Aと、
これと対応するように基板1の所定面にそれぞれ設けら
れた接合部1Aとを例えばバンプ等でなる接合材4を用
いて接合することにより形成されている。この場合当該
ICフリツプチツプ2においては、図7に示すように、接
合部2Aが実装面の各辺に沿つてそれぞれ並ぶように設
けられており、従つて実装面の周辺部において基板1と
接合される。
2. Description of the Related Art As shown in FIG. 5 and FIG.
In an IC flip chip mounting substrate 3 in which the IC flip chip 2 is mounted on each of the IC flip chips 2, a plurality of joint portions 2A provided on the lower surface of the IC flip chip 2 (hereinafter referred to as the mounting surface),
Corresponding to this, it is formed by joining the joining portions 1A respectively provided on the predetermined surfaces of the substrate 1 with the joining material 4 such as bumps. In this case
In the IC flip chip 2, as shown in FIG. 7, the joint portions 2A are provided so as to be lined up along each side of the mounting surface, and accordingly, are joined to the substrate 1 at the peripheral portion of the mounting surface.

【0003】[0003]

【発明が解決しようとする課題】ところがこの種のICフ
リツプチツプ実装基板3においては、ICフリツプチツプ
2が接合材4を介して直接基板1上に接合されているた
めに、当該ICフリツプチツプ2と基板1との熱膨張率の
違いから温度変化等によつてICフリツプチツプ2、基板
1及び接合材4に応力や歪みが生じることがあり、この
結果ICフリツプチツプ2や接合材4が破壊することがあ
つた。この場合温度変化によつて任意の第1及び第2の
接合材4間に生じるICフリツプチツプ2の歪みの大きさ
は、当該第1の接合部材4が取り付けられた位置から当
該第2の接合材4が取り付けられた位置までの距離(以
下これを接合材間距離と呼ぶ)が長くなるほど大きくな
る。
However, in this type of IC flip chip mounting substrate 3, since the IC flip chip 2 is directly bonded onto the substrate 1 via the bonding material 4, the IC flip chip 2 and the substrate 1 are bonded together. Due to the difference in the thermal expansion coefficient between the IC chip and the IC chip, stress or strain may occur in the IC flip chip 2, the substrate 1 and the bonding material 4, and as a result, the IC flip chip 2 and the bonding material 4 may be destroyed. . In this case, the magnitude of the distortion of the IC flip chip 2 caused between the arbitrary first and second bonding materials 4 due to the temperature change depends on the position of the first bonding member 4 from the position where the second bonding material 4 is attached. The longer the distance to the position where 4 is attached (hereinafter referred to as the inter-bonding material distance), the larger the distance.

【0004】従つてこの種のICフリツプチツプ2におい
ては、チツプ2が大きくなるほど各接合材間距離が大き
くなるためにICフリツプチツプ2に生じる歪みも大きく
なり、この結果チツプ2及び接合材4が壊れ易くなるこ
とにより温度変化に対する当該ICフリツプチツプ2の信
頼性が低下する問題があつた。
Therefore, in the IC flip chip 2 of this type, the larger the chip 2, the larger the distance between the respective bonding materials, so that the distortion generated in the IC flip chip 2 also increases, and as a result, the chip 2 and the bonding material 4 are easily broken. Therefore, there is a problem that the reliability of the IC flip chip 2 with respect to the temperature change is lowered.

【0005】本発明は以上の点を考慮してなされたもの
で、信頼性を向上させ得る半導体装置及びその半導体装
置の実装方法を提案しようとするものである。
The present invention has been made in consideration of the above points, and is intended to propose a semiconductor device capable of improving reliability and a method of mounting the semiconductor device.

【0006】[0006]

【課題を解決するための手段】かかる問題を解決するた
め本発明においては、実装面に複数の第1の接合部11
がそれぞれ設けられ、各第1の接合部11を、それぞれ
基板12の所定面に設けられた対応する第2の接合部1
3に所定の接合手段14を用いて接合するようにして基
板12に実装する半導体装置において、半導体チツプ1
0、20の実装面の全面に渡つて分布するように配置さ
れた第1の接合部11を設けるようにした。
In order to solve such a problem, in the present invention, a plurality of first joint portions 11 are mounted on the mounting surface.
Are provided respectively, and each first joint portion 11 is provided with a corresponding second joint portion 1 provided on a predetermined surface of the substrate 12.
In the semiconductor device mounted on the substrate 12 so as to be bonded to the substrate 3 using a predetermined bonding means 14, the semiconductor chip 1
The first joint portions 11 arranged so as to be distributed over the entire mounting surfaces of 0 and 20 are provided.

【0007】また本発明においては、実装面に複数の第
1の接合部11がそれぞれ設けられ、各第1の接合部1
1を、それぞれ基板12の所定面に設けられた対応する
第2の接合部13に所定の接合手段14を用いて接合す
るようにして基板12に実装する半導体装置の実装方法
において、第1の接合部11を半導体チツプ10、20
の実装面の全面に渡つて分布するように配置し、各第1
の接合部11をそれぞれ基板12の第2の接合部13に
接合手段14を介して接合するようにした。
In the present invention, a plurality of first joint portions 11 are provided on the mounting surface, and each first joint portion 1 is provided.
In the mounting method of the semiconductor device, 1 is mounted on the substrate 12 so as to be bonded to the corresponding second bonding portions 13 provided on the predetermined surface of the substrate 12 by using the predetermined bonding means 14. The joint portion 11 is connected to the semiconductor chips 10 and 20.
It is arranged so that it is distributed over the entire mounting surface of
Each of the joint portions 11 is joined to the second joint portion 13 of the substrate 12 via the joining means 14.

【0008】さらに本発明においては、各第1の接合部
11を、半導体チツプ10の実装面の中央部から所定面
の各対角線に沿うようにそれぞれ配置した。
Further, in the present invention, each first joint portion 11 is arranged along the diagonal line of the predetermined surface from the central portion of the mounting surface of the semiconductor chip 10.

【0009】さらに本発明においては、各第1の接合部
11を、半導体装置20の実装面の中央部から所定面の
各端辺にそれぞれ垂直な各直線に沿うようにそれぞれ配
置した。
Further, in the present invention, each first joint portion 11 is arranged along the straight line which is perpendicular to each end side of the predetermined surface from the central portion of the mounting surface of the semiconductor device 20.

【0010】[0010]

【作用】半導体チツプ10、20の実装面の全面に渡つ
て分布するように配置された第1の接合部11を設ける
ようにしたことにより、第1の接合部11間の距離を小
さく抑えることができ、かくして温度変化等に起因する
当該半導体チツプ10、20の歪みを抑制することがで
きる。
By providing the first joint portions 11 arranged so as to be distributed over the entire mounting surfaces of the semiconductor chips 10 and 20, the distance between the first joint portions 11 is suppressed to be small. Therefore, it is possible to suppress the distortion of the semiconductor chips 10 and 20 due to the temperature change and the like.

【0011】[0011]

【実施例】以下図面について、本発明の一実施例を詳述
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

【0012】図1において、10は全体としてICフリツ
プチツプを示し、実装面に複数の電極及びダミー電極
(以下これらをまとめて単に電極11と呼ぶ)が中心部
から各対角線にそれぞれ沿うように直線状にそれぞれ設
けられている。このため図2に示すように、当該ICフリ
ツプチツプ10を実装する基板12のパターン面上に
は、当該ICフリツプチツプ10における各電極11と同
様の配置に複数のランド13がそれぞれ設けられてい
る。
In FIG. 1, reference numeral 10 indicates an IC chip as a whole, and a plurality of electrodes and dummy electrodes (hereinafter collectively referred to as electrodes 11) are linearly formed on the mounting surface so as to extend along respective diagonal lines from a central portion. Are provided in each. Therefore, as shown in FIG. 2, a plurality of lands 13 are provided on the pattern surface of the substrate 12 on which the IC flip chip 10 is mounted, in the same arrangement as the electrodes 11 of the IC flip chip 10.

【0013】これにより当該ICフリツプチツプ10にお
いては、各電極11をバンプ14を介して当該基板12
の対応するランドにそれぞれ接合することにより、基板
12に実装するようになされている。
As a result, in the IC flip chip 10, the electrodes 11 are connected to the substrate 12 via the bumps 14.
Are mounted on the substrate 12 by being bonded to the corresponding lands.

【0014】以上の構成において、ICフリツプチツプ実
装基板では、任意の2つの接合材間に生じるICフリツプ
チツプ10の歪みの大きさは接合材間距離に比例する。
この場合図5〜図7に示すような従来のICフリツプチツ
プ2では、図3及び図7からも明らかなように、接合材
間距離が最も長いのは同一の対角線上に位置する互いに
異なる隅部にそれぞれ配置された2つの接合材4A及び
4B並びに4C及び4D間であり、従つて当該ICフリツ
プチツプ2を基板1上に実装した場合には当該2つの接
合材4A及び4B並びに4C及び4D間のICフリツプチ
ツプ2に最も大きな歪みが生じる。
In the above-mentioned structure, in the IC flip chip mounting board, the magnitude of distortion of the IC flip chip 10 caused between any two joining materials is proportional to the distance between the joining materials.
In this case, in the conventional IC flip chip 2 as shown in FIGS. 5 to 7, it is clear from FIGS. 3 and 7 that the longest distance between the bonding materials is at the corners different from each other located on the same diagonal line. Between the two bonding materials 4A and 4B and 4C and 4D, respectively. Therefore, when the IC flip chip 2 is mounted on the substrate 1, it is between the two bonding materials 4A and 4B and 4C and 4D. The IC chip tip 2 has the largest distortion.

【0015】ところが実施例のICフリツプチツプ10で
は、上述のように実装面の中心部に複数のバンプ4が配
置されているために、接合材間距離が最も長いものでも
上述の2つの接合材4A及び4B並びに4C及び4D間
の接合材間距離に比べて十分に短く、従つて当該ICフリ
ツプチツプ10を基板12上に実装したときに温度変化
によつて発生する温度変化等に起因するICフリツプチツ
プ10の歪みの大きさを従来のICフリツプチツプ2に比
べて実用上十分に軽減することができる。
However, in the IC flip chip 10 of the embodiment, since the plurality of bumps 4 are arranged at the central portion of the mounting surface as described above, even if the distance between the bonding materials is the longest, the two bonding materials 4A described above are used. And 4B, and 4C and 4C and 4D are sufficiently shorter than the distance between the bonding materials, and accordingly, when the IC flip chip 10 is mounted on the substrate 12, the IC flip chip 10 caused by a temperature change caused by a temperature change or the like. In comparison with the conventional IC flip chip 2, the magnitude of the distortion can be reduced sufficiently in practical use.

【0016】以上の構成によれば、ICフリツプチツプ1
0の実装面に接合材としての複数のバンプ14を各対角
線にそれぞれ沿うように順次配置したことにより、従来
のICフリツプチツプ2に比べて温度変化によるチツプの
歪みを抑制できる。従つて温度変化等に起因するICフリ
ツプチツプ10及びバンプ14等の損傷を防止でき、か
くしてICフリツプチツプの信頼性を向上させることがで
きる。
According to the above configuration, the IC flip chip 1
By arranging a plurality of bumps 14 as bonding materials on the mounting surface of No. 0 so as to be along the respective diagonals, it is possible to suppress chip distortion due to temperature change as compared with the conventional IC flip chip 2. Therefore, it is possible to prevent the IC flip chip 10, the bump 14, etc. from being damaged due to a temperature change or the like, and thus improve the reliability of the IC flip chip.

【0017】またこの場合、ICフリツプチツプ10に形
成する電極11の数を従来のICフリツプチツプ2に形成
する電極の数と同一にするものとすると、この実施例の
ICフリツプチツプ10では隣接する電極11間の距離を
長くすることができるために基板12との接合に用いる
バンプ14を大きくすることができる。従つて各バンプ
14が破壊し難くなることにより、当該ICフリツプチツ
プ10の信頼性をさらに向上させることができる。
Further, in this case, assuming that the number of electrodes 11 formed on the IC flip chip 10 is the same as the number of electrodes formed on the conventional IC flip chip 2, this embodiment has the same structure.
In the IC flip chip 10, since the distance between the adjacent electrodes 11 can be increased, the bump 14 used for bonding with the substrate 12 can be enlarged. As a result, the bumps 14 are less likely to be broken, so that the reliability of the IC flip chip 10 can be further improved.

【0018】さらに当該ICフリツプチツプ10において
は、電極11間のピツチを従来のICフリツプチツプ2の
電極11間のピツチと同一にするものとすると、従来の
ICフリツプチツプ2に形成できるインプツト/アウトプ
ツト電極数よりも多くのインプツト/アウトプツト電極
を形成することができ、かくしてICフリツプチツプの信
頼性を向上させることができる。
Further, assuming that the pitch between the electrodes 11 in the IC flip chip 10 is the same as the pitch between the electrodes 11 of the conventional IC flip chip 2,
It is possible to form more input / output electrodes than the number of input / output electrodes that can be formed on the IC flip chip 2, thus improving the reliability of the IC flip chip.

【0019】なお上述の実施例においては、ICフリツプ
チツプ10の電極11を図1に示すように各対角線にそ
れぞれ沿うように順次形成するようにした場合について
述べたが、本発明はこれに限らず、例えば図4に示すよ
うに、ICフリツプチツプ20の実装面の互いに対向する
各辺の中央部を結ぶように電極11を順次形成するよう
にしても良く、要は、ICフリツプチツプ10の実装面に
バンプ14間の距離が大きくならないように電極11を
形成するのであれば、電極11の配置パターンとしては
この他種々のパターンを適用できる。
In the above embodiment, the electrodes 11 of the IC flip chip 10 are sequentially formed along the respective diagonal lines as shown in FIG. 1, but the present invention is not limited to this. For example, as shown in FIG. 4, the electrodes 11 may be sequentially formed so as to connect the central portions of the respective sides of the mounting surface of the IC flip chip 20 that face each other. If the electrodes 11 are formed so that the distance between the bumps 14 does not become large, various other patterns can be applied as the arrangement pattern of the electrodes 11.

【0020】また上述の実施例においては、ICフリツプ
チツプ10の実装面に当該ICフリツプチツプ10と基板
12とを接合する手段(接合材)としてのバンプ14を
各対角線にそれぞれ沿うように形成するようにした場合
について述べたが、本発明はこれに限らず、バンプ14
とバンプ14以外の他の接合材とを合わせて全体として
ICフリツプチツプ10の実装面に図1のようなパンプの
配置パターンを形成するようにしても良い。
Further, in the above-described embodiment, the bumps 14 as means (bonding material) for bonding the IC flip chip 10 and the substrate 12 are formed on the mounting surface of the IC flip chip 10 along the respective diagonal lines. However, the present invention is not limited to this.
And the bonding material other than the bump 14 as a whole
A bump arrangement pattern as shown in FIG. 1 may be formed on the mounting surface of the IC flip chip 10.

【0021】この場合当該バンプ14以外の他の接合材
は、ICフリツプチツプ10の電極11と基板12のラン
ド13間以外の所において当該ICフリツプチツプ10及
び基板12を接合するものであつても良い。
In this case, the bonding material other than the bump 14 may bond the IC flip chip 10 and the substrate 12 at a position other than between the electrode 11 of the IC flip chip 10 and the land 13 of the substrate 12.

【0022】[0022]

【発明の効果】上述のように本発明によれば、実装面に
複数の第1の接合部がそれぞれ設けられ、各第1の接合
部を、それぞれ基板の所定面に設けられた対応する第2
の接合部に所定の接合手段を用いて接合することにより
基板に実装する半導体装置において、半導体チツプの実
装面の全面に渡つて分布するように配置された第1の接
合部を設けるようにしたことにより、温度変化等に起因
する当該半導体チツプの歪みを抑制することができ、か
くして信頼性を向上させ得る半導体装置及び半導体装置
の実装方法を実現できる。
As described above, according to the present invention, a plurality of first joint portions are provided on the mounting surface, and each of the first joint portions is provided on the predetermined surface of the substrate. Two
In a semiconductor device which is mounted on a substrate by bonding to the bonding portion of the semiconductor chip using a predetermined bonding means, a first bonding portion arranged so as to be distributed over the entire mounting surface of the semiconductor chip is provided. As a result, it is possible to realize the semiconductor device and the mounting method of the semiconductor device, which can suppress the distortion of the semiconductor chip due to the temperature change or the like and thus improve the reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例のICフリツプチツプにおける電極の形成
パターンを示す平面図である。
FIG. 1 is a plan view showing an electrode formation pattern in an IC flip chip of an embodiment.

【図2】図1に示すICフリツプチツプを実装する基板の
ランドパターンを示す平面図である。
FIG. 2 is a plan view showing a land pattern of a substrate on which the IC flip chip shown in FIG. 1 is mounted.

【図3】接合材間距離の説明に供する平面図である。FIG. 3 is a plan view for explaining a distance between joining materials.

【図4】他の実施例を示す平面図である。FIG. 4 is a plan view showing another embodiment.

【図5】従来のICフリツプチツプを基板に実装した様子
を示す斜視図である。
FIG. 5 is a perspective view showing a state in which a conventional IC flip chip is mounted on a substrate.

【図6】接合材を用いてICフリツプチツプ及び基板を接
合したときの様子を示す側面図である。
FIG. 6 is a side view showing a state in which an IC flip chip and a substrate are joined using a joining material.

【図7】従来のICフリツプチツプに形成された接合部の
形成パターンを示す平面図である。
FIG. 7 is a plan view showing a formation pattern of a joint portion formed in a conventional IC flip chip.

【符号の説明】[Explanation of symbols]

1、12……基板、1A、2A……接合部、2、10、
20……ICフリツプチツプ、3……ICフリツプチツプ実
装基板、4、4A〜4D……接合材、11……電極、1
3……ランド、14……バンプ。
1, 12 ... Substrate, 1A, 2A ... Joint, 2, 10,
20 ... IC flip chip, 3 ... IC flip chip mounting substrate, 4, 4A to 4D ... Bonding material, 11 ... Electrode, 1
3 ... Land, 14 ... Bump.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】実装面に複数の第1の接合部がそれぞれ設
けられ、各上記第1の接合部を、それぞれ基板の所定面
に設けられた対応する第2の接合部に所定の接合手段を
用いて接合するようにして上記基板に実装する半導体装
置において、 上記半導体チツプの上記実装面の全面に渡つて分布する
ように配置された上記第1の接合部を具えることを特徴
とする半導体装置。
1. A plurality of first joint portions are respectively provided on a mounting surface, and each of the first joint portions is joined to a corresponding second joint portion provided on a predetermined surface of a substrate by a predetermined joining means. A semiconductor device mounted on the substrate in such a manner as to be bonded by using the above-mentioned semiconductor chip, wherein the semiconductor device is provided with the first bonding portion arranged so as to be distributed over the entire surface of the mounting surface of the semiconductor chip. Semiconductor device.
【請求項2】実装面に複数の第1の接合部がそれぞれ設
けられ、各上記第1の接合部を、それぞれ基板の所定面
に設けられた対応する第2の接合部に所定の接合手段を
用いて接合するようにして上記基板に実装する半導体装
置の実装方法において、 上記第1の接合部を上記半導体チツプの上記実装面の全
面に渡つて分布するように配置し、 各上記第1の接合部をそれぞれ上記基板の上記第2の接
合部に上記接合手段を介して接合することを特徴する半
導体装置の実装方法。
2. A plurality of first joint portions are respectively provided on the mounting surface, and each of the first joint portions is joined to a corresponding second joint portion provided on a predetermined surface of the substrate by a predetermined joining means. In the method for mounting a semiconductor device, which is mounted on the substrate in such a manner as to be bonded to each other, the first bonding portion is arranged so as to be distributed over the entire mounting surface of the semiconductor chip, and each of the first 2. The method for mounting a semiconductor device, wherein each of the joint portions is joined to the second joint portion of the substrate via the joining means.
【請求項3】各上記第1の接合部を、上記半導体チツプ
の上記実装面の中央部から上記所定面の各対角線に沿う
ようにそれぞれ配置したことを特徴とする請求項1に記
載の半導体装置。
3. The semiconductor according to claim 1, wherein each of the first bonding portions is arranged along a diagonal line of the predetermined surface from a central portion of the mounting surface of the semiconductor chip. apparatus.
【請求項4】各上記第1の接合部を、上記半導体装置の
上記実装面の中央部から上記所定面の各端辺にそれぞれ
垂直な各直線に沿うようにそれぞれ配置したことを特徴
とする請求項1に記載の半導体装置。
4. The first joint portions are arranged so as to extend along straight lines perpendicular to respective end sides of the predetermined surface from a central portion of the mounting surface of the semiconductor device. The semiconductor device according to claim 1.
JP25003293A 1993-09-10 1993-09-10 Semiconductor device and method of mounting semiconductor device Expired - Fee Related JP3334816B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25003293A JP3334816B2 (en) 1993-09-10 1993-09-10 Semiconductor device and method of mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25003293A JP3334816B2 (en) 1993-09-10 1993-09-10 Semiconductor device and method of mounting semiconductor device

Publications (2)

Publication Number Publication Date
JPH0786330A true JPH0786330A (en) 1995-03-31
JP3334816B2 JP3334816B2 (en) 2002-10-15

Family

ID=17201821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25003293A Expired - Fee Related JP3334816B2 (en) 1993-09-10 1993-09-10 Semiconductor device and method of mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP3334816B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203758A (en) * 2003-12-16 2005-07-28 Samsung Electronics Co Ltd Driving chip and display device having the same
US7427812B2 (en) 2004-03-15 2008-09-23 Casio Computer Co., Ltd. Semiconductor device with increased number of external connection electrodes

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203758A (en) * 2003-12-16 2005-07-28 Samsung Electronics Co Ltd Driving chip and display device having the same
US7903067B2 (en) 2003-12-16 2011-03-08 Samsung Electronics Co., Ltd. Driver chip and display apparatus having the same
US7427812B2 (en) 2004-03-15 2008-09-23 Casio Computer Co., Ltd. Semiconductor device with increased number of external connection electrodes

Also Published As

Publication number Publication date
JP3334816B2 (en) 2002-10-15

Similar Documents

Publication Publication Date Title
US6303998B1 (en) Semiconductor device having a chip mounted on a rectangular substrate
JP2001274196A (en) Semiconductor device
US20110266672A1 (en) Integrated-circuit attachment structure with solder balls and pins
JPH05109813A (en) Semiconductor device
JPH09260436A (en) Semiconductor device
JP2007189044A (en) Substrate and semiconductor device
JP2907168B2 (en) Semiconductor device and bonding structure of semiconductor device and substrate
JP2000133668A (en) Semiconductor device and mounting structure
JP2570468B2 (en) Manufacturing method of LSI module
JP3334816B2 (en) Semiconductor device and method of mounting semiconductor device
JPH0530083B2 (en)
JPH1197569A (en) Semiconductor package
JPH11307683A (en) Semiconductor device, printed wiring board mounting the same, and method of manufacturing the same
JP2000068271A (en) Wafer device, chip device, and method of manufacturing chip device
JP3270233B2 (en) Semiconductor device
KR100694455B1 (en) Semiconductor Package
JP3285017B2 (en) Semiconductor device
JPH0669371A (en) PGA package
JPH1167829A (en) Electronic component mounting method and electronic component and wiring board used in the method
JP2783233B2 (en) LSI package
JPH05326833A (en) Semiconductor mounting substrate
JPH098166A (en) Package equipment
JPH09283560A (en) Semiconductor device and manufacturing method thereof
JPH0543294B2 (en)
JPS6262533A (en) High-density mounting method for semiconductor element

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees