JPH0786790B2 - Counter value reading method - Google Patents

Description

The present invention relates to a method of reading a counter value of a counter having a counter width larger than the bus width of a data bus, and a method of reading a counter value capable of reducing the amount of program steps and increasing the processing speed. The counter value is read from a counter having a counter width larger than the bus width of the data bus by dividing the counter value into upper bits and lower bits and transferring them to the data bus through the selecting means. In the system, holding means for holding the upper bit at the timing of reading the lower bit is provided, and the upper bit held in the holding means is transferred to the selecting means at the next timing.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reading a counter value of a counter having a counter width larger than the bus width of a data bus.

Although various counters are used in the data processing device, some of these counters include, for example, TOD (Time
There is something that needs to read the value accurately by the instruction of the CPU like the clock. In such a counter, if the counter width is larger than the bus width of the CPU data bus, the data must be divided and read and transferred to the data bus. in this case,
Since the counter constantly changes while transferring a part of the counter value, the counter value may change before the remaining part is read. For this reason, carry correction is performed by software, but in this case, the step amount of the program increases and the processing speed decreases. Therefore, it is necessary to develop a reading method for correctly transferring the counter value for divided reading at high speed to the data bus without increasing the step amount.

[Prior Art] As a conventional reading method of a counter value, for example, there is one as shown in FIG.

In FIG. 4, 1 is a counter (for example, TOD clock), and this counter 1 is composed of, for example, lower 4 bytes and upper 1 byte, for a total of 40 bits. 2 is a data bus, and the bus width of this data bus 2 is 32 bits. The 40-bit counter value cannot be transferred to the 32-bit data bus 2 at one time. Therefore, the lower 4 bytes and the upper 1 byte are divided and read to the multiplexer 3, and the data selected by the multiplexer 3 is transferred to the data bus 2.

From the counter 1, first, the lower byte (08 to 39) is read, and then the upper 1 byte (00 to 07) is read. In this case, the value of the upper 1 byte is a value obtained by adding a carry to the value read as the upper 1 byte, because a carry occurs while reading the lower 4 bytes and then reading the upper 1 byte. Therefore, it is necessary to read the upper and lower levels twice and correct the values.

Specifically, the following carry correction is performed by a program.

・ At the first time, the lower 4 bytes read out are a and the upper 1 byte is A.

-The lower 4 bytes read out the second time are set to b, and the upper 1 byte is set to B.

When the MSB (most significant bit) of the lower 4 bytes a is "1" and the MSB (most significant bit) of b of the lower 4 bytes is "0"
In the case of, the MSB changes at the lower 4 bytes a and the lower 4 bytes b means that there was a carry propagation between the reading of the lower 4 bytes a and the reading of the lower 4 bytes b. To be

Here, if the upper 1 byte A = the upper 1 byte B, it means that the carry has propagated before the A is read, and therefore the carry must be corrected. At this time, the actual value of the upper 1 byte A is A-1.

On the other hand, if the upper 1 byte B = the upper 1 byte A + 1, it means that the carry has been propagated after A is read, and therefore the carry correction is unnecessary. Upper 1 byte A
It is considered that carry has propagated between the lower 4 bytes b and the lower 4 bytes b, and the actual value of the upper 1 byte A at this time is A.

When such carry correction is performed by hardware, the amount of hardware is significantly increased, so that it is performed by software (program).

[Problems to be Solved by the Invention] However, in such a conventional counter value reading method, since carry correction is performed by a program, the step amount of the program increases,
Further, there is a problem that the processing speed is also reduced.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a reading method of a counter value that can reduce the step amount of a program and increase the processing speed.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1, reference numeral 14 is a data bus, 11 is a counter having a counter width larger than the bus width of the data bus 14, and 16 is a counter value obtained by dividing the counter 11 into upper bits 12 and lower bits 13 and reading them. The selecting means 15 selects and transfers the upper bit 12 and the holding means 15 holds the upper bit 12 at the timing of reading the lower bit 13.

[Operation] Since a counter having a counter width larger than the bus width of the data bus cannot transfer the counter value to the data bus at one time, the lower byte is transferred and the upper byte is transferred. In this case, the lower byte is transferred. The upper byte is latched in the holding means at the timing of reading out to the selecting means.

That is, the counter constantly changes while transferring the lower byte, and when trying to transfer the upper byte, the data in the upper byte may have changed. When latching and transferring the next lower byte, the upper byte is transferred from the holding means to the selecting means. Therefore, the unchanged value of the data is transferred to the selecting means and transferred from the selecting means to the data bus.

As described above, since it is not necessary to perform carry correction by the program, the step amount of the program can be greatly reduced, and the processing speed can be significantly increased.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

2 and 3 are diagrams showing an embodiment of the present invention.

In FIG. 2, reference numeral 11 is a counter that constitutes, for example, a TOD (Time of Day) clock, and this counter 11 is constituted by 40 bits. Of the 40 bits (00-07), the high-order 1 byte 12 (08-15), (16-23), (24-31),
(32 to 39) form the lower 4 bytes 13. The counter 11 is incremented by 1 each time a clock is input. Reference numeral 14 is a data bus to which the counter value of the counter 11 is transferred, and the bus width of the data bus 14 is 32 bits.

The 32 bits consist of 4 bytes (00 to 07), (08 to 15), (16 to 23) and (24 to 31).

As described above, since the counter width of the counter 11 is larger than the bus width of the data bus 14, the counter value is divided into the lower 4 bytes 13 and the upper 1 byte 12 and transferred.

Reference numeral 15 is a latch circuit as a holding means, and this latch circuit 15 latches the upper 1 byte 12. That is, the bottom 4
When reading byte 13, the upper 1 byte 12 is latched at the same time. 15A is an AND circuit to which a timing signal for reading the lower 4 bytes 13 and a clock are input.
Enable the clock at the timing of reading byte 13,
At that clock, the latch circuit 15 takes in the upper 1 byte 12.

Reference numeral 16 is a multiplexer as a selection means. In the next cycle in which the lower 3 bytes 13 are fetched in the multiplexer 16, the upper 1 byte 12 is fetched from the latch circuit 15.
Multiplexer 16 selects the required data and data bus
Transfer to 14.

Next, the operation will be described.

FIG. 3 shows a time chart for explaining the operation.

In FIG. 3, A is data, A + 1 ... A + 4 is data obtained by adding 1 to the data A at the clock input, AL is the lower 4 bytes of the data A, and AH is the data A. The upper 1 byte of each is shown.

Also, TOD is the counter 11 and TODL is the lower 4 of the counter 11.
Byte, TODH is the upper 1 byte of counter 11, NDB is A
The state where L and AH are stored is shown respectively.

The data A of the counter 11 is incremented by 1 each time a clock is input, and changes to A + 1, A + 2, A + 3, A + 4 .... Since the counter 11 is constantly changing even after the lower 4 bytes 13 are transferred to the data bus 14, the counter value may change until the remaining upper 1 byte 12 is transferred to the data bus 14.

Therefore, at the timing of reading the lower byte 13 to the multiplexer 16, the upper 1 byte 12 is latched in the latch circuit 15. Then, at the next timing, the upper 1 byte 12 latched by the latch circuit 15 is transferred to the multiplexer 16.
By latching the remaining high-order 1 byte 12 in the latch circuit 15 as described above, the value of the high-order 1 byte 13 that has not changed remains in the multiplexer 16 even if the counter 11 changes and the counter value becomes the next value. Transferred. The multiplexer 16 selects necessary data and transfers it to the data bus 14.

As described above, by simply adding the latch circuit 15, it is not necessary to perform carry correction by the program, and the correct counter value can be transferred to the data bus 16. Therefore, the step amount of the program can be significantly reduced, and the processing speed can be significantly increased.

EFFECTS OF THE INVENTION As described above, according to the present invention, the upper byte of the counter is latched in the latch circuit at the timing of reading the lower byte and then transferred to the data bus. Therefore, carry correction by a program is performed. The number of steps of the program can be greatly reduced and the processing speed can be significantly increased.

[Brief description of drawings]

 FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a time chart, and FIG. 4 is a diagram showing a conventional example. In the figure, 11 ... Counter, 12 ... Higher 1 byte, 13 ... Lower 4 bytes, 14 ... Data bus, 15 ... Latch circuit (holding means), 15A ... And circuit, 16 ... Multiplexer (selection means).

Claims (1)

[Claims] 1. A selection means (16) for reading a counter value by dividing it into upper bits (12) and lower bits (13) from a counter (11) having a counter width larger than the bus width of a data bus (14). In the method of reading the counter value to be transferred to the data bus (14) via the holding means (15) for holding the upper bit (12) at the timing of reading the lower bit (13), the next timing The high-order bit (1
The method of reading the counter value is characterized in that 2) is transferred to the selecting means (16).