JPH07947Y2 - Voltage applied current measurement circuit - Google Patents
Voltage applied current measurement circuitInfo
- Publication number
- JPH07947Y2 JPH07947Y2 JP12275288U JP12275288U JPH07947Y2 JP H07947 Y2 JPH07947 Y2 JP H07947Y2 JP 12275288 U JP12275288 U JP 12275288U JP 12275288 U JP12275288 U JP 12275288U JP H07947 Y2 JPH07947 Y2 JP H07947Y2
- Authority
- JP
- Japan
- Prior art keywords
- current
- voltage
- transistor
- load
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005259 measurement Methods 0.000 title claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、負荷に設定電圧を印加して該負荷に流れる電
流を測定する電圧印加電流測定回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a voltage application current measuring circuit for applying a set voltage to a load and measuring a current flowing through the load.
従来、負荷に設定電圧を印加して該負荷に流れる電流を
測る場合、一般に、いわゆるVFM (Voltage Forcing Me
asurement)の機能をもった電源を用いて測る方法か、
あるいは、直列に電流計を挿入して測るか、または、直
列に抵抗を挿入し、該抵抗の電圧降下を電圧計によって
測る簡便な方法が採られてきた。Conventionally, when measuring a current flowing through a load by applying a set voltage to the load, generally, a so-called VFM (Voltage Forcing Mean) is used.
Assurement) method of measuring with a power supply,
Alternatively, a simple method has been adopted in which an ammeter is inserted in series for measurement, or a resistance is inserted in series and the voltage drop of the resistance is measured by a voltmeter.
上記の直列に電流計あるいは抵抗を挿入して測る簡便な
方法では、設定電圧に対し、電流計の内部抵抗あるいは
挿入抵抗による電圧降下分の誤差が生ずるという問題が
あった。The above simple method of inserting an ammeter or a resistor in series has a problem that an error of a voltage drop occurs due to the internal resistance of the ammeter or the insertion resistance with respect to the set voltage.
一方、従来の設定電圧全域にわたる電圧を補償するVFM
の機能をもった電源を組込んだ測定回路は、回路構成が
複雑で、高価であるという問題があった。On the other hand, VFM that compensates for the voltage over the conventional set voltage range
The measuring circuit incorporating the power supply having the function of has a problem that the circuit configuration is complicated and expensive.
本考案は上記の事情に鑑みてなされたもので、簡単な回
路構成で、誤差少なく測定できる回路を提供することを
目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit which has a simple circuit configuration and can perform measurement with a small error.
本考案の測定回路は、カレント・ミラー回路を用い、該
カレント・ミラー回路の一方のトランジスタのコレクタ
からの出力をオペアンプに負帰還することにより、該ト
ランジスタに順方向電流が流れた場合の電圧降下を補償
し、該カレント・ミラー回路の他方のトランジスタのコ
レクタに電流−電圧変換回路を接続し、設定電圧を上記
オプアンプの非反転入力端子に入力して上記カレント・
ミラー回路の上記一方のトランジスタのコレクタを経て
負荷に印加し、上記電流−電圧変換回路に現われる変換
電圧によって負荷に流れる電流を測定する構成としたも
のである。The measuring circuit of the present invention uses a current mirror circuit, and by negatively feeding back the output from the collector of one transistor of the current mirror circuit to an operational amplifier, a voltage drop occurs when a forward current flows through the transistor. Current-voltage conversion circuit is connected to the collector of the other transistor of the current mirror circuit, and the set voltage is input to the non-inverting input terminal of the op-amp to input the current
The mirror circuit is configured to be applied to the load via the collector of the one transistor and to measure the current flowing through the load by the converted voltage appearing in the current-voltage conversion circuit.
第1図は本考案の一実施例を示す回路図である。 FIG. 1 is a circuit diagram showing an embodiment of the present invention.
図において1は電圧入力端子、2はオペアンプ3a,3bは
カレント・ミラー回路を構成するトランジスタQ1,Q2,4
は電圧出力端子、5はオペアンプ、6は抵抗R1、7は負
荷である。In the figure, 1 is a voltage input terminal, 2 is operational amplifiers 3a and 3b, and transistors Q 1 , Q 2 and 4 are current mirror circuits.
Is a voltage output terminal, 5 is an operational amplifier, 6 is a resistor R 1 , and 7 is a load.
電圧入力端子1に設定電圧V1を印加すると、この電圧が
オペアンプ2の出力端子、トランジスタQ1を経て電圧出
力端子4に電圧V3として出力される。トランジスタQ1は
ダイオード接続になっているため、V3はV1に対してダイ
オードの順方向電圧分降下する。これを補償するため
に、トランジスタQ1の出力がオペアンプ2に負帰還され
ており、V1=V3となり、負荷7に設定電圧V1が途中で電
圧降下することなく印加される。When the set voltage V 1 is applied to the voltage input terminal 1, this voltage is output as the voltage V 3 to the voltage output terminal 4 via the output terminal of the operational amplifier 2 and the transistor Q 1 . Since the transistor Q 1 is diode-connected, V 3 drops with respect to V 1 by the diode forward voltage. In order to compensate for this, the output of the transistor Q 1 is negatively fed back to the operational amplifier 2, V 1 = V 3 , and the set voltage V 1 is applied to the load 7 without a voltage drop on the way.
トランジスタQ1とQ2がカレント・ミラー回路を構成して
いるため、トランジスタQ1に流れる電流I1とトランジス
タQ2に流れる電流I2の間には、トランジスタQ1,Q2の直
流増幅率をHFEとすると、 の関係が成立し、HFEが充分大きいと、I2がI1に殆ど等
しくなる。Since the transistors Q 1, Q 2 constitute a current mirror circuit, while the current I 2 flowing in the current I 1 and the transistor Q 2 to which flows through the transistor Q 1 is a direct current amplification factor of the transistor Q 1, Q 2 Is H FE , When the relation of is established and H FE is large enough, I 2 becomes almost equal to I 1 .
この電流I2をオペアンプ5と抵抗R1が構成する電流−電
圧変換回路で電圧に変換したV4(=−I2R)を測ること
で、負荷7を流れる電流値を得る。The current value flowing through the load 7 is obtained by measuring V 4 (= −I 2 R) obtained by converting the current I 2 into a voltage by the current-voltage conversion circuit configured by the operational amplifier 5 and the resistor R 1 .
以上のように、負荷7に設定電圧を印加し、負荷7を流
れる電流I1と殆んど等しい電流I2を電圧に変換して測る
構成のため、誤差の少ない測定ができる。As described above, since the setting voltage is applied to the load 7 and the current I 2 that is almost equal to the current I 1 flowing through the load 7 is converted into a voltage for measurement, measurement with less error can be performed.
第2図、第3図はそれぞれ本考案の他の実施例を示す回
路図である。2 and 3 are circuit diagrams showing other embodiments of the present invention.
図において1,2,3a,3b,4,5,6,7は第1図の同一符号と同
一または相当するものを示し、8,9はトランジスタQ3,Q
4、10は抵抗R2である。In the figure, 1,2,3a, 3b, 4,5,6,7 are the same as or corresponding to the same reference numerals in FIG. 1, and 8,9 are transistors Q 3 , Q
4 and 10 are resistors R 2 .
第2図に示すものは、基本動作は第1図に示す実施例と
同じで、電流I1と電流I2の近似性をより高めるために、
トランジスタQ3を追加したものである。この場合、電流
I1とI2の関係は となる。The one shown in FIG. 2 has the same basic operation as that of the embodiment shown in FIG. 1, and in order to further improve the approximation of the current I 1 and the current I 2 ,
This is the addition of transistor Q 3 . In this case, the current
The relationship between I 1 and I 2 Becomes
第3図に示すものは、負荷7に流れる電流が比較的に大
きい場合、オプアンプ2の出力電流の不足を補償するた
めに、トランジスタQ4を追加し、さらに、ミラー電流I2
を小さくするために、抵抗R2を挿入したもので、電流I1
に対し電流I2は で表わす電流に抑えられる。In the case shown in FIG. 3, when the current flowing through the load 7 is relatively large, a transistor Q 4 is added in order to compensate for the shortage of the output current of the op amp 2, and further, the mirror current I 2 is added.
For the smaller, obtained by inserting the resistor R 2, the current I 1
In contrast, the current I 2 is The current is suppressed to.
ここでK:ボルツマンの定数、T:絶対温度、q:電子の電荷
量、 この場合、抵抗R2を大きくすれば、電流計としての感度
が低下することがない。Here, K: Boltzmann's constant, T: absolute temperature, q: electron charge amount. In this case, if the resistance R 2 is increased, the sensitivity as an ammeter does not decrease.
上記には各トランジスタがPNPのものを示したが、NPNト
ランジスタにしてもよい。Although each transistor is shown as a PNP transistor in the above description, it may be an NPN transistor.
また、オペアンプ2の入力バイアス電流は、FET入力のB
i−FETタイプを使用すれば、カレント・ミラー回路に与
える影響は無視できる。Moreover, the input bias current of the operational amplifier 2 is B of the FET input.
If the i-FET type is used, the effect on the current mirror circuit can be ignored.
以上説明したとおり、本考案によれば、簡単な回路構成
によって、抵抗などによる電圧降下がもたらす誤差を含
むまない値が得られるという効果がある。As described above, according to the present invention, it is possible to obtain a value that does not include an error caused by a voltage drop due to a resistor or the like with a simple circuit configuration.
第1図は本考案の一実施例を示す回路図、第2図、第3
図はそれぞれ本考案の他の実施例を示す回路図である。 1……電圧入力端子、2……オペアンプ、3a,3b,8,9…
…トランジスタ、4……電圧出力端子、5……オペアン
プ、6,10……抵抗、7……負荷、 なお図中同一符号は同一または相当するものを示す。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2, and FIG.
Each of the drawings is a circuit diagram showing another embodiment of the present invention. 1 ... voltage input terminal, 2 ... operational amplifier, 3a, 3b, 8, 9 ...
... Transistor, 4 ... Voltage output terminal, 5 ... Op Amp, 6,10 ... Resistance, 7 ... Load, the same reference numerals in the drawings indicate the same or corresponding ones.
Claims (1)
電流を測定する電圧印加電流測定回路において、第1の
オペアンプの非反転入力端子に上記設定電圧を接続し、
該オペアンプの出力端子からダイオード接続した第1の
トランジスタを経て一端を接地した上記負荷に電流を流
すよう構成した電流回路、 上記第1のトランジスタと上記負荷との接続点の電圧を
上記第1のオペアンプの反転入力端子に接続し、上記負
荷に加えられる電圧がほぼ等しくなるよう制御するフィ
ードバック回路、 上記第1のトランジスタに対するカレントミラーを構成
し、上記第1のトランジスタに流れる電流とほぼ同一の
電流が流れる第2のトランジスタ、 第2のオペアンプの反転入力端子に上記第2のトランジ
スタの電流出力端子を接続し、該第2のオペアンプの非
反転入力端子を接地し、該第2のオペアンプの出力端子
と上記反転入力端子との間に所定抵抗値の抵抗を接続し
て構成した電流電圧変換回路を備えたことを特徴とする
電圧印加電流測定回路。1. A voltage application current measuring circuit for applying a set voltage to a load to measure a current flowing through the load, wherein the set voltage is connected to a non-inverting input terminal of a first operational amplifier,
A current circuit configured to flow a current from the output terminal of the operational amplifier to the load whose one end is grounded via a diode-connected first transistor, wherein the voltage at the connection point between the first transistor and the load is the first A feedback circuit connected to the inverting input terminal of the operational amplifier to control the voltage applied to the load to be substantially equal, and a current mirror that forms a current mirror for the first transistor and has a current that is substantially the same as the current flowing through the first transistor. Is connected to the inverting input terminal of the second operational amplifier, the current output terminal of the second transistor is connected, the non-inverting input terminal of the second operational amplifier is grounded, and the output of the second operational amplifier is A current-voltage conversion circuit configured by connecting a resistor having a predetermined resistance value between the terminal and the inverting input terminal is provided. Voltage source current measurement circuit for a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12275288U JPH07947Y2 (en) | 1988-09-21 | 1988-09-21 | Voltage applied current measurement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12275288U JPH07947Y2 (en) | 1988-09-21 | 1988-09-21 | Voltage applied current measurement circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0245468U JPH0245468U (en) | 1990-03-28 |
| JPH07947Y2 true JPH07947Y2 (en) | 1995-01-11 |
Family
ID=31370976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12275288U Expired - Lifetime JPH07947Y2 (en) | 1988-09-21 | 1988-09-21 | Voltage applied current measurement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07947Y2 (en) |
-
1988
- 1988-09-21 JP JP12275288U patent/JPH07947Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0245468U (en) | 1990-03-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6492845B1 (en) | Low voltage current sense amplifier circuit | |
| JPH07947Y2 (en) | Voltage applied current measurement circuit | |
| JPH0770935B2 (en) | Differential current amplifier circuit | |
| JP2778781B2 (en) | Threshold voltage generation circuit | |
| US6292056B1 (en) | Differential amplifier with adjustable common mode output voltage | |
| JPH09105680A (en) | Temperature measurement circuit | |
| JPH0624298B2 (en) | Current amplifier circuit | |
| JP2001201382A (en) | Air flow meter | |
| JP2862370B2 (en) | Current detection circuit | |
| JPS6211034Y2 (en) | ||
| JPS615321A (en) | Current-to-current converting circuit | |
| JP3001692B2 (en) | Voltage detection circuit | |
| JP2588164B2 (en) | Inverting amplifier | |
| JP2976487B2 (en) | Semiconductor device temperature characteristic correction device | |
| JPH089618Y2 (en) | Thermistor temperature conversion circuit | |
| JPH0332094Y2 (en) | ||
| JP2793194B2 (en) | Constant current circuit | |
| JP3258202B2 (en) | Differential circuit | |
| JPH0760981B2 (en) | Voltage-current conversion circuit | |
| JP2509463Y2 (en) | Differential amplifier circuit | |
| JPS5848597Y2 (en) | Reference junction compensation circuit | |
| JP2514235Y2 (en) | Amplifier circuit | |
| JPS6415175U (en) | ||
| JPH0354427Y2 (en) | ||
| JP3087352B2 (en) | Non-inverting amplifier |