JPH0797130B2 - Digital pattern generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital pattern generator used for inspection of electronic circuits such as timing analysis, that is, a digital pattern generator for generating a timing waveform.

[0002]

2. Description of the Related Art Digital pattern generators are mainly IC
It is used for motion analysis and timing analysis of electronic circuits. FIG. 11 shows a block diagram of a digital pattern generator, which includes a control circuit 10 using a microprocessor (CPU) and a memory circuit (data) that stores a digital data pattern (or simply data pattern). A pattern RAM) 20 and a timing adjustment circuit 40 that changes the output timing based on the signal from the memory circuit 20. Further, the parallel-serial conversion circuit 30 may be provided between the memory circuit 20 and the timing adjustment circuit 40 to convert low-speed parallel data into high-speed serial data. The timing adjustment circuit 40 is
It comprises a timing waveform generation circuit 60 for generating a rough timing waveform, a delay / pulse width variable circuit 50 for finely adjusting its output, and a clock generation circuit 42. Hereinafter, the timing waveform generating circuit 60 will be mainly described.

FIG. 12 shows D as a typical output waveform of a digital pattern generator used for timing analysis.
NRZ (Delayed Not Return To Zero)
The waveform, the RZ (return to zero) waveform, and the R1 (return to one) waveform are shown. These waveforms are usually obtained by adding processing such as delay to the 1 or 0 digital data pattern output from the data pattern RAM 20 in synchronization with the data clock.

For example, the DNRZ waveform is a waveform obtained by delaying the digital pattern output from the RAM 20 as it is (without changing the waveform) in synchronization with the data clock. The RZ waveform is the digital output of RAM20.
If the pattern is 1, it starts at 0, becomes 1 after the set time, and then returns to 0 after the set time, while
If the pattern is 0, the waveform is maintained at 0. R
Contrary to RZ, if the digital pattern is 0, the waveform starts at 1 and becomes 0 after a set time, and then returns to 1 after the set time, while the digital pattern becomes 1
If so, 1 is a waveform that is maintained.

The conventional circuits for generating the RZ waveform and the R1 waveform are roughly classified into the following two types. That is,
They are "data pattern control type circuit" and "timing clock control type circuit". These are shown in FIGS. 13 and 14. Note that these figures show only the case of the RZ waveform for simplicity. In either method, usually, a fine delay / pulse width variable circuit 50 is used for fine timing adjustment, that is, adjustment of delay, rising edge, falling edge, pulse width up to several tens of nanoseconds.
(For example, Bt62 manufactured by Brooktree)
2 type IC etc.). Therefore, here, there is no problem in waveform generation in a minute range of several nanoseconds. Also, regarding the difference in the method here, not the fine adjustment by the delay / pulse width variable circuit 50, but the circuit for generating a large timing waveform of the pattern generator will be examined.

FIG. 13 shows a data pattern control type circuit 1.
10 is a block diagram of a conventional example of No. 00. This has a counter means 110 for each channel, and each counter means 110 includes a counter control circuit 112, two counters 114 and 116, and an RS flip-flop (F
F) 118. These counters 114 and 1
A count value is set in each of 16 and counts the data clock. At this time, the output of the counter 114 is input to the S (set) input terminal of the RS flip-flop 118, and the output of the counter 116 is input to the R (reset) input terminal. Therefore, when the counter 114 finishes counting the data clock by the set value from the time when the data pattern becomes 1, the RS flip-flop 118 is set and its output becomes 1. Following this, when the counter 116 finishes counting the set value, the RS flip-flop 118 is reset, the output returns to 0, and the RZ
A waveform is generated.

FIG. 14 is a block diagram of a conventional example of the timing / clock control circuit 200. Each channel of the circuit 200 has a timing selection circuit 210, and each timing selection circuit 210 includes the data control circuit 2.
12, two multiplexers (MUX) 214 and 21
6 and a D flip-flop 218. The output of the D flip-flop 218 becomes 1 when 1 is input to the clock input end while 1 is input to the D input end. Also, as soon as 1 is input to the R (reset) input terminal, its output is reset and returns to 0.
In this embodiment, the data pattern is input to the D input terminal, the output signal of the MUX 214 is input to the CLK (clock) input terminal, and the MUX2 is input to the R (reset) input terminal.
16 output signals are input.

FIG. 15 shows a block diagram of the clock generating means 230 shown in FIG. The clock generating means 230 generates a plurality of clocks having different frequencies based on a reference clock using a counter or the like, and uses the CLKH clock for the rising edge as the MUX 214.
The CLKL clock for the falling edge to MUX2
Supply to 16. Each MUX selects a clock having an appropriate frequency from a plurality of clocks. Then, after the data pattern from the RAM becomes 1, the output of the D flip-flop 218 becomes 1 when the output from the MUX 214 is received at the clock input terminal. The output of the MUX 216 then resets the D flip-flop 218 so that the output returns to 0 and an RZ waveform is generated. The circuit 20
In the case of 0, the output waveforms of all channels are not independent, and are limited by the number of types of clocks generated by the clock generating means 230.

In both of these two types, the timing of rising and falling of the waveform is changed by counting the clock with a counter. At this time, if the timing is arbitrarily changed, the output waveform of each channel can be arbitrarily changed and output. Also, if the R1 waveform is required, the data pattern may be inverted and input to each circuit, and the output thereof may be further inverted.

[0010]

In the data pattern control type circuit, since each channel has a rising edge of the waveform and a counter required for the rising edge, an independent waveform can be generated for each channel. Further, the means for generating the clock becomes simpler as compared with the case of controlling the timing clock. However, several or more high-speed counters are required for each channel, which is expensive and consumes a large amount of power. If the number of channels is further increased, the circuit scale becomes very large.

The timing / clock control type circuit has a counter or the like on the basic clock generator side to generate timing clocks of a necessary type required for rising and rising of a waveform, and raising them for each channel.
Since the selection is made at each falling edge, only the clock selection circuit (MUX) and the register are required for each channel. Therefore,
If the number of selectable clocks is limited as compared with the case of controlling the data pattern, the circuit scale per channel can be reduced, and when the number of channels is increased, the cost is low and the power consumption is low. However, the types of waveforms that can be used are limited to the number of types of timing clocks that can be generated by the clock generation means, and the output of each channel cannot be made completely independent.

Therefore, an object of the present invention is to provide a digital pattern generator which requires a relatively small circuit scale even if it has multiple channels. Another object of the present invention is to provide a digital pattern generator capable of outputting an independent digital pattern waveform from each channel.
Still another object of the present invention is to provide a digital pattern waveform capable of outputting a digital pattern waveform having an arbitrary waveform according to the setting.
The purpose is to provide a pattern generator.

[0013]

The digital pattern generator of the present invention is constructed as follows. That is, the data clock generating means 44 generates a data clock. The timing clock generating means 46 generates a timing clock faster than the data clock. At this time, the timing clock may be divided to generate the data clock. A RAM may be used as the data pattern generating means 20, which operates in synchronization with a data clock and outputs a digital data pattern. The timing waveform memory means 64, which is suitable for using RAM, operates in synchronization with the timing clock and outputs the timing waveform stored in advance. Address means 7
0 supplies an address to the timing waveform memory means to output a timing waveform. Logical product generation means
80 is a digital data pattern and timing wave
Generates and outputs the logical product of shapes. Furthermore, the sequential circuit
The output of the logical product generation means 80 and the timing waveform
It is also possible to generate an output with a predetermined pulse width that is fixed.
Yes. According to this, the output over two cycles of the timing waveform
Can also be generated.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention. This is based on the data pattern output from the memory circuit (data pattern RAM) 20 in accordance with the data clock, and operates the timing RAM 64 at a timing clock faster than the above-mentioned data clock to generate a waveform for each data clock. Is generated. The register 90 is a synchronization register that prevents glitches and synchronizes the timing waveform with the timing clock. According to the present invention, not only a normal RZ waveform or the like, but also an arbitrary timing waveform written in the timing RAM 64 can be output. Hereinafter, this new timing waveform will be referred to as a return-to-program (RP) waveform. FIG. 2 is a timing chart of various timing waveforms that can be generated by the digital pattern generator of the present invention.

The timing clock is easier to control when it is an integral multiple of the data clock, but it is not always required to be an integral multiple. However, the timing pattern RA
The address generator for M74 must be initialized to synchronize with the timing clock for each data clock. Therefore, if the data clock generator 44 divides the timing clock from the timing clock generator 46 to generate the data clock, the circuit can be simplified.

Timing by the timing RAM 64
Regarding the output of the pattern waveform, the case of outputting the RZ waveform will be described as an example. As shown in FIG. 3, it is assumed that the timing RAM 64 can generate a timing waveform having twice the frequency of the data pattern output at the maximum clock frequency at which the data pattern RAM 20 can operate. Then, when the data clock frequency is the highest frequency, since the period of 1 in the data pattern is the shortest, the timing RAM 64 outputs 00, 0.
Only 1, 10, or 11 timing patterns can be generated. However, as the data clock frequency becomes lower, the period of 1 in the data pattern becomes longer. Therefore, if the timing pattern previously written in the timing RAM 64 is output during the period of 1 of the data pattern, it becomes various. RZ waveform of can be output. For example, when the frequency is lowered, 0000, 0001, ...
The timing pattern waveforms such as 1110 and 1111 may be read from the timing RAM 64 and the data pattern may be output during the period of 1. By lowering the frequency of the data clock in this way, various timing waveforms can be output within the range permitted by the capacity of the timing RAM 64. For example, the RP waveform can be output.

In order to generate the RZ waveform from the timing RAM 64, a waveform of "010" is required at least, but when the frequency is high, there are cases where only the waveforms of 01, 10, etc. can be produced as described above. . However, in this case, since the pulse width of the waveform is very short, it may be adjusted by the delay / pulse width variable circuit 50 in the subsequent circuit.
For example, 10 patterns of delay / pulse width variable circuit 50
If it is input to, a waveform such as 010 can be obtained by first delaying for a certain time and then changing the pulse width. In this way, the delay / pulse width variable circuit 50 has
Not only the function of slightly delaying the pulse for several picoseconds to tens of nanoseconds, but also the function of changing the pulse width may be provided. Of course, such a delay / pulse width variable circuit may not be used, and a delay circuit and a pulse width variable circuit may be provided independently. I explained the RZ waveform, but of course R
One waveform can be similarly generated. For example, the data pattern may be inverted and input to the circuit, and its output may be further inverted.

FIG. 4 shows an embodiment having a 4-channel output according to the present invention. In this example, the data pattern of 4 channels is the upper 4 of the timing RAM 64.
Bits A11 to A8 are supplied to D3 to D0
To output a timing waveform of four channels. The timing RAM 64 has four memory cells corresponding to D3 to D0. However, these four memories
The cell addresses are A11 to A0, which are common.

5 and 6 show examples of memory cells corresponding to D3 and D0, respectively. As can be seen from the figure, the upper 4 bits A1 for each memory cell
16 addresses can be selected by specifying addresses 1 to A8. However, as can be seen from FIG. 5, for the memory cell for D3, if A11 is "0", X is "
If it is 1 ", it is set to select Y. Also, as can be seen from FIG.
If A8 is "0", X is selected, and if "1", Y is selected. In other words, by inputting to A11,
The output of D3 is uniquely determined as X or Y. Similarly, D2
D0 is also uniquely determined by the inputs of A10 to A8. For the X or Y determined in this way, the memory cell is "0" or "1" by supplying the output of the address generator that changes with the timing clock to the A7 to A0 addresses of the lower 8 bits. Output the pattern of RZ waveform, R1 waveform, etc. and 25 for each X or Y
Six types of waveforms are selectively output. As a result, the bottom 8
This means that an operation is performed in which the upper 4 bits select 256 patterns determined by the bits. That is, the memory is used as a calculation means. However, in this example, it is necessary to prepare 8 patterns of 256 patterns for the same X or Y for each memory cell, which is a waste of memory usage.

FIG. 7 shows another embodiment having a 4-channel output according to the present invention. Timing RAM 64
Has 4 memories corresponding to 4 channels.
Have cells. However, one type of timing pattern is written in each memory cell, and
Regardless of the pattern, one kind of timing from the timing RAM 64 according to the output from the address generator
The pattern (timing waveform) is output. Calculation of Figure 7
As indicated by the AND gate symbol of means 80, R
Timing pattern RAM with 1 or 0 of data pattern depending on whether to output Z waveform or R1 waveform
Output from 64 (timing waveform)
By taking de), generating an RZ waveform or R1 waveform
Can be output. According to this, since the capacity of the timing RAM 64 required to store the timing pattern is one pattern for each channel, it may be smaller than that in the case of FIG. Further, a format combining the two of FIGS. 4 and 7 may be used. That is, after the data pattern is input to the timing RAM 64 as an address to obtain the output, the output and the data pattern may be further calculated.

FIG. 8 is a block diagram of still another embodiment of the present invention. In the circuits shown in FIGS. 4 and 7, RZ,
The R1 and RP waveforms could be generated, but the DNRZ waveform cannot be generated as it is. In other words, since it is based on the waveform output from the timing RAM 64 within one cycle, it is impossible to generate a waveform that exceeds one cycle of the timing RAM 64 and extends over two cycles, as in the DNRZ waveform. It was But,
According to FIG. 8, a small addition to the circuit that generates the RZ waveform
A DNRZ waveform can also be generated simply by adding a circuit .

The output of the DNRZ waveform will be described. First, the pattern for one clock of the timing clock is written in the address of the timing RAM 64 corresponding to the time when the rising transition of the DNRZ waveform occurs. The contents of other addresses are 0. By default, the output of the timing register 90 is 0. The operation is started from this state. Data pattern is 1
Then, if the output of the timing RAM 64 also changes to 1 and the address becomes 1, the output of the timing register 90 becomes 1. The register 90 holds the output of 1 even if the output of the timing RAM 64 changes. In order for the output of the timing register 90 to change to 0, the data pattern becomes 0, the output of the timing RAM 64 also changes to 0, and the timing clock comes subsequently. Therefore, in order to set the output to 0, the timing register 90 and its value are fed back to form a sequential circuit. It can consist of several gates. in this way,
A DNRZ waveform is obtained by using the timing register 90.

An AND gate 82 shown in FIG. 8 corresponds to the arithmetic circuit 80 shown in FIG.
The use of 4 is similar to that described in FIG. 7.
If the timing RAM 64 is used as described with reference to FIG. 4, the AND gate 82 may not be used. Further, the RZ waveform and the DNRZ waveform can be selected by the mode signal received by the NOR gate 84.
In this example, if the mode signal is 0, the DNRZ waveform is obtained, and if the mode signal is 1, the RZ waveform is obtained. In addition,
If the RZ waveform can be generated as described above, the R1 waveform can be easily generated.

FIGS. 9 and 10 are timing charts showing the time relationship of the signals at each point of the circuit according to the mode signal in FIG. As shown in FIG. 9, when the mode signal is 0, a DNRZ waveform in which only the delay amount is changed can be generated without changing the width of the data pattern. On the other hand, as shown in FIG. 10, when the mode signal is 1 and the data
When the pattern is also 1, the timing waveform (RZ waveform, R1 waveform, etc.) in which the width of the output of the timing RAM 64 and the delay amount are controlled can be generated. Actually, the timing RAM 64
To the timing RAM 6 using a slightly faster clock to the timing register 90.
Allow the gate circuit output using the output of 4 to be successfully captured in the timing register 90. Similarly, the delay time of the data pattern needs to be adjusted so that it can be properly captured in the timing register 90. Note that an arithmetic circuit may be added for application to the circuit described in FIG.

As described above, when the present invention is compared with the data pattern control type circuit 100, it is not necessary to have several high-speed ECL counters for each channel, and one small-capacity high-speed RAM is provided for several channels. Since it only needs to be carried, it consumes less power. ECL of 4 outputs with 4k bits
If an (emitter coupled logic) RAM is used, one ECL RAM can output four channels. Further, when the conventional data pattern control type circuit has multiple channels, the circuit scale is very large, and in practice, it is used as an ECL gate array, which is very expensive. On the other hand, according to the present invention, similar pattern timing can be generated by a relatively inexpensive normal ECL RAM.

Further, in comparison with the conventional timing / clock control type circuit 200, the present invention can generate a timing waveform independently for each channel, and the power consumption is E
The power consumption can be halved as compared with the timing selection circuit 210 which is composed of two CL multiplexers. Furthermore, the number of parts used can be significantly reduced.

Further, the major feature of the present invention is that, unlike the prior art, it does not generate the rising and falling edges of the timing waveform but uses the pattern contents of the timing RAM 64, so that RZ, R1
In addition to the DNRZ waveform and the DNRZ waveform, an RP (return to program) waveform that can be called an arbitrary timing waveform such as 010011 can be generated as long as it can be written in the timing RAM. Thus, the present invention is capable of producing almost any timing waveform of a commonly needed digital pattern.

[0028]

According to the digital pattern generator of the present invention, even if there are multiple channels, it is not necessary to use a plurality of counters for each channel, so that the circuit scale can be relatively small. On the other hand, it is possible to output an independent digital pattern waveform from each channel. If various timing waveforms are stored in the timing waveform memory means, many waveforms required for timing analysis can be output. At this time, since the logical product generating means generates and outputs the logical product of the data pattern and the timing waveform, the capacity of the timing waveform memory means that requires high speed operation is relatively small and inexpensive.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital pattern generator of the present invention.

FIG. 2 is a timing chart showing timing waveforms that can be generated by the digital pattern generator of the present invention.

FIG. 3 is a timing chart when the data clock has the highest frequency.

FIG. 4 is a block diagram of an embodiment of the timing adjustment circuit of the digital pattern generator of the present invention.

FIG. 5 is a diagram showing setting of a memory cell for D3 output of the timing RAM.

FIG. 6 is a diagram showing setting of a D0 output memory cell of the timing RAM.

FIG. 7 is a block diagram of another embodiment of the timing adjustment circuit of the digital pattern generator of the present invention.

FIG. 8 is a block diagram of still another embodiment of the timing adjustment circuit of the digital pattern generator of the present invention.

9 is a diagram showing a timing chart when the mode signal is set to 0 in the circuit shown in FIG.

10 is a diagram showing a timing chart when the mode signal is set to 1 in the circuit shown in FIG.

FIG. 11 is a block diagram showing a conventional example of a digital pattern generator.

FIG. 12 is a diagram showing a typical output waveform of a digital pattern generator used for timing analysis.

FIG. 13 is a block diagram of a conventional example of a data pattern control type circuit 100 of a digital pattern generator.

FIG. 14 is a block diagram of a conventional example of a timing / clock control type circuit 200 of a digital pattern generator.

15 is a block diagram of the clock generation means 230 shown in FIG.

[Explanation of symbols]

 10 Control Circuit 20 Data Pattern RAM 40 Timing Adjustment Circuit 44 Data Clock Generating Means 46 Timing Clock Generating Means 50 Delay / Pulse Width Variable Circuit 60 Timing Waveform Generating Circuit 62 RAM Control Circuit 64 Timing RAM 82 AND Operation Generating Means 84, 86, 90 Sequential circuit

Claims (2)

[Claims] 1. A data clock generating means for generating a data clock, a timing clock generating means for generating a timing clock faster than the data clock, and an operation in synchronization with the data clock. Then, a data pattern generating means for outputting a digital data pattern, a timing waveform memory means for operating in synchronization with the timing clock and outputting a prestored timing waveform, and an address for the timing waveform memory means are provided. A digital pattern generator comprising: addressing means for supplying; and logical product generating means for generating and outputting a logical product of the digital data pattern and the timing waveform. 2. The output of the logical product generation means and the tie
Sequence of generating output with a predetermined pulse width determined by the minging waveform
The digital pattern generator of claim 1 further comprising a circuit.
Raw organ.