JPH0797367B2 - 1-chip microcomputer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer.

[0002]

2. Description of the Related Art An example of a conventional one-chip microcomputer having a logic circuit that operates asynchronously with a clock input is a one-chip microcomputer having an event counter. In this example, the power-down operation is performed by an event input that is asynchronous with the clock input. However, the count value or overflow that is the output of the counter is read in or synchronized with the clock input, and is not connected to the output terminal of the one-chip microcomputer as an output signal that operates asynchronously with the clock input.

Another example is a one-chip microcomputer having a serial input / output port. In this example as well, a serial input signal asynchronous with the clock input is directly or parallel-converted and read or interrupted in synchronization with the clock input.
Since the serial output modulates and outputs the output data set up in synchronization with the clock input, it may not be synchronized with the clock input. However, the signal input to the serial input terminal is processed once in synchronization with the clock input, and the newly generated signal is output to the output terminal as output data. Serial input and serial output operate asynchronously with the clock input. Does not correspond to the input and output of the logic circuit.

Another example is a one-chip microcomputer having a phase lock loop circuit. In this case, the output signal is generated without directly involving the microcomputer with respect to the input signal, which is referred to in the present invention as
A set of input terminals and output terminals that operate without synchronizing with the clock input may be configured. However, the phase-locked loop circuit is an analog circuit as its main constituent element, and does not correspond to the logic circuit which operates asynchronously with the clock input in the present invention.

[0005]

In the prior art, the processing cycle time T ₀ of the one-chip microcomputer and the
The fastest cycle time T ₁ of the input and output signal systems that operate asynchronously with the clock input that can be processed by the chip microcomputer is T ₁ > = T ₀ , and only very slow processing can be performed. Therefore, in the field where high-speed processing is required, it is impossible to effectively use the multi-stage time-series processing capability of a one-chip microcomputer and the processing capability corresponding to many conditions.

Further, in the prior art, the output of the 1-chip microcomputer is output to, for example, a logical product gate from the risk that the 1-chip microcomputer may deviate from the normal operation due to external noise or other causes and start a runaway. The measures were taken such as connecting and forcibly holding down the AND gate in the situation where a runaway might start.

In the above-mentioned theory, in the prior art, various logic circuits are connected to the outside of the one-chip microcomputer in order to cope with the case where high-speed operation is required or the case where danger is prevented.

An object of the present invention is to provide a one-chip microcomputer which requires such an external logic circuit and simultaneously realizes the processing capability of the one-chip microcomputer and high-speed signal processing.

[0009]

The one-chip microcomputer of the present invention is an internal synchronization signal generating an internal synchronization signal.
Command generation circuit and execute instructions in synchronization with the internal synchronization signal
Control circuit and a plurality of bits generated from the control circuit.
And a data holding circuit for holding data
A one-chip microphone
Output enable signal is input from outside the computer.
Input terminal and the 1-chip microcomputer
An output terminal for outputting a plurality of bits of data to the outside,
The multi-bit data held in the data holding circuit, and
Input the output enable signal input to the input terminal
However, if the output enable signal indicates output prohibition,
The one-chip microcomputer through the output terminal
Fixed to either the first level or the second level outside the
Output multiple bits of data and output the output enable signal.
If the signal indicates output permission, the corresponding 1
The multi-bit data is stored outside the chip microcomputer.
The first level depending on the data content of each bit of the data or
A logic circuit that outputs a second-level multi-bit data
It is characterized by having.

[0010]

When an input signal is applied to the input terminal of the set of the input terminal and the output terminal which operate without being synchronized with the clock input configured as described above, the internal clock input is irrelevant regardless of the clock input timing. An output appears at an output terminal paired with the input terminal according to an asynchronous logic circuit that operates asynchronously.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.

According to an embodiment of the present invention, a one-chip microcomputer which directly or frequency-divides a clock input to determine a machine cycle or an instruction cycle and executes an instruction has a logic circuit which operates asynchronously with a clock, A part of the input signal of the logic circuit is connected to a part of the input terminal of the one-chip microcomputer as an input terminal, and a part or all of the output signal of the logic circuit
An output terminal is provided as a part of the output terminal of the chip microcomputer, and an input terminal and an output terminal that operate without synchronizing with a clock are configured. Therefore, if an input signal is given to the input terminal among the input terminal and the output terminal that operate without synchronizing with the clock input, the output terminal will follow the asynchronous logic circuit that operates asynchronously with the internal clock regardless of the clock timing. The output appears in.

In FIG. 1, the clock input 4 is supplied to the internal synchronizing signal generating circuit 2b, and the internal synchronizing signal generating circuit 2b.
Generates a plurality of internal sync layers 2d.

Reference numeral 2a is a main control circuit of the one-chip microcomputer, and in the present embodiment, it receives a plurality of internal synchronizing signals 2d and outputs an 8-bit data output signal 2f and an 8-bit data latch clock 2e.

The 8-bit data output signal 2f is latched (held) in an 8-bit latch (data holding circuit) 2c in synchronization with the 8-bit data latch clock 2e. 2 above
The circuit 2 which includes a to 2f and executes an instruction in synchronization with the clock input 4 outputs the 8-bit latch data output signals 6a to 6 to the logic circuit 3 which operates asynchronously with the clock input 4.
It outputs h.

The asynchronous logic circuit 3 which operates asynchronously with the clock input 4 is composed of eight 2-input AND circuits 3a. The input enable signal 5 is connected to one input of the 2-input AND circuit 3a to enable the output enable. When the signal 5 is at 0 level, all eight data outputs 7a to 7h of the eight 2-input AND circuit 3a are at 0 level. In this embodiment, 1 level of the data outputs 7a to 7h is valid and 0 level is invalid, and in the above case, the data outputs 7a to 7h.
Since all of h are 0 level, when the output enable signal 5 is 0 level, all the data outputs 7a to 7h are in the invalid state.

When the output enable signal 5 is 1 level, the levels of the 8-bit latch data output signals 6a to 6h appear in the eight data outputs 7a to 7h as they are.

As described above, in this embodiment, the output enable signal 5 which is the input signal of the asynchronous logic circuit 3 which operates asynchronously with the clock input 4 is supplied to the 1-chip microcomputer 1.
And the data outputs 7a to 7h, which are output signals of the asynchronous logic circuit 3, as a part of the output terminals of the one-chip microcomputer 1, and the set of the input terminal and the output terminal of the asynchronous logic circuit 3. Is configured as. The eight 2-input AND circuits 3a of this embodiment may be configured by a gate array, a programmable logic array, or an erasable programmable pull logic array.

[0019]

According to the present invention, the multi-stage time-series processing capability of the conventional one-chip microcomputer and the processing capability capable of handling many conditions can be introduced into a circuit system that must perform high-speed processing. Further, since the logic circuit which has conventionally been required to be placed outside is not necessary, the processing capacity, space, cost and reliability of the system can be greatly improved by using the one-chip microcomputer of the present invention.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a one-chip micro computer of the present invention.

[Explanation of symbols]

 2 ... Circuit that executes instructions in synchronization with clock input 4 ... Logic circuit that operates asynchronously with clock input 4 ... Clock input 5 ... Output enable signal 6a-6h ... Data output

Claims (4)

[Claims] 1. An internal synchronization signal generating circuit for generating an internal synchronization signal, a control circuit for executing an instruction in synchronization with the internal synchronization signal, and a data holding device for holding a plurality of bit data generated by the control circuit. A 1-chip microcomputer including a circuit, an input terminal to which an output enable signal is input from the outside of the 1-chip microcomputer, and an output terminal that outputs data of a plurality of bits to the outside of the 1-chip microcomputer. The multi-bit data held in the data holding circuit and the output enable signal input to the input terminal are input, and when the output enable signal indicates output prohibition, the one-chip microcomputer of the one chip microcomputer is input via the output terminal. External data of multiple bits fixed to either the first level or the second level When the output enable signal indicates output permission, a plurality of first-level or second-level signals are output to the outside of the one-chip microcomputer via the output terminal according to the data content of each bit of the multi-bit data. A one-chip microcomputer including a logic circuit for outputting bit data. 2. The one-chip microcomputer according to claim 1, wherein the logic circuit is composed of a gate array. 3. The one-chip microcomputer according to claim 1, wherein the logic circuit is configured by a programmable logic array. 4. A one-chip microcomputer according to claim 1, wherein said logic circuit is composed of an erasable programmable logic array.