JPH01199242A - Microcomputer system abnormality detection device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microcomputer-based abnormality detection device used in a control system using a microcomputer as a control device.

BACKGROUND ART FIG. 3 is a schematic block diagram of a control system incorporating this type of conventional device, FIG. 4 is a block diagram showing in more detail the input/output relationship of the abnormality detection device shown in FIG. 3, and FIG. The figure is a block diagram of the same device.0 First, in Figure 3, 1 is a main control unit, and 2 is a sub-control unit, both of which are mainly composed of a microcomputer (hereinafter referred to as a microcomputer). It is something that Reference numeral 3 denotes an abnormality detection device, and this abnormality detection device 3 monitors the operation of the microcomputer in the main control section 1 using a main monitoring signal inputted from the main control section 1, and outputs a switching signal when an abnormality occurs in the main control section 1. The changeover switch SW is switched to the sub side. As a result, the control system is configured to transfer control to the sub-control section 2 when an abnormality occurs in the main control section 1.

4 is an input system consisting of various sensors for obtaining data used for control, and 5 is an output system consisting of controlled equipment and the like.

In FIG. 4, 6a is a microcomputer of the main control unit 1;
8a is a clock generating section, and 8a is an abnormality detecting section which together with the clock generating section 7 constitutes the abnormality detecting device 3.

The microcomputer 6a outputs the main monitoring signal (WDTR8T in the figure) at a cycle within a predetermined range.

The clock generator 7 generates a clock signal with a constant period (C in the figure).
K).

The main monitoring signal from the microcomputer 6a and the clock signal from the clock generator 7 are input to the abnormality detection section 8a.The abnormality detection section 8a measures the input period of the main monitoring signal using the clock signal. By doing so, an abnormality in the microcomputer 6a is detected and a switching signal (BU in the figure) is generated.Reset in the figure is a hard reset signal at power-up, etc.

As shown in FIG. 5, the abnormality detection section 8a is roughly composed of a counter 2o called a watchdog timer, a D flip-flop 21, and an OR gate 22a.

The counter 20 performs a timekeeping operation by counting the clock signal from the clock generator 7, and outputs a carry when the count is up. The time from the start of counting by the counter 20 to the carry output is the maximum allowable value of the input cycle of the main monitoring signal, that is, the carry is the abnormality detection signal of the microcomputer 6a.

The carry signal is input to the D input terminal of the flip-flop 21, and the clock signal from the clock generator 7 is input to the tarlock input terminal of the flip-flop 21. When a carry enters the D input terminal of this 7-lip flop 21, the Q output terminal becomes high. This corresponds to the switching signal described above.

A main monitoring signal and a hard reset signal are input to the OR gate 22a, and its output is input to the R input terminal of the counter 20.

This allows the counter 20 to be reset by either of the two signals. The hard reset signal is also input to the R input terminal of the flip-flop 21 so that it is reset.

Next, the operation will be explained.

When the microcomputer 6a is in a normal operating state, the main monitoring signal is output from the microcomputer 6a at a cycle within a predetermined range, and the counter 20 is initialized repeatedly at that cycle, so that it does not output a carry.

Therefore, the Q output terminal of the clip-flop 21 also remains low, and control by the main control section 1 continues.

Then, when an abnormality occurs in the microcomputer 6a and the main monitoring signal is no longer output at a cycle within the predetermined range, the counter 20 counts up and a carry signal is output.

Therefore, the Q output terminal of the flip-flop 21 becomes high, and control is transferred from the main control section 1 to the sub-control section 2.

In this way, even the conventional abnormality detection device can detect an abnormality in the microcomputer 6a by detecting that the output cycle of the main monitoring signal no longer falls within a predetermined range.

Problems to be Solved by the Invention However, in the conventional abnormality detection device described above, the main monitoring signal is output through a signal line of a certain length that is unrelated to the microcomputer system, so an abnormality may occur in this signal line. In this case, it may be detected as abnormal even though the microcomputer system is normal, or it may not be detected even though there is an abnormality in the microcomputer system, which may affect the reliability of the detection operation. There was a problem with missing parts.

Furthermore, for the same reason, it was difficult to detect abnormalities in various pass lines belonging to the microcomputer system, and the performance was not sufficient.

The present invention is intended to solve such conventional problems, and aims to provide a microcomputer-based abnormality detection device that improves the reliability of detection operation and the detection ability.

Means for Solving the Problems In order to achieve the above object, the present invention provides a microcomputer system with the following features:
A monitoring data generating means is provided for outputting monitoring data such as address data, write command data, and writing data at a cycle within a predetermined range through various path lines, and the address data and write command data are input to an address decoder. A write command signal is generated, and when the time measurement deviates from the cycle within the predetermined range, the time measurement content of a timer that generates an abnormality detection signal of the microcomputer system is initialized by the write command signal, and the write command signal is In addition to monitoring the output cycle, each write data has a specific relationship with each other, and when the write command signal is received, this write data is taken into one register, and at the same time, this one register is A shift register is provided to shift the data stored in the register to another register, and the data in that one register and the other register are fed to a judgment circuit, and the judgment circuit determines whether a specific relationship is established between both data. It is designed to monitor.

Therefore, according to the present invention, since signals for microcomputer monitoring are outputted through various path lines belonging to the microcomputer system, malfunctions due to abnormalities unrelated to the microcomputer system can be prevented as much as possible.

Monitors the output cycle of address data and write command data output through the data bus, address bus, and control bus, as well as monitors the specific relationship that should be established between each write data output through the data bus. This makes it possible to reliably detect not only abnormalities in the microcomputer itself, but also abnormalities in each of these pass lines.

Embodiments Below, embodiments of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the input/output relationship in an embodiment of the abnormality detection device according to the present invention, and FIG. 2 is a block diagram of the same device. It is a diagram.

First, in FIG. 1, 6b is a microcomputer of the main control section, and this microcomputer 6b alternately outputs write command data and read command data through the control bus 10 at a cycle within a predetermined range, and at the same time outputs write command data and read command data through the address bus 10. 11, and each time write command data is output, write data having a specific relationship with the previous data is output through the data bus. The write/read command data and address data are applied to the address decoder 9, where they are decoded into a write command signal (WDWE in the figure) and a read command signal (WDRE in the figure).

Reference numeral 8b denotes an abnormality detecting section which together with the conventional clock generating section 7 constitutes an abnormality detecting device. This abnormality detection section 8b is
An abnormality in the microcomputer 6b is detected by monitoring the output cycle of the write command signal and read command signal from the address decoder 9 and the establishment of a specific relationship between the write data coming through the data bus 12, as in the conventional case. generates a switching signal.

In FIG. 2, 22b is a three-man-powered OR gate, and a write command signal, a read command signal, and a hard reset signal are input to 22b, and its output is input to the R input terminal of the counter 20. .

This counter 20 and flip-flop 21 are the same as those in FIG.

23 is a shift register, and 23a and 23b are D flip-flops forming each bit thereof.

The microcomputer 6b is connected to the D input terminal of the flip-flop 23a.
On the same day, the write data is input from the input terminal, and the write command signal is input to the input terminal of the flip-flop 23a.When the flip-flop 23a receives the write command signal, the content of the write data appears at the Q output terminal. It has become. A hard reset signal is input to the S input terminal of the flip-flop 23a, so that the Q output terminal is at a high level in an initial state such as when power is turned on.

The output of the Q output terminal of the flip-flop 23a is input to the D input terminal of the flip-flop 23b, and the write command signal is input to the same clock input terminal. When received, the contents of the Q output terminal of flip-flop 23a appear at its Q output terminal.

That is, when the write command signal is output, the write data is taken into the flip-flop 23a, and the data stored in the flip-flop 23a is shifted to the flip-flop 23b. A node reset signal is input to the R input terminal of the flip-flop 123b, and the Q output terminal of the flip-flop 23b is set to a low level in the initial state.

24 is a 3-state buffer, and this buffer 24
inputs the output of the Q output terminal of the flip-flop 23a, and becomes enabled, that is, in a readable state in response to a read command signal.

The microcomputer 6b outputs read command data to
It also has a function of reading data from the flip-flop 23a using the buffer 24, generating data in a complementary relationship with this data, and using this data as write data. In other words, the above-mentioned specific relationship is here a complement relationship.

Here, the step corresponding to the access function to the shift register 23 of the microcomputer 6b is that in the first access after the power is turned on, read command data is outputted together with address data to read the data of the flip-flop 23a, and the read data is Create complement data and (
For convenience of explanation, this step will be referred to as step a. ) In the next access, address data, write data, and their complement data are output as write data (for convenience of explanation, this is referred to as step b). From then on, these steps are repeated in the order of step a and step b. .

25 is a comparator, this comparator 25 is
By inputting the output of the Q output terminal of the flip-flop 23a as a negative input, and inputting the output of the Q output terminal of the flip-flop 23b as a positive input, and comparing the two, it is determined whether or not a complement relationship is established between the two. It is something to do. This comparator 25 outputs a low level when it determines that it is true, and outputs a low level when it determines that it does not hold true.
Become Ileperu. This high level signal becomes an abnormality detection signal.

26 is a flip-flop, and the output of the comparator 25 is input to the D input terminal of this flip-flop 26.
A write command signal is input to the taro clock input terminal. As a result, when the output of the comparator 25 reaches the ``1'' level, the Q output terminal of the flip-flop 26 becomes a high level at the timing of the write command signal, and a switching signal (BU) is output.

Reference numeral 27 denotes an OR gate for outputting a switching signal, and the switching signals from the flip-flops 21 and 26 are outputted to the changeover switch SW via this OR gate 27.

Next, the operation of the above embodiment will be explained.

When the microcomputer 6b is in a normal operating state, the microcomputer 6b outputs access data at a cycle within a predetermined range. Therefore, the counter 20 is reset by the read command signal and the write command signal, and the access data is output within the predetermined range. Since the initialization is repeated periodically, it is not possible to output a carry.

On the other hand, the flip-flop 23 of the shift register 23
Since the data in a and 23b also maintain a complement relationship, the output of the comparator 25 remains at a low level.

If an abnormality occurs in the program execution state of the microcomputer 6b, the control path 10, or the address bus 11, and the address data and read/write command data are not output at a cycle within a predetermined range, the counter 20 starts counting. UP and outputs a carry. Therefore, the output of the flip-flop 21 becomes high level,
A switching signal is output from the OR gate 27, and the control section is switched to the sub.

Furthermore, when an abnormality occurs in the data bus 12, the complementary relationship between the data in the flip-flops 23a and 23b is disrupted, so the output of the comparator 25 becomes high level, the output of the flip-flop 26 becomes high level, and switching is performed from the OR gate 27. A signal will be output. Therefore, even if an abnormality occurs in the data bus 12, the control section can be switched to the sub.

In this way, according to the above embodiment, address data, read/write command data, write data, and read data, which are signals for monitoring the microcomputer system, are sent and received through the pass line. It is possible to prevent malfunctions due to abnormalities in absent areas as much as possible.

In other words, the output cycle of the access data outputted through the control bus 10 and the here address path 11 is monitored, and the complement relationship set between each write data outputted through the data bus 12 is monitored. , not only abnormalities in the main body of the microcomputer 6b but also abnormalities in each pass line are reliably detected.

Note that in the above embodiment, the flip-flop 23a123
We created a complementary relationship between each data in b, but if we create a more complex relationship as the specific relationship, the correct relationship will be erroneously maintained even though an abnormality has occurred. This will prevent this from happening.

Effects of the Invention As is clear from the above embodiments, the present invention outputs microcomputer monitoring signals through various path lines belonging to the microcomputer system, so malfunctions may occur due to abnormalities unrelated to the microcomputer system. This has the effect that the detection operation can be prevented as much as possible, and the reliability of the detection operation is improved.

Monitors the output cycle of address data and write command data output through the data bus, address bus, and control bus, as well as monitors the specific relationship that should be established between each write data output through the data bus. This makes it possible to reliably detect not only abnormalities in the microcomputer itself, but also abnormalities in various path lines, and has the effect of improving detection ability.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a microconbeater-based abnormality detection device according to the present invention, Fig. 2 is a block diagram showing the input/output relationship of the device, and Fig. 3 is a block diagram of a control system in which the device is incorporated. FIG. 4 is a block diagram showing the outline, FIG. 4 is a block diagram showing the input/output relationship in a conventional abnormality detection device, and FIG. 5 is a block diagram showing the configuration of the abnormality detection device shown in FIG. 4 in detail.・Microcomputer, 7...Clock generator, 8b・
... Abnormality detection unit, 9... Address decoder, 10...
・Control bus, 11...Address bus, 12・
...Data bus, 20...Counter, 21...Flip-flop, 23...Shift register, 25...
comparator. Name of agent: Patent attorney Toshio Nakao and one other person Figure 4 Figure 5

Claims (1)

[Claims] Consists of a part of a microcomputer system, it outputs address data through the address bus at a cycle within a predetermined range, and at the same time outputs write command data through the control bus. monitoring data generating means for outputting write data having a specific relationship with the data; an address decoder for generating a write command signal based on the address data and the write command data; When this happens, it is detected as an abnormality in the microcomputer system and outputs the abnormality detection signal, and a timer whose timing is initialized by the write command signal, and a timer whose timing is initialized by the write command signal, A shift register that takes in data into one register and simultaneously shifts the data stored in this one register to another register; Abnormality detection for a microcomputer system, comprising: a determination circuit that determines whether a specific relationship is established, and when it is not established, detects this as an abnormality in the microcomputer system and outputs the abnormality detection signal. Device.