JPH0799610A - Solid-state image sensor - Google Patents

Abstract

(57) [Abstract] [Purpose] The transfer efficiency between horizontal registers can be improved by increasing the charge transfer time until the signal charges in the final stage of vertical registers are transferred to the transfer area between horizontal registers. , The vertical streak defect rate is significantly reduced. [Structure] In a frame / interline transfer type image sensor having an image part and a storage part,
The final stage and the first stage of the vertical register 15 in the storage section
Between the first horizontal register H1 and the first and second VH transfer areas 16a and 16b for transferring the signal charges transferred to the final stage of the vertical register 15 to the first horizontal register H1.
To form. Then, these VH transfer areas 16a and 1
P-type impurity diffusion regions 18a and 18b are respectively formed under 6b by high-energy ion implantation of P-type impurities, and the potential distribution in the first and second VH transfer regions 16a and 16b is the first. The horizontal register H1 is set so as to be inclined downward.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device having a plurality of horizontal registers, and more particularly to a solid-state image pickup device for improving charge transfer efficiency between horizontal registers.

[0002]

2. Description of the Related Art Recently, as the number of horizontal pixels increases,
For example, in an image sensor for 2 million pixel HDTV, the read frequency of the signal output and the horizontal register (C
Since the driving frequency of (CD) becomes high, the structure of one horizontal register that has been conventionally used causes problems such as an increase in power consumption for driving the CCD and a decrease in charge transfer efficiency in the horizontal register. Is coming.

Therefore, as a solution to these problems, a structure of a CCD solid-state image pickup device having a plurality of horizontal registers has been proposed (Television Society, Vol. 41, N).
11 (1987) "Ultra High Resolution CCD Image Sensor" and Japanese Patent Laid-Open No. 1-308072).

In this CCD image sensor, as shown in FIG. 10, a large number of light receiving portions (not shown) for photoelectrically converting into an amount of electric charge according to the amount of incident light are arranged in a matrix, and the plurality of light receiving portions are also arranged. Of these, a plurality of vertical registers (not shown) that are common to the light receiving units arranged in the column direction, the image unit 101 arranged in the row direction, and the image unit 101 are arranged adjacent to the image unit 101. There is no light receiving part formed in the image part 101, and the storage part 10 in which only a large number of vertical registers are continuously formed so as to be continuous with the plurality of vertical registers in the image part 101.
2 is a so-called frame interline transfer (FIT) type image sensor.

This image sensor has a storage unit 10
Two horizontal registers, which are adjacent to two and which are common to a large number of vertical registers, are arranged side by side. Here, of the two horizontal registers, the horizontal register located on the storage unit side is referred to as a first horizontal register H1, and the other horizontal registers are referred to as a second horizontal register H2. Then, between the storage unit 102 and the first horizontal register H1, the signal charges transferred to the vertical register at the final stage in the storage unit 102 are stored in the first horizontal register H1.
2 vertical-horizontal transfer areas (hereinafter,
VH transfer areas) 103a and 103b are formed in common and parallel to a large number of vertical registers.

Further, between the first and second horizontal registers H1 and H2, a register for selectively transferring the signal charges once transferred to the first horizontal register H1 to the second horizontal register H2. An inter-transfer area 104 is formed. This inter-register transfer area 104 is a horizontal register H
1 and H2 are formed to extend in the horizontal direction, and as shown in FIG. 12, at positions corresponding to vertical registers in, for example, odd columns (... 2n-3 columns, 2n-1 columns) of the vertical registers. Channels that block transfer of signal charge
Each stopper region CS is formed.

On the vertical register in the image section 101 and the vertical register in the storage section 102,
For example, four vertical transfer electrodes ST1 to ST4 made of a two-layer polycrystalline silicon layer are formed via insulating films, respectively. That is, four vertical transfer electrodes ST1 to ST4 are set as one set, and a large number of the sets are sequentially arranged in the vertical direction. Then, each of the four vertical transfer electrodes ST1
To ST4 are supplied with four vertical transfer pulses φST1 to φST4 having different phases from each other. By supplying these vertical transfer pulses φST1 to φST4, the potential distribution under the vertical transfer electrodes ST1 to ST4 is changed. It changes sequentially, which causes the signal charge to be transferred vertically along the vertical register.

Particularly, in the image section 101, the signal charge accumulated in the light receiving section is
First, the data is read to the vertical register, and then, within this vertical blanking period, the signal charges transferred to the vertical register are transferred at high speed to the vertical register of the storage unit 102.

The storage section 102 transfers the signal charges transferred to the vertical register in the vertical blanking period to the horizontal register side in units of one row in the subsequent horizontal blanking period. As a result, the signal charges in the final stage of the vertical register are transferred to the two VH transfer regions 103a and 103b.
First, the signal charges for the odd columns (... 2n-3 columns, 2n-1 columns) among them are transferred to the first horizontal register H1, and the channel stopper region CS formed in the register-to-register transfer region 104. , The transfer to the second horizontal register H2 is stopped, and the even columns (... 2n-4 columns,
Signal charges relating to the 2n−2 column, 2n column) are transferred to the second horizontal register H2.

Then, in the next horizontal scanning period, for example, the first horizontal transfer electrode GH1 and the second horizontal transfer electrode GH2 are formed of, for example, two layers of polycrystalline silicon layers formed on the horizontal registers H1 and H2. 2 with different phases
By applying the phase horizontal transfer pulses φH1 and φH2,
The signal charges are sequentially transferred to the output unit 105 (see FIG. 10) side, combined in the output unit 105, and taken out as the image pickup signal S from the output terminal φout.

First and second horizontal transfer electrodes GH1 and G
H2 is the horizontal register H1 and H as shown in FIG.
2 are alternately arranged in the lateral direction, and the shape thereof is, for example, in terms of the first horizontal transfer electrode GH1, on the first horizontal register H1, for example, an odd number column (... 2n-3 columns). , 2n−1 columns), the transfer electrodes H between the registers are provided at the positions corresponding to the vertical registers.
Even columns on H (... 2n-4 columns, 2n-2 columns, 2n
It is bent to the side corresponding to the vertical register for the column) and is continuously arranged on the second horizontal register H2 at a position corresponding to the vertical register for the even column.

The same applies to the second horizontal transfer electrode GH2. First, the second horizontal transfer electrode GH2 is arranged on the first horizontal register H1 at a position corresponding to the vertical register for an even column, and on the way to the inter-register transfer electrode HH for an odd column. It is bent to the side corresponding to the vertical register, and is continuously arranged on the second horizontal register H2 at a position corresponding to the vertical register for the odd column.

Then, in this conventional image sensor, in order to improve the charge transfer efficiency between the horizontal registers H1 and H2, as shown in FIG. 12, the transfer electrodes formed on the first horizontal register H1 are connected. The potential distribution in the first horizontal register H1 is set between the registers by, for example, forming a reverse fan shape (divergent shape) or continuously changing the concentration distribution of the impurity diffusion region forming the first horizontal register. It is designed to be inclined downward in the charge transfer direction.

That is, the image section 101, the storage section 102, the first and second VH transfer areas 103a and 103b, and the first horizontal register H shown on the line CC in FIG.
1. Looking at the potential distribution of each impurity diffusion region when the same potential (for example, 0 V) is applied to each transfer electrode formed on the inter-register transfer region 104 and each impurity diffusion region of the second horizontal register H2. , As shown in FIG. 11, from the image portion 101 to the second VH transfer area 103b.
Is a flat distribution, the first horizontal register H1 has a downward slope toward the second horizontal register H2 side, and the first horizontal register H1 extends from the inter-register transfer area 104 to the second horizontal register H2. The potential distribution of the horizontal register H1 is continuous with a flat distribution.

Here, the transfer state of the signal charges in the conventional image sensor will be described with reference to the timing chart of FIG. 13 and an operation conceptual diagram showing potential changes under various transfer electrodes shown in FIGS. 14 and 15. In the figure, φST1 to φST4 are first to fourth vertical transfer pulses supplied to the first to fourth vertical transfer electrodes ST1 to ST4, respectively, and φVH1 and φVH2 are first and second vertical transfer pulses, respectively.
VH transfer electrodes VH1 and VH2 are supplied with the first and second VH transfer pulses, and φH1 and φH2 are supplied with the first and second horizontal transfer electrodes GH1 and GH2. , ΦHH represent inter-register transfer pulses supplied to the inter-register transfer electrodes HH. In addition, the operation conceptual diagrams shown in FIGS. 14 and 15 show a pair of transfer states of signal charges relating to odd-numbered columns and transfer states of even-numbered columns at each time.

The state at time t1, that is, the first and second vertical transfer electrodes S in the storage section 102
From the state where the signal charge e is accumulated in the potential well continuously formed under T1 and ST2, and the signal charge e is accumulated in the potential well formed under the first VH transfer electrode VH1, The transfer state of e will be described.

First, at the next time t2, the third vertical transfer pulse φST3, the second VH transfer pulse φVH2, and the register-to-register transfer pulse φHH are at high levels, so that the signal charge e is stored in the storage section 102. At the final stage, transferred / stored in potential wells continuously formed under the first to third vertical transfer electrodes ST1 to ST3,
At the same time, the signal charges are transferred / stored in the potential wells continuously formed under the first and second VH transfer electrodes VH1 and VH2.

At the next time t3, since the first vertical transfer pulse φST1 and the first VH transfer pulse φVH1 are at low levels, the signal charge e is the second and third in the final stage of the storage section 102. Of the vertical transfer electrodes ST2 and ST3, the signal charges are transferred and accumulated in the potential well formed continuously, and at the same time, the signal charges are transferred and accumulated in the potential well formed under the second VH transfer electrode VH2.

At the next time t4, the fourth vertical transfer pulse φST4 is at a high level, and the second VH transfer pulse φVH2.
Becomes low level, the signal charge e is transferred / stored in the potential well continuously formed under the second and third vertical transfer electrodes ST2 and ST3 in the final stage of the storage section 102. At this time, the signal charge e under the second VH transfer electrode VH2 at the time t3 is transferred to the first horizontal register H1 side because the potential under the second VH transfer electrode VH2 becomes shallow. It
In this case, since the potential of the first horizontal register H1 has a downward slope toward the second horizontal register H2 side, the signal charge e is generated by the first horizontal register H1.
1 is transferred to the register transfer area 104 at high speed,
As a result, it is stored under the inter-register transfer electrode HH.

Then, at the next time t5, the second vertical transfer pulse φST2 becomes low level and the first VH transfer pulse φVH1 becomes high level, so that the signal charge e is stored in the final stage of the storage section 102. No. 3 vertical transfer electrode ST3 to the first VH transfer electrode VH1 are continuously transferred and accumulated in the potential well formed below. At this time, the signal charge e transferred under the inter-register transfer electrode HH remains stored under the inter-register transfer electrode HH.

At the next time t6, since the first vertical transfer pulse φST1 becomes high level, the storage unit 1
The signal charge e in the previous stage of the final stage of 02 is transferred below the first vertical transfer electrode ST1. At this time, the signal charge e at the final stage of the storage unit 102 is still accumulated in the potential well formed continuously from below the third vertical transfer electrode ST3 to below the first VH transfer electrode VH1. Even under HH, the signal charge e is still accumulated.

At the next time t7, since the third vertical transfer pulse φST3 becomes low level, the signal charge e in the final stage is below the fourth vertical transfer electrode ST4 and below the first VH transfer electrode VH1. It will be transferred and accumulated in the continuously formed potential wells. At this time, since the first horizontal transfer pulse φH1 simultaneously becomes high level, the potential under the horizontal register H1 relating to the odd-numbered columns becomes deep in the first horizontal register H1, and the second horizontal register H2 becomes Horizontal register H2 for even columns
The lower potential becomes deeper. As a result, the transfer of the signal charges e for the odd columns is stopped at the channel stopper region CS formed in the inter-register transfer region 104, and the transfer of the signal charges for the even columns under the inter-register transfer electrodes HH and It is transferred and accumulated in the potential well formed continuously under the second horizontal register H2.

At the next time t8, the second vertical transfer pulse φST2 becomes high level, so that the signal charge e in the previous stage of the final stage is continuously formed under the first and second vertical transfer electrodes ST1 and ST2. Will be transferred and accumulated in the potential wells. At this time, there is no potential change in the first and second horizontal transfer pulses φH1 and φH2 and the register-to-register transfer pulse φHH, so the state at t7 is still maintained.

At the next time t9, since the fourth vertical transfer pulse φST4 and the register-to-register transfer pulse φHH are both at low level, the signal charge e at the final stage is the first
VH transfer electrode VH1 is transferred to and accumulated in a potential well formed under. At this time, the inter-register transfer electrode H
Since the potential under H becomes shallow, the signal charge e relating to the even column under the inter-register transfer electrode HH is completely transferred to the potential well of the second horizontal register H2.
As a result, the signal charges e related to the odd columns are distributed to the first horizontal register H1 and the signal charges e related to the even columns are distributed to the second horizontal register H2.

[0025]

As described above, in the conventional image sensor, for example, the HDT of 2 million pixels is used.
In order to apply to a V image sensor or the like, the number of horizontal registers is two in order to reduce the driving frequency of the horizontal registers by half. In this case, there is a problem that charge distribution transfer between the two horizontal registers H1 and H2 is difficult and causes a vertical streak defect. However, as described above, the transfer formed on the first horizontal register H1. Electrode G
The shape of H1 is, for example, an inverted fan shape (divergent shape) to enhance the electric charge transfer electric field of the first horizontal register H1. Alternatively, the concentration distribution of the impurity diffusion region forming the first horizontal register H1 is continuously changed so that the potential distribution in the first horizontal register H1 is inclined downward in the charge transfer direction between the registers H1 and H2. By the first
Measures such as strengthening the charge transfer electric field of the horizontal register H1 are taken.

However, even if the above measures are taken, the transfer efficiency of the distribution of the signal charges to the first and second horizontal registers H1 and H2 is not yet perfect, and the charge transfer electric field of the first horizontal register H1 is changed. It is necessary to improve the distribution transfer efficiency by further strengthening or by increasing the distribution transfer time.

That is, in the conventional image sensor,
As can be seen from the timing chart of FIG. 13 and the operation conceptual diagrams of FIGS. 14 and 15, the first VH transfer electrode VH
It takes from t1 to t4 to transfer the signal charge e under 1 below the register transfer electrode HH, and the signal charge e at the final stage of the storage unit 102 is transferred below the first VH transfer electrode VH1. There is only a short time t until the initial time t5 of the period during which the signal charge e is transferred, and the above period starts before the transfer of the signal charges e is completed. There is a problem that efficiency cannot be effectively improved.

The present invention has been made in view of the above problems, and an object thereof is to reduce the charge transfer time until the signal charges in the final stage of the vertical register are transferred to the transfer region between the horizontal registers. It is an object of the present invention to provide a solid-state imaging device that can be taken for a long time, can improve the transfer efficiency between horizontal registers, and can significantly reduce the vertical streak defect rate.

[0029]

According to the present invention, a large number of light receiving portions for photoelectrically converting into an amount of electric charge according to the amount of incident light are arranged in a matrix, and among the large number of light receiving portions, the light receiving portions are arranged in the column direction. A solid-state image pickup in which a large number of vertical registers that are common to the light receiving unit are arranged in a row direction, and a plurality of horizontal registers that are common to the plurality of vertical registers arranged in the row direction are arranged. 2 in the transfer area between the final stage of the vertical register and the horizontal register in the device.
The present invention has a plurality of transfer electrodes, and the potential distribution below these transfer electrodes is configured to be inclined downward toward the horizontal register side.

In this case, the potential distribution under the vertical register in the electrically neutral state may be made shallower than that of the horizontal register. Further, it is preferable that the drive pulse supplied to each transfer electrode is an alternating pulse when the charge in the final stage of the vertical register is transferred to the horizontal register side.

[0031]

In the solid-state image sensor according to the present invention, two pixels are provided on the transfer area between the final stage of the vertical register and the horizontal register.
Since there are book transfer electrodes, and the potential distribution under these transfer electrodes is inclined downward toward the horizontal register side, the charges transferred to the final stage of the vertical register can be transferred to the horizontal register side at high speed. This makes it possible to transfer charges between a plurality of horizontal registers at high speed.

Further, by making the potential distribution under the vertical register in an electrically neutral state shallower than that of the horizontal register, it is possible to prevent the generation of a fringing electric field generated between the vertical register and the horizontal register. , The charges can be transferred to the horizontal register side without causing a reduction in the maximum handled charge amount transferred by the vertical register.

Further, when the electric charge at the final stage of the vertical register is transferred to the horizontal register side, the drive pulse supplied to each transfer electrode is an alternating pulse to prevent the occurrence of a fringing electric field between the transfer electrodes. You can, and
Since the potential distribution under the transfer electrode is inclined downward toward the horizontal register side, the charges transferred to the final stage of the vertical register can be transferred at high speed and without causing transfer residue.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a solid-state image sensor according to the present invention is applied to a so-called frame / interline transfer type image sensor (hereinafter, simply referred to as an image sensor according to the embodiment) will be described with reference to FIGS. While explaining.

The image sensor IS according to this embodiment is
As shown in FIG. 1, a large number of light receiving portions (not shown) for photoelectrically converting into an amount of electric charge according to the amount of incident light are arranged in a matrix, and among the large number of light receiving portions, the light receiving portions arranged in the column direction are received. A plurality of vertical registers (not shown) that are common to all the parts are arranged in the row direction, and the image part 1 is arranged adjacent to the image part 1 and formed in the image part 1. In the so-called frame interline transfer (FIT), there is no light receiving unit and the storage unit 2 is formed by extending a plurality of vertical registers (not shown) in succession to the plurality of vertical registers in the image unit 1. ) Type image sensor.

In this image sensor IS, as shown in FIG. 4, a P-type well region 12 is formed on an N-type silicon substrate 11, and an N-type well region 12 serving as a charge transfer path is formed on the surface of the well region 12. Embedded channel region 13 is formed. In plan view, as shown in FIG. 3, a large number of vertical columns adjacent to the storage unit 2 and separated in the row direction by a large number of channel stopper regions 14 (shown by diagonal lines). Two horizontal registers that are common to the register 15 are arranged side by side. Of the two horizontal registers, the horizontal register located on the storage unit 2 side is the first horizontal register H1 and the other horizontal registers are the second horizontal register H2.
Is written.

Then, as shown in FIG. 4, between the storage unit 2 and the first horizontal register H1, the signal charges transferred to the final stage of the vertical register 15 in the storage unit 2 are transferred to the first horizontal register H1. Two vertical-horizontal transfer areas (hereinafter referred to as the first and second VH transfer areas 1 for transfer).
6a and 16b) are formed in common for a plurality of vertical registers 15 and in parallel with each other.

In this embodiment, as shown in FIG. 4, the first horizontal register H1 to the second horizontal register H
N-type deep buried channel region 1 by high-energy ion implantation under buried channel region 13 extending over 2
7 is formed, and the potential distribution under the first and second horizontal registers H1 and H2 in the electrically neutral state is set to be deeper than the vertical register 15 by a depth h. In addition, the first and second VH transfer areas 16
P-type impurity diffusion regions 18a and 18b are formed under a and 16b by high-energy ion implantation of selective P-type impurities (for example, boron (B)),
The potential distributions in the first and second VH transfer regions are set to have a downward slope toward the first horizontal register H1.

The P-type impurity diffusion regions 18a and 18
As a method of forming b, the P-type impurity concentration is formed so as to be continuously thin in the charge transfer direction. That is, when viewed from the impurity concentration of the horizontal registers H1 and H2, the N-type impurity concentration under each VH transfer electrode 16a and 16b is formed to be higher in the signal charge transfer direction.

Specifically, the P-type impurity diffusion region 1 in the first and second VH transfer regions 16a and 16b is used.
When 8a and 18b are viewed two-dimensionally, for example, as shown in FIG. 5, the vertical register 15 side has a base and the first horizontal register H1 side has a vertex as a triangular pattern.
In the figure, a right triangle pattern is shown. By forming the P-type impurity diffusion regions 18a and 18b in a triangular pattern in this manner, the concentration of P-type impurities on the vertical register 15 side in each VH transfer region 16a and 16b is high, and the first horizontal register is formed. The concentration distribution is such that the concentration of the P-type impurity gradually decreases toward the H1 side, and when a predetermined voltage is applied to the VH transfer electrodes VH1 and VH2 on each VH transfer region 16a and 16b, each V
The potentials of the H transfer regions 16a and 16b have a downward slope distribution toward the first horizontal register H1.

As another method, as shown in FIG. 6, the depth of the P-type impurity diffusion regions 18a and 18b on the vertical register 15 side is increased, and the depth is gradually increased toward the first horizontal register H1. So that
P-type impurities are introduced by, for example, oblique ion implantation, and the P-type impurity diffusion regions 18a and 18b are formed into a shape of a substantially right triangle having a bottom on the vertical register 15 side and an apex on the first horizontal register H1 side. May be formed.

On the other hand, as shown in FIG. 4, between the first and second horizontal registers H1 and H2, the signal charges once transferred to the first horizontal register H1 are selectively selected to the second horizontal register. Inter-register transfer area 19 for transfer to H2
Are formed. The inter-register transfer region 19 is composed of an N-type impurity diffusion region having a relatively high concentration, and is formed to extend laterally along the first and second horizontal registers H1 and H2. In the inter-register transfer area 19, as shown in FIG. 3, the transfer of the signal charges is stopped at a position corresponding to the vertical register 15 in, for example, an odd column (... 2n-3 column, 2n-1 column) of the vertical register 15. Channel / stopper regions CS are formed respectively.

On the vertical register in the image unit 1 and the vertical register in the storage unit 2, for example, 2
Of four vertical transfer electrodes ST1 made of polycrystalline silicon layers
To ST4 are respectively formed via the insulating film 20. That is, four vertical transfer electrodes ST1 to ST4 are set as one set, and a large number of the sets are sequentially arranged in the vertical direction. Then, each of the four vertical transfer electrodes ST1 to ST1
Four vertical transfer pulses φST1 to φST4 having different phases are supplied to ST4, respectively. By supplying these vertical transfer pulses φST1 to φST4, the first to fourth vertical transfer electrodes ST1 to ST4 are supplied. The lower potential distribution sequentially changes, whereby the signal charges are vertically transferred along the vertical registers 15.

In particular, in the image section 1, the signal charges accumulated in the light receiving section are first read out to the vertical register in the vertical blanking period, and then transferred to the vertical register in this vertical blanking period. The signal charges are transferred at high speed to the vertical register 15 of the storage unit 2.

The storage unit 2 transfers the signal charges transferred to the vertical register 15 in the vertical blanking period to the first horizontal register H1 in units of one row in the subsequent horizontal blanking period.
Transfer to the side. As a result, the signal charges in the final stage of the vertical register 15 are first transferred to the first horizontal register H1 via the two VH transfer regions 16a and 16b, and of them, for example, odd columns (... 2n-3 columns). , 2n-1
The signal charges relating to the (column) are blocked from being transferred to the second horizontal register H2 in the channel stopper region CS (see FIG. 3) formed in the inter-register transfer region 19, and the even columns (... 2n-4 columns, 2n). -2 columns, 2n columns) are transferred to the second horizontal register H2.

Then, in the next horizontal scanning period, the first
And two horizontal transfer pulses having different phases to the first horizontal transfer electrode GH1 and the second horizontal transfer electrode GH2, which are formed by, for example, two layers of polycrystalline silicon layers formed on the second horizontal registers H1 and H2. By applying φH1 and φH2, the signal charges are sequentially transferred to the output section 21 (see FIG. 1), combined in the output section 21, and taken out as the image pickup signal S from the output terminal φout.

First and second horizontal transfer electrodes GH1 and G
H2 is, as shown in FIG. 3, horizontal registers H1 and H2.
In the above, they are arranged alternately and in the lateral direction, and the shape thereof is as follows with respect to the first horizontal transfer electrode GH1.
On the first horizontal register H1, for example, the vertical register 1 for odd-numbered columns (... 2n-3 columns, 2n-1 columns)
5 is arranged at a position corresponding to 5, and on the way, on the register transfer area 19, even columns (... 2n-4 columns, 2n-2 columns, 2
It is bent to the side corresponding to the vertical register 15 for the (n columns) and is continuously arranged on the second horizontal register H2 at a position corresponding to the vertical register for the even columns.

The same applies to the second horizontal transfer electrode GH2. First, on the first horizontal register H1, even-numbered columns (...
n-4 columns, 2n-2 columns, 2n columns) are arranged at locations corresponding to the vertical registers 15 and, on the way, odd-numbered columns (... 2n-3 columns, 2n-1 columns) on the inter-register transfer area 19.
Is bent to the side corresponding to the vertical register 15 regarding the second horizontal register H2, and is continuously arranged on the second horizontal register H2 at a position corresponding to the vertical register 15 regarding the odd number column.

In the image sensor IS according to this embodiment, in order to improve the charge transfer efficiency between the first and second horizontal registers H1 and H2, as shown in FIG. The shape of the transfer electrode GH1 or GH2 formed on H1 is, for example, an inverted fan shape (divergent shape).
Or by continuously changing the concentration distribution of the impurity diffusion region forming the first horizontal register H1, the potential distribution in the first horizontal register H1 is inclined downward toward the inter-register transfer region 19. I am trying to become.

Here, the image section 1, the storage section 2, the first VH transfer area 16a, the second VH transfer area 16b, the first horizontal register H1, and the inter-register transfer area shown on the line AA in FIG. 19 and impurity diffusion regions of the second horizontal register H2, particularly the first VH transfer region 16a and the second VH transfer region 16a.
In the VH transfer area 16b, the first horizontal register H1, the inter-register transfer area 19 and the second horizontal register H2, each transfer formed on each impurity diffusion area along the line BB in FIG. Looking at the potential distribution of each impurity diffusion region when the same potential (for example, 0 V) is applied to the electrodes, as shown in FIG. 2, first, the range from the image portion 1 to the storage portion 2 is a flat distribution. There is.
Next-stage first and second VH transfer areas 16a and 16b
Has a distribution in which the potential in contact with each vertical register 15 is shallower than the potential of the storage unit 2, exists as a so-called potential barrier, and further has a distribution in which the potential continuously increases toward the first horizontal register H1. That is, each of the VH transfer regions 16a and 16b has a potential distribution that is inclined downward toward the first horizontal register H1. The first horizontal register H1 has a downwardly sloping distribution toward the second horizontal register H2, and the potential distribution of the first horizontal register H1 continues from the inter-register transfer area 19 to the second horizontal register H2. Has a flat distribution.

Here, the transfer state of the signal charges in the image sensor according to the present embodiment will be described with reference to the timing chart of FIG. 7 and an operation conceptual diagram showing potential changes under various transfer electrodes shown in FIGS. 8 and 9. explain. In addition,
In the figure, φST1 to φST4 are respectively the first to fourth
First to fourth supplied to the vertical transfer electrodes ST1 to ST4 of
Vertical transfer pulses of φVH1 and φVH2 are formed on the first and second VH transfer regions 16a and 16b.
And the first and second VH transfer pulses supplied to the second VH transfer electrodes VH1 and VH2, φH1 and φH2 are supplied to the first and second horizontal transfer electrodes GH1 and GH2, respectively. A horizontal transfer pulse, φHH, indicates an inter-register transfer pulse supplied to the inter-register transfer electrode HH formed on the inter-register transfer area 19. Further, the operation conceptual diagrams shown in FIGS. 8 and 9 show the transfer state of the signal charges relating to the odd columns and the transfer state relating to the even columns as a pair at each time.

The state at time t1, that is, the first and second vertical transfer electrodes ST1 in the storage section 2
Signal charges of the image sensor IS are transferred from the state where the signal charges are stored in the potential well formed continuously under ST2 and ST2 and the signal well is stored in the potential well formed below the first VH transfer electrode ST1. The state will be described.

First, at the next time t2, the third vertical transfer pulse φST3, the second VH transfer pulse φVH2, and the register-to-register transfer pulse φHH each become high level, and the first VH transfer pulse φVH1 becomes low level. Become.
The signal charges accumulated in the final stage of the storage unit 2 at time t1 are the first to third vertical transfer electrodes ST1 to ST1.
It is transferred and accumulated in the potential well formed continuously under ST3.

At this time, the first VH transfer electrode VH
Since the potential under 1 becomes shallower and at the same time the potential under the second VH transfer electrode VH2 becomes deeper,
And under the second VH transfer electrodes VH1 and VH2,
A downward staircase-shaped potential distribution is formed toward the first horizontal register H1 side, and each VH transfer electrode VH
The potential distribution under 1 and VH2 is continuously inclined downward toward the first horizontal register H1 side, and the first horizontal register H1 is set low between the vertical register 15 and the first horizontal register H1. Potential step h (Fig. 2
(Refer to FIG. 4), the first
Signal charges e accumulated under the VH transfer electrode VH1 of
Will be transferred at high speed to the first horizontal register H1 side.

Further, the potential distribution of the first horizontal register H1 is inclined downward toward the second horizontal register H2 in consideration of high-speed transfer, and further below the inter-register transfer electrodes HH for even columns. Since the potential is deep, the signal charges relating to the even-numbered columns are eventually transferred at a high speed from below the first VH transfer electrode VH1 to below the inter-register transfer electrode HH. On the other hand, the transfer of the signal charges e relating to the odd-numbered columns is blocked by the channel stopper region CS formed in the inter-register transfer region 19.

That is, in this embodiment, at the time t2, the final stage of the vertical register 15 (to be exact, the first VH
The signal charge e is transferred from the transfer electrode VH1) to the inter-register transfer electrode HH.

Then, at the next time t3, the first vertical transfer pulse φST1 and the second VH transfer pulse φVH2.
Becomes the low level, and the fourth vertical transfer pulse φS
Since T4 becomes high level, the signal charge e is applied to the second to fourth vertical transfer electrodes S in the final stage of the storage unit 2.
It is transferred and accumulated in the potential well formed continuously under T2 to ST4. At this time, the signal charge e transferred under the inter-register transfer electrode HH remains stored under the inter-register transfer electrode HH.

At the next time t4, since the state at the time t3 is still held, the signal charge e in the final stage of the vertical register 15 is still below the second to fourth vertical transfer electrodes ST2 to ST4. It remains accumulated in the continuously formed potential well. In addition, the inter-register transfer electrode H
The signal charge e transferred below H is also transferred to the inter-register transfer electrode H.
It remains accumulated under H.

Then, at the next time t5, the second vertical transfer pulse φST2 becomes low level and the first VH transfer pulse φVH1 becomes high level, so that the signal charge e becomes the first charge in the final stage of the storage section 2. Data is transferred and accumulated in the potential well formed continuously under the third and fourth vertical transfer electrodes ST3 and ST4. At this time, the signal charge e transferred under the inter-register transfer electrode HH remains stored under the inter-register transfer electrode HH.

At the next time t6, since the first vertical transfer pulse φST1 becomes high level, the storage unit 2
Of the signal charge e in the stage before the final stage of the first transfer electrode S
Will be transferred under T1. At this time, the signal charge e at the final stage of the storage unit 2 remains accumulated in the potential well formed continuously under the third and fourth vertical transfer electrodes ST3 and ST4, and also under the inter-register transfer electrode HH. The signal charge e is still accumulated.

At the next time t7, since the third vertical transfer pulse φST3 becomes low level, the signal charge e at the final stage is under the fourth vertical transfer electrode ST4 and the first VH transfer electrode VH1. It will be transferred and accumulated in the continuously formed potential wells. At this time, since the first horizontal transfer pulse φH1 simultaneously becomes high level, the potential under the horizontal register H1 relating to the odd-numbered columns becomes deep in the first horizontal register H1, and the second horizontal register H2 becomes Horizontal register H2 for even columns
The lower potential becomes deeper. As a result, the transfer of the signal charges e related to the odd columns remains blocked in the channel stopper region CS formed in the inter-register transfer region 19, and the transfer of the signals charges e related to the even columns between the registers. It is transferred and accumulated in the potential well formed continuously under the electrode HH and under the second horizontal register H2.

At the next time t8, since the second vertical transfer pulse φST2 becomes high level, the signal charge e in the previous stage of the final stage is continuously formed under the first and second vertical transfer electrodes ST1 and ST2. Will be transferred and accumulated in the potential wells. At this time, there is no potential change in the first and second horizontal transfer pulses φH1 and φH2 and the register-to-register transfer pulse φHH, so the state at t7 is still maintained.

At the next time t9, since the fourth vertical transfer pulse φST4 and the register-to-register transfer pulse φHH are at low levels, the signal charge e at the final stage is the first
VH transfer electrode VH1 is transferred to and accumulated in a potential well formed under. At this time, the inter-register transfer electrode H
Since the potential under H becomes shallow, the signal charge e relating to the even column under the inter-register transfer electrode HH is completely transferred to the potential well of the second horizontal register H2.
As a result, the signal charges e related to the odd-numbered columns are distributed to the first horizontal register H1 and the signal charges e related to the even-numbered columns are distributed to the second horizontal register H2.

As described above, in the image sensor IS according to the present embodiment, the first and second VH transfer areas 16a and 16b between the final stage of the vertical register 15 and the first horizontal register H1 are first and second. Second VH transfer electrode V
H1 and VH2, and these transfer electrodes VH1 and VH
Since the potential distribution under 2 is inclined downward toward the first horizontal register H1 side, the signal charge e transferred to the final stage of the vertical register 15 can be transferred to the first horizontal register H1 side at high speed. This makes it possible to transfer charges between the plurality of horizontal registers H1 and H2 at high speed.

Further, the vertical register 1 in an electrically neutral state
By making the potential distribution under 5 smaller than that of the first horizontal register H1, it is possible to prevent the occurrence of a fringing electric field that occurs between the vertical register 15 and the first horizontal register H1. The signal charge e can be transferred to the first horizontal register H1 side without causing a reduction in the maximum handled charge amount transferred in.

Further, as indicated by t1 to t2 in FIG.
When transferring the signal charge e at the final stage of the vertical register 15 to the first horizontal register H1 side, first and second VH transfer pulses φV supplied to the VH transfer electrodes VH1 and VH2 are transferred.
By using H1 and VH2 as alternating pulses, it is possible to prevent the generation of a fringing electric field between the first and second VH transfer electrodes VH1 and VH2, and moreover, the potential distribution under each VH transfer electrode VH1 and VH2. Has a downward slope toward the first horizontal register H1 side, the signal charge e transferred to the final stage of the vertical register 15 can be transferred at high speed and without causing transfer residue.

Moreover, as can be seen from the timing chart of FIG. 7, at the time t2, the first VH transfer electrode V
Since the signal charge e under H1 can be transferred to below the inter-register transfer electrode HH, the signal charge e at the final stage of the storage unit 2 is transferred to the first VH transfer electrode VH1 under the initial period. Long time until t5 (3 times longer than before)
Therefore, the above period does not start before the transfer of the signal charge e is completed. As a result, inconveniences such as transfer residue do not occur, and the efficiency of transfer between registers can be effectively improved. That is, the vertical register 15
Of the signal charge e in the final stage of the horizontal registers H1 and H2
It is possible to lengthen the charge transfer time until the transfer to the transfer region between them, improve the transfer efficiency between the horizontal registers H1 and H2, and significantly reduce the vertical streak defect rate.

In the above embodiment, the example applied to the frame / interline transfer system is shown, but the invention can also be applied to other image sensors of the interline transfer system.

[0069]

As described above, according to the solid-state image pickup device of the present invention, a large number of light receiving portions for photoelectrically converting into an amount of electric charge according to the amount of incident light are arranged in a matrix, and among these many light receiving portions. , A number of vertical registers that are common to the light receiving portions arranged in the column direction are arranged in the row direction,
In a solid-state imaging device in which a plurality of horizontal registers common to a plurality of vertical registers arranged in the row direction are arranged, two solid registers are provided on a transfer area between the final stage of the vertical registers and the horizontal register. Since the potential distribution under the transfer electrodes is inclined downward toward the horizontal register side, the signal charges in the final stage of the vertical register are transferred to the transfer region between the horizontal registers. It is possible to take a long time to transfer the electric charges, to improve the transfer efficiency between the horizontal registers, and to significantly reduce the vertical streak defect rate.

[Brief description of drawings]

FIG. 1 is a plan view showing a schematic configuration of an embodiment (hereinafter, simply referred to as an image sensor according to the embodiment) in which a solid-state image sensor according to the present invention is applied to a so-called frame / interline transfer type image sensor.

FIG. 2 is a line AA in FIG. 1 and B in FIG.
FIG. 9 is a diagram showing potential distributions under various transfer electrodes when the same potential is applied to the various transfer electrodes when viewed in a cross section on the −B line.

FIG. 3 is a plan view showing a configuration of a main part of the image sensor according to the present embodiment, particularly a part from a final stage of vertical registers to a second horizontal register in a storage part.

4 is a sectional view taken along line BB in FIG.

5A and 5B are first and second image sensors according to the present embodiment.
FIG. 5 is a plan view of a main part showing a formation pattern of a P-type impurity diffusion region formed by introducing a P-type impurity under the VH transfer region of FIG.

FIG. 6 is a first and second image sensor according to the present embodiment.
FIG. 9 is a cross-sectional view of a main part showing another formation pattern of a P-type impurity diffusion region formed by introducing a P-type impurity under the VH transfer region of FIG.

FIG. 7 is a timing chart showing output timings of transfer pulses supplied to various transfer electrodes of the image sensor according to the present embodiment.

8 is a timing chart from t1 to t in FIG.
It is an operation conceptual diagram which shows the transfer state of the signal charge accompanying the change of the potential under various transfer electrodes at 5 o'clock.

9 is a timing chart from t6 to t in FIG.
It is an operation conceptual diagram which shows the transfer state of the signal charge accompanying the change of the potential under various transfer electrodes at 9 o'clock.

FIG. 10 is a plan view showing a schematic configuration of an image sensor according to a conventional example.

FIG. 11 is a diagram showing potential distributions under various transfer electrodes when the same potential is applied to the various transfer electrodes when viewed in a cross section taken along the line CC in FIG.

FIG. 12 is a plan view showing a configuration of a main part of the image sensor according to the present embodiment, in particular, a part from the final stage of the vertical register to the second horizontal register in the storage part.

FIG. 13 is a timing chart showing output timings of transfer pulses supplied to various transfer electrodes of an image sensor according to a conventional example.

14 is a timing chart t1 of FIG.
FIG. 9 is an operation conceptual diagram showing a transfer state of signal charges accompanying a change in potential under various transfer electrodes at time t5.

15 is a timing chart t6 of FIG.
FIG. 11 is an operation conceptual diagram showing a transfer state of signal charges accompanying a change in potential under various transfer electrodes at to t9.

[Explanation of symbols]

 IS image sensor 1 image part 2 storage part 11 silicon substrate 12 P-type well region 13 buried channel region 14 channel stopper region 15 vertical register 16a and 16b first and second VH transfer region 17 deep buried channel regions 18a and 18b P-type impurity diffusion region CS channel stopper region ST1 to ST4 First to fourth vertical transfer electrodes VH1 and VH2 First and second VH transfer electrodes GH1 and GH2 First and second horizontal transfer electrodes φST1 to φST4 First to fourth vertical transfer pulses φVH1 and φVH2 First and second VH transfer pulses φGH1 and φGH2 First and second horizontal transfer pulses

Claims (3)

[Claims] 1. A large number of light receiving portions for photoelectrically converting into an amount of electric charge according to the amount of incident light are arranged in a matrix, and among these large numbers of light receiving portions, the light receiving portions arranged in the column direction are common. In the solid-state image sensor in which a plurality of vertical registers are arranged in the row direction, and a plurality of horizontal registers common to the plurality of vertical registers arranged in the row direction are arranged, A solid-state imaging device, comprising two transfer electrodes on a transfer region between a stage and the horizontal register, and a potential distribution under the transfer electrodes is inclined downward toward the horizontal register. 2. The solid-state imaging device according to claim 1, wherein a potential distribution under the vertical register in an electrically neutral state is shallower than that of the horizontal register. 3. The solid according to claim 1, wherein the drive pulse supplied to each transfer electrode is an alternating pulse when the electric charge at the final stage of the vertical register is transferred to the horizontal register side. Image sensor.