JPH08123728A - Memory content update circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable the memory contents of the data storage memory in a digital signal processing device to be updated without fail by simple programming. [Structure] The C-BUS 10 has a coefficient memory (C-ME
M) 16, a general-purpose memory (G-RAM) 20, an arithmetic logic operation unit (ALU) 26, and a product-sum operation unit (MA).
C) 28, a program memory (P-MEM) 32,
The host interface circuit (HOST-IF) 34 is connected. Host interface circuit (HOST
-IF) 34 is an interface circuit for exchanging programs and data between the DSP and the host coat roller 36, and includes a timing control unit, a data receiving unit, a buffer memory, a data transmitting unit, etc. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory content updating circuit in a digital signal processing device.

[0002]

2. Description of the Related Art Conventionally, DSP (D) has been used for digital signal processing such as digital filter, digital automatic equalization, fast Fourier transform (FFT), etc.
igitalSignal Processor) is used. In general,
The DSP has a high-speed multiplier, an adder, a program memory, a data memory, and the like to realize high-speed multiply-accumulate operation processing, and is a microprocessor of microprogram control type or PLA control type capable of pipeline processing. Is configured as. Recently, DSPs for specific applications such as sound processing, image processing, and communication are becoming popular.

Such a special-purpose DSP is manufactured as a one-chip semiconductor integrated circuit, and the memory capacity of each memory in the system is minimized in order to reduce the system / chip cost as much as possible. . Then, for the program memory for storing the program and the coefficient memory for storing the coefficient data whose value is fixed among the data, the required program and the coefficient data are downloaded from the host controller at any time.

FIG. 10 shows a configuration of a main part of a conventional DSP having a function of updating the memory contents of a coefficient memory and a program memory. The coefficient memory 100 for storing coefficient data and the program memory 102 for storing program data are each connected to an internal bus 104. An interface circuit 106 for exchanging programs and data between the DSP and the host controller 120 is also connected to the internal bus 104.

In the interface circuit 106,
A reception register 108 for receiving data from the host controller 120, a buffer memory 110 for storing a group of new coefficient data C0, C1, ... CN used for updating, and a group of new coefficient data C0, C1, ...
Address information SA representing the memory address in the coefficient memory 100 in which the first coefficient data C0 in CN is to be written
And an update start address register 112 for holding A group of new coefficient data C0, C1, ... CN for updating and update start address information SA
Are sent together from the host controller 120 and stored in the buffer memory 110 and the update start address register 112 from the reception buffer 108, respectively.

The DSP is provided with a coefficient update controller 114 including a logic circuit for updating the memory contents (coefficient data) of the coefficient memory 100. The coefficient update control unit 114 includes an interface circuit 106.
The contents of the start address register 112 (update start address information SA) are given. On the other hand, the read address generated by the memory address circuit 116 during the memory access for reading the coefficient memory 100 is also given to the coefficient update control unit 114. The coefficient update control unit 114 determines that the instruction of the currently executed program is the coefficient memory 100.
From the memory address circuit 116, a function of comparing the read address from the memory address circuit 116 with the update start address information SA to determine whether they match, and an interface The buffer memory 110 of the circuit 106 has a function of reading coefficient data.

A group of new coefficient data C0 for updating,
When C1, ... CN are stored in the buffer memory 110 and the instruction of the program being executed is an instruction for reading data from the coefficient memory 100, and the read address matches the update start address information SA, The coefficient data C0 at the head is read from the buffer memory 110 of the interface circuit 106. The read coefficient data C0 is transferred via the internal bus 104 to the destination specified by the instruction (for example, an arithmetic unit not shown) and is also sent to the coefficient memory 100 to be specified by the read address. Is written to the memory address. In this way, the memory content (coefficient data) is updated at the memory address in the coefficient memory 100 designated by the update start address information.

Thereafter, when data is to be read from the coefficient memory 100 again, the next coefficient data C1 is read from the buffer memory 110 of the interface circuit 106.
Is read out and its coefficient data C1 is read in the same manner as above.
Is sent to a predetermined data transfer destination and is written in the memory address in the coefficient memory 100 designated by the read address of the instruction. After that, the same operation is repeated until all the coefficient data in the buffer memory 110 are empty (updated).

In this DSP, the program memory 10
The memory contents (program) of No. 2 are updated by downloading a new program from the host controller 120. A predetermined control signal from the host controller 120 is given to the control device 118 via the interface circuit 106 to switch to the program download mode. When the program is switched to the program download mode, the program that was being executed is interrupted, and after the system is reset, the series of program data from the host controller 120 is transferred to the interface circuit 106 and the internal bus 1.
It is transferred (downloaded) to the program memory 102 via 04.

[0010]

As described above, in the conventional DSP, the coefficient data C0 in the buffer memory 110 of the interface circuit 106 from the time when the read address for the coefficient memory 100 matches the update start address information SA. A predetermined flag is set until the C1, ..., CN are all empty (updated), and the coefficient memory update mode is set. During this mode, the buffer memory 110 outputs a predetermined order every time a read command is issued to the coefficient memory 100. One coefficient data Ci is read out at the same time, and the read coefficient data Ci is used in the read command and simultaneously written into the memory address in the coefficient memory 100 designated by the read address. .

In such a coefficient data updating method, the order of the read command to the coefficient memory 100 in the coefficient memory updating mode is such that the coefficient data C0,
It must correspond to the order of C1, ... CN. Otherwise, the access destination (memory address) of the read instruction for the coefficient memory 100 and the buffer memory 110
The write destination (the memory address to be updated) of the coefficient data Ci to be read from does not match, and the execution process of the instruction and the update of the memory content of the coefficient memory 100 are erroneous.

However, the fact that the order of the read instructions is completely restricted by the order of updating the coefficient data or the order of the memory addresses to be updated makes the coding of the program difficult and becomes a bottleneck in the program development. . Moreover, even if the order of the read instructions is carefully matched with the update order of the coefficient data at the coding stage, an interrupt request is generated during the coefficient memory update mode at the program execution stage, and the coefficient memory 100 is requested during the interrupt process. When the memory access for reading is performed, the order of the instructions does not match the update order of the coefficient data from that point on time, and as a result, the instruction execution process and the coefficient memory update process are mistaken.

Further, in order to update the memory contents (program) of the program memory 102, in the conventional DSP,
As described above, the download from the host controller 120 is performed again. However, switching to the program download mode has a disadvantage that the execution of the program is stopped and the DSP processing (sound processing, image processing, etc.) is interrupted.

In a general-purpose DSP, a program memory having a relatively large memory capacity can be built in, or an auxiliary memory for a program can be added to the outside, so that a sufficient program area can be obtained and a necessary amount can be provided from the beginning. It is possible to write the program in the program memory in advance, and thus it is often unnecessary to rewrite (update) the program. On the other hand, in the dedicated DSP for a specific application as described above, the system / chip cost is kept as low as possible.
In most cases, it is not possible to even add an auxiliary memory for programs to the outside, and how well a limited program area (for example, 256 to 512 words) in the internal memory is used effectively affects the processing performance. However, like the conventional DSP described above, if the process being executed is stopped every time the program is rewritten (updated), the processing performance of the DSP is significantly reduced.

The present invention has been made in view of the above problems of the prior art. That is, a first object of the present invention is to provide a memory content updating circuit capable of surely updating the memory content of a data storage memory in a digital signal processing device by simple programming.

A second object of the present invention is to provide a memory content updating circuit capable of updating the memory content of the program storage memory in the digital signal processing device at an arbitrary memory address without stopping the execution of the program. To provide.

[0017]

In order to achieve the first object, the first memory content updating circuit of the present invention is arranged such that the memory content of the data storage memory in the digital signal processing device is transferred from an external control device. In the memory content updating circuit for updating in response to the request, the external control device receives address information indicating each memory address in the memory for data updating and new data for updating. Receiving means for receiving, buffer memory for storing the address information received by the receiving means and new data for updating, and arbitrary data from the data storing memory in the digital signal processing device. The address information generated for reading is compared with the address information stored in the buffer memory to determine whether or not there is a match. When the result of collation coincidence is obtained from the address collation unit and the address collation unit, the execution cycle of the instruction is interrupted, and new data for updating corresponding to the address information of the collation coincidence is obtained. The data operation means reads the data from the buffer memory, sends the read data to the destination specified by the instruction, and writes the data to the memory address in the data storage memory specified by the address information.

Further, in order to achieve the above second object,
A second memory content updating circuit of the present invention is a memory content updating circuit for updating the memory content of a program storing memory in a digital signal processing device in response to a request from an external control device. Address information storage means for storing in advance address information indicating a memory address to be updated in the memory; receiving means for receiving new program data for update transmitted from the external control device; Buffer means for holding the new program data for updating received by the receiving means, interrupt generating means for generating a predetermined interrupt request for updating, and address information storage in response to the interrupt request Reading the address information from the means,
An interrupt processing means for transferring the new program data for the update held in the buffer means to a memory address in the program storage memory designated by the read address information is provided.

Further, a third memory content updating circuit of the present invention is such that, in the second memory content updating circuit, the address information read from the address information storage means is incremented or decremented by a predetermined value. It is configured to have address calculation means and address writing means for writing new address information obtained by the address calculation means into the address information storage means.

[0020]

In the first memory content updating circuit of the present invention, address information (update address information) indicating each write destination (memory address to be updated) is written in the buffer memory together with new data for updating. ) Also set (memory)
To be done. The address collating means compares the read address directed to a predetermined data storage memory with each update address to determine whether or not they match. Then, when a comparison match is obtained, the data operation means operates to read the data corresponding to the updated address information from the buffer memory and send it to the destination specified by the instruction,
It is also sent to the data storage memory and written in the memory address specified by the update address information.

In the second memory content updating circuit of the present invention,
Address information representing a memory address to be updated in the program storage memory is set (stored) in advance in the address information storage means. When new program data for updating from the external control device is received by the receiving means, the interrupt generating means issues a predetermined interrupt request, whereby the interrupt processing means operates. In this interrupt processing, the address information is read from the address information storage means, and the program data from the reception means is transferred to the memory address in the program storage memory designated by the address information.

In the third memory content updating circuit of the present invention,
In the second memory content update circuit, the address information read from the address information storage means is converted into address information representing the memory address to be updated next by the address calculation means. Then, this new address information is written in the address information storage means by the address writing means.

[0023]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows a system configuration of an audio / digital signal processing DSP according to an embodiment of the present invention. This DSP system has, for example, three independent data buses (C-BUS10, D-BUS12, G-BUS1) each having a data bus width of 24 bits.
4) and each part is connected to these buses as shown in the figure.

The C-BUS 10 has a coefficient memory (C-M
EM) 16, general-purpose memory (G-MEM) 20, arithmetic logic operation unit (ALU) 26, and product-sum operation unit (MA)
C) 28, a program memory (P-MEM) 32,
The host interface circuit (HOST-IF) 34 is connected.

The D-BUS 12 has a data memory (D-
MEM) 18, general-purpose memory (G-MEM) 20, and external memory input / output interface circuit (EX-IF) 22
And an audio interface circuit (AU-IF) 2
4, an arithmetic logic operation unit (ALU) 26, and a product-sum operation unit (MAC) 28 are connected.

The G-BUS 14 includes a general-purpose memory (GM
EM) 20, external memory input / output interface circuit (EX-IF) 22, arithmetic logic unit (AL)
U) 26 is connected.

C-MEM16, D-MEM18, GM
The EM 20 is an SRAM (Static Randam Access Memor) having a memory capacity of 256 × 24 bits, for example.
y). The C-MEM 16 mainly stores coefficient data for sum-of-products calculation, and EX-IF2
Address information for accessing an external memory (not shown) connected to the memory 2 is also stored. D-MEM18
Stores data (mainly audio data) used for product-sum calculation and other calculations and data of calculation results.

The G-MEM 20 is usually the D-MEM 18
Used as extended memory. When handling a large amount of delay data such as sound field reproduction, the delay data that cannot be stored in the D-MEM 18 is accumulated in the external memory composed of RAM, and a predetermined command (background external memory read command) is stored when necessary. Delay data from external memory by G
-Incorporated in MEM20. In this case, G
The MEM 20 also stores address information for accessing the external memory. In addition, G-MEM20 is C
-It can also be used as an expansion memory of the MEM 16, and may store coefficient data as needed.

C-MEM16, D-MEM18 and G
The MEM 20 is provided with addressing units 17, 19 and 21 for performing address calculation, respectively.

The EX-IF 22 is also connected to the external memory for accumulating the delayed data, and has a memory control function capable of accessing the external memory to write or read data, and stores address information for memory access. It has an address register to hold and a data register to hold write or read data.

The AU-IF 24 is an interface circuit for exchanging data between the DSP and an external digital audio circuit.
D playback circuit, next stage digital filter or D / A
It is connected to a converter etc. When an audio signal (data) is input from an external circuit, the AU-IF24
When one piece of data is stored in the internal register, an interrupt is issued to the control device 30 which will be described later, and the data is D
-It is designed to be stored in the D-MEM 18 through the BUS 12.

The ALU 26 is an arithmetic unit for performing arbitrary arithmetic operations and logical operations, and also has an accumulator built therein. The MAC 28 is an arithmetic unit that exclusively performs sum-of-products arithmetic,
It has a built-in multiplier and accumulator. 2 like this
Since one arithmetic unit (ALU26, MAC28) is provided, MAC is performed while adding with the ALU26, for example.
Parallel processing such as convolution with 28 is possible.

The P-MEM 32 is, for example, 512 × 32.
SRAM (Static Randam) with a bit memory capacity
Access Memory) and stores a program that defines the processing operation of the DSP. The control circuit 30 is a P-MEM
The instruction code is sequentially read out from 32 and PLA (Program
It functions to control the registers and gates (not shown) in the system by the Logic Array method and cause each unit to execute the instruction. The control bus is not shown in FIG. 1 for convenience of description.

The HOST-IF 34 is an interface circuit for exchanging data and control signals between the DSP and the host controller 36, and the C-BUS 1
0, D-BUS 12 are connected by a parallel port, and the host controller 36 is connected by a serial port. Program data stored in the P-MEM 32,
The coefficient data and the address information stored in the C-MEM 16 and the address information stored in the G-MEM 20 are given from the host controller 36, and the HOST-IF 3
4 through C-BUS 10 to each memory.

As shown in FIG. 2, the HOST-IF34
Is composed of a timing control unit 40, a data receiving unit 42, a C-MEM update buffer 44, and a data transmitting unit 46.

The timing control unit 40, for example a plurality of external signal input pins CS, as defined in the table of FIG. _{3 -, HRBCK, HRS, HXBCK} , HXS, H
It has BCKS and HDIR, and is configured to input a predetermined control signal from the host controller 36 to these input pins to control the operation timing of each unit in the HOST-IF 34.

The data receiving unit 42 is, for example, shown in FIG.
As shown in FIG. 1, it is composed of one serial input parallel output shift register SHR (8 bits), one host interface mode register HIM (8 bits), and five reception registers HR4 to HR0. ing. The input terminal of the shift register SHR is connected to the signal input pin HR for inputting the serial data from the host controller 36 as defined in the table of FIG.

Chip select signal CS provided from the host controller 36 to the timing control unit 40
_- it is then changed from the high level to a low level, the first byte of data (mode selection data) is written to the host interface mode register HIM, HO
The ST-IF 34 reception or transmission mode is selected. This mode register HIM is also used by the host controller 36 as shown in the table of FIG.
It is used for interrupt requests from the computer and control of program execution start timing after downloading.

The data sent from the host controller 36 following the mode selection data passes through the receiving registers HR4 to HR0 according to the selected mode and the control unit 3
Control registers in 0 (CR3-0), PM
C-MEM update buffer 44 (CUADR, CUBU in EM32, C-MEM16 or HOST-IF34)
F).

FIG. 6 shows the configuration of the C-MEM update buffer 44. The C-MEM update buffer 44 is a C-MEM.
Address buffer CUADR for storing address information (for example, 9 bits) representing each memory address in 16 to be updated, and a coefficient for storing new coefficient data (for example, 24 bits) used for updating It is composed of a data buffer CUBUF. For example, the address buffer CUADR has (n + 1) (for example, 16) 9-bit registers CUADR (0) ...
It is configured as a FIFO (first in, first out) type memory consisting of CUADR (n) and has a coefficient data buffer CUBUF.
Also a FIFO consisting of (n + 1) (eg 16) 24-bit registers CUBUF (0) to CUBUF (n)
It is configured as a (first in, first out) type memory.

The concept of the FIFO in this embodiment includes not only the physical first-in first-out method but also the first-in first-out method in a logical sense that determines the order of inserting and the order of outputting using a flag, for example.

FIG. 6 also shows an address comparator 50 and a coefficient update control circuit 52 which are normally provided outside the HOST-IF 34. Address buffer CUADR
Is connected to one input terminal of the address comparator 50, and the group of address information for updating stored in the registers CUADR (0) to CUADR (n) is input to the address comparator 50 one by one in order. It is supposed to be done. Read address information for the C-MEM 16 generated by the addressing unit 17 is input to the other input terminal of the address comparator 50.

The address comparator 50 compares the address information input to both input terminals and outputs a comparison output signal CP indicating whether or not they match. The comparison output signal CP from the address comparator 50 is input to the coefficient update control circuit 52. The coefficient update control circuit 52 includes the control device 30.
A read request signal and a write request signal for the C-MEM 16 generated by the above are also input.

An instruction during program execution is C-MEM
In the case of reading data from 16, the controller 30 gives a read request signal to the coefficient update control circuit 52. On the other hand, the read address information from the addressing unit 17 is given to the comparator 50. If the address buffer CUADR is not empty, that is, if unused update address information remains in at least one of the registers CUADR (0) to CUADR (n), the highest rank of them The updated address information of the above is given to the comparator 50. If the read address information matches the updated address information, the comparator 50
A comparison output signal CO representing comparison match is output.

In this case, the coefficient update control circuit 52 takes the logic of the read request signal from the control device 30 and the comparison output signal CP from the comparator 50, and controls the C-MEM 16 not to read it but to write it. Send a signal. At the same time, the coefficient update control circuit 52 gives a control signal to the coefficient data buffer CUBUF to read the coefficient data corresponding to the update address information which has been compared and matched this time. The coefficient data read from the coefficient data buffer CUBUF is sent to the destination specified by the read command through the C-BUS 10 and at the same time the C-MEM 1
Also sent to 6. Address information from the addressing unit 17 and a write control signal from the coefficient update control circuit 52 are also sent to the C-MEM 16, and the coefficient data from the coefficient data buffer CUBUF is designated by the address information. It is written in the memory address.

In this way, the C of the HOST-IF34 is
The above operation is performed each time a read command is issued to the C-MEM 16 until the address information for update and the new coefficient data stored in the MEM update buffer 44 become empty (used), and the read address. When the information matches the updated address information, new coefficient data corresponding to the updated address information is read from the C-MEM update buffer 44, and the read coefficient data is used in the read instruction. C-ME specified by the read address information (that is, updated address information)
The data is written in the memory address of M16.
When the address information and the new coefficient data for updating in the C-MEM update buffer 44 is all empty (used), the empty flag EMPTY _- becomes the low level, the update to the host controller 36 has been completed Let me know.

FIG. 7 shows a host controller 36 and HOST-I for updating the memory contents in the C-MEM 16.
The format of communication with F34 is shown. For example, to change the filter characteristics according to the sound quality adjustment of the reproduced sound, C
-When it is necessary to partially update the memory contents (coefficient data) in the MEM 16, the host controller 36
For OST-IF34, chip select signal CS _-
To the enable state (low level) and then C-
Mode selection data for instructing the MEM update mode is first transmitted, and then address information for update and new coefficient data for each one word are required (for example, n.
Send only word).

The mode selection data is sent to the controller 30 via the host interface mode register HIM of the data receiving unit 42, as described above. Further, each update address information is stored in each address register CUADR (i) of the address buffer CUADR of the C-MEM update buffer 44 via the receiving registers HR4 and HR3 of the data receiving unit 42. Further, each new coefficient data is stored in each coefficient data buffer CUBUF (i) of the C-MEM update buffer 44 via the receiving registers HR2, HR1, HR0 of the data receiving unit 42.

In FIG. 7, when the mode selection data is written in the host interface mode register HIM, even if some unused coefficient data remains in the C-MEM update buffer 44 at that time, all the registers in the buffer 44 will remain. There are clear, empty flag eMPTY _-
Is forced to low level (write enabled state). Then, the address information for updating the first set and the new coefficient data are respectively received by the receiving registers (HR4, HR3).
), (HR2, HR1, when transferred from HR0) to C-MEM address buffer CUADR (0 update buffer 44) and the coefficient data buffer CUBUF (0), empty flag at that time EMPTY _- is high Become a level.

Upon completion of transmission of the required update address information and new coefficient data, the host controller 36
The chip select signal to the DSP CS _- disabling state (high level) to. with this,
The update operation for the memory contents of the C-MEM 16 enters the standby state. However, while CS _- is at the high level, the empty flag EMPTY _- is at the high impedance level (Hi-z).

As described above, in the DSP of this embodiment,
In the C-MEM update buffer 44 of the HOST-IF 34,
A group of coefficient data for updating is stored together with the address information of each writing destination. And C-MEM
Each time a read command for 16 is performed, each update address information is compared with the read address information, and if the two match, the C-MEM designated by the address information.
The memory contents (coefficient data) are updated at the memory address in 16.

Therefore, for example, even if the memory information other than the update target in the C-MEM 16 is accessed for reading after the address information for updating the first set and the new coefficient data are used for updating. , The address comparator 50 does not output the comparison output signal CP for comparison and coincidence, so that the update operation is not activated and the read command is executed as it is. Then, the execution instruction of the program becomes a stage for performing read memory access to the memory address in the C-MEM 16 specified by the second set of update address information,
The address comparator 50 outputs the comparison output signal CP indicating comparison and coincidence, and at this time, the update operation relating to the second set of coefficient data is performed.

As a result, even if a program execution instruction, particularly a read instruction for the C-MEM 16, accesses a memory address other than the update target during the coefficient memory update mode,
There is no risk that wrong instruction execution processing and update processing will be performed. Therefore, the coding of the program is not restricted due to the update of the C-MEM 16, and the software development efficiency is improved. Further, even if an interrupt occurs during the coefficient memory update mode, there is no risk of erroneous instruction execution processing and update processing, so system reliability can be improved.

In this embodiment, the unused update address information in the C-MEM update buffer 44 is supplied to the address comparator 50 one by one in order. Therefore, there is only one piece of update address information that is compared with the read address information for the C-MEM 16, and
The coefficient data to be read from the EM update buffer 44 is fixed. In normal digital signal processing, the order of use (that is, the order of reading from the C-MEM 16) in a group of coefficient data is fixed, so that C-MEM is used.
Almost no problem arises when prioritizing a group of address information for updating stored in the update buffer 44 and new coefficient data.

However, although the circuit configuration becomes complicated, the C-MEM update buffer 4 is not assigned such a priority order.
All the unused update address information in 4 are set to C-MEM1.
If there is a match with the read address information for No. 6, the coefficient data corresponding to the matched update address information can be read from the C-MEM update buffer 44.

The memory contents to be updated in the C-MEM 16 are not limited to the coefficient data, and address information and other arbitrary data can be used.

Next, referring to FIG. 8 and FIG.
Update of the memory contents of the P-MEM (program memory) 32 in the SP will be described.

FIG. 8 shows an example of a memory map of a program in the P-MEM 32. As shown in the figure, for example, when the memory capacity of the P-MEM 32 is 4K, the programs of the main routine are collectively stored in the first half of the memory area, the programs of various subroutines are stored in the latter half of the memory area, and interrupts are made at appropriate places. The program of the processing routine is stored.

In the present embodiment, P-
The interrupt processing program for updating the memory contents of the MEM 32 is stored in a predetermined area (for example, A1 to A2). Further, in the P-MEM 32, the memory content to be updated (for example, the address information designating the head address A3 of the subroutine program (SR) is previously stored in the C-MEM).
It is stored in 16 predetermined memory addresses AX.

FIG. 9 shows a host controller 36 and HOST-I for updating the memory contents in the P-MEM 32.
The communication format with F34 is shown.

For example, depending on the pitch adjustment of the reproduced sound, P-
When it is necessary to update the subroutine program SR in the MEM 32, the host controller 36 sets the HOS
For the T-IF 34, the chip select signal CS _- is enabled (low level), and then the P-ME
Mode selection data for instructing the M update mode is transmitted first, and then program data for one word (32 bits) for update is transmitted every 8 bits in four times. At this time, when the first 8 bits of program data is written in the reception register HR3, empty flag EMPTY _- goes high.

After transmitting the program data for one word, the host controller 36 once sets the chip select signal CS _- to a high level (disable state), and immediately after that, sets the CS _- to a low level (enable state). ) And send the mode selection data indicating the interrupt request. This mode selection data is HOST-I
When input to the shift register SHR of F34 and then written to the host interface mode register HIM, an interrupt request signal is output to the control device 30.

Upon receipt of this interrupt request, the control device 30 saves the contents of the program counter (correctly, the current program address + 1) and the status bits of the ALU 26, MAC 28, etc. on the stack, and then executes a predetermined interrupt. Jump to the first address A1 of the processing program. In this interrupt processing program, the P-ME described later
M write command (PW) is specified, and C-
Address information for designating a predetermined memory address AX of the MEM 16 is described.

The C-MEM 16 is accessed based on this address information, and the contents of the memory address AX (that is, the address information designating the leading address A3 of the memory area (subroutine program SR) in the P-MEM 32 to be updated). Is read. The read address information is transferred to the accumulator of the ALU 26. This ALU
The address information stored in the accumulator is further transferred to the program counter.

Thus, the P-MEM write command (PW)
Is executed, a part of the program data for one word (the most significant 24 bits) held in the reception registers HR3 to HR0 of the HOST-IF34 is part of the C-BUS10.
The rest (least 8 bits) directly through P-MEM3
It is transferred to 2 and written in memory address A3. Then, the address information is incremented by 1 in the ALU accumulator, and the incremented address information is written in the memory address AX in the C-MEM 16. This completes the update of one word, and the various data saved in the stack are returned to the original registers. As a result, the execution of the main program, which has been suspended due to interrupt processing, is resumed.

[0067] On the other hand, when P-MEM write command (PW) is executed, HOST-IF 34 is Empty Flag EMPTY _- and a low level (enable state), to be received next words of program data It informs the host controller 36 that it has become. In response to this notification, the host controller 36 transmits the next one word of program data again at the timing shown in FIG. 9, and then transmits the interrupt request mode selection data. Interrupt processing is executed. In this case, the value of the address information read from the memory address AX in the C-MEM16 is incremented by one compared with the previous interrupt, so the program data for one word this time is the memory address in the P-MEM32. It will be written to (A3 +1).

In this way, the memory contents or areas (A3 to A4) to be updated in the P-MEM 32 are 1 or less.
Updated word by word by interrupt processing. Therefore, P-
Due to the update of the memory contents of the MEM 32, the execution of the main program is not interrupted (finished halfway) even if it is temporarily interrupted during the interrupt processing, and therefore the audio signal processing is not substantially interrupted. Absent. In addition, C-MEM read by interrupt processing for updating
Contents of specified memory address AX in 16 (address information)
Is set to an arbitrary value, the arbitrary memory area in the P-MEM 32 can be updated.

In this embodiment, the HOST-IF 34 holds the program data for one word, and the program data for one word is updated by one interrupt processing. However, one interrupt by the design change. It is also possible to update the program data of 2 words or more by the processing.
In addition, the address information for designating the start address of the memory area to be updated in the P-MEM 32 is stored in the C-MEM16.
It is also possible to store it in a memory other than the above, for example, in the G-MEM 20.

The DSP of this embodiment holds the program and coefficient data from the host controller 36 in the HO.
It also has a function of downloading to the P-MEM 32 and the C-MEM 16 via the ST-IF 34, respectively.
When these are downloaded, 1 is set in the HLT bit of the mode selection data from the host controller 36.
Is set and execution of the program is stopped (FIG. 5).

Although the memory content updating circuit of this embodiment relates to a DSP for audio / digital signal processing, the memory content updating circuit according to the present invention can be applied to other digital signal processing devices. is there.

[0072]

As described above, according to the first memory content updating circuit of the present invention, in the digital signal processing device, the writing destination (the memory address to be updated is written to each new data for updating). ) Is assigned and set in the buffer memory respectively, and the read address for the data storage memory is compared with each update address information, and when a comparison match is obtained, the update address Since the data corresponding to the information is read from the buffer memory and written in the target memory address, the update operation will not be mistaken. Therefore, the order of execution instructions is not restricted by the update order of data or memory addresses, which simplifies the coding of programs and improves reliability.

According to the second memory content updating circuit of the present invention, in the digital signal processing device, the address information representing the memory address to be updated in the program storage memory is set (stored) in advance. Every time, new program data for updating from the external control device is received, the program data is written to the memory address specified by the address information by interrupt processing, so the execution of the program should be stopped. Instead, the contents of any (desired) memory address can be updated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an audio / digital signal processing DSP according to an embodiment of the present invention.

FIG. 2 shows a host interface circuit (H
It is a block diagram which shows the structural example of OST-IF).

FIG. 3 is a diagram illustrating a host interface circuit (HOST) according to an embodiment.
3 is a table showing functions of various terminal pins in (-IF).

FIG. 4 is a diagram illustrating a host interface circuit (HOST) according to an embodiment.
FIG. 3 is a block diagram showing a configuration example of a data receiving unit in (IF).

FIG. 5 is a table showing a format of mode selection data written in the host interface mode register of the embodiment.

FIG. 6 illustrates a host interface circuit (HOST) according to an embodiment.
3 is a block diagram showing a configuration example of a C-MEM update buffer and a configuration example of an update address comparator and an update control circuit in (-IF). FIG.

FIG. 7 is a host controller and HOST- for updating the memory contents in the coefficient memory (C-MEM) of the embodiment.
It is a figure which shows the communication format with IF.

FIG. 8 is a diagram showing an example of a memory map of a program in the program memory (P-MEM) of the embodiment.

FIG. 9 is a diagram showing a communication format between a host controller and a host interface circuit (HOST-IF) for updating the memory contents in the program memory (P-MEM) of the embodiment.

FIG. 10 is a block diagram showing a configuration of a main part of a conventional DSP.

[Explanation of symbols]

10 C-BUS (data bus) 12 D-BUS (data bus) 14 G-BUS (data bus) 16 C-MEM (coefficient memory) 18 D-MEM (data memory) 17, 19, 21 Addressing unit 26 ALU ( Arithmetic and logic operation unit) 28 MAC (sum of products operation unit) 30 control device 32 P-MEM (program memory) 34 HOST-IF (host interface circuit) 36 host controller 40 timing control unit 42 data receiving unit 44 C-MEM update Buffer 50 Address comparator 52 Coefficient update control circuit

Claims (3)

[Claims] 1. A memory content update circuit for updating the memory content of a data storage memory in a digital signal processing device in response to a request from an external control device, comprising: an update target in the data storage memory; Receiving means for receiving address information representing each memory address and new data for updating from the external control device, the address information received by the receiving means and new data for updating. And a buffer memory for storing the address information generated to read out arbitrary data from the data storage memory in the digital signal processing device, and match the address information with the address information stored in the buffer memory. The address collating means for judging whether or not the address collating means judges whether or not the collation coincidence judgment result is obtained from the address collating means. The execution cycle of the instruction is interrupted, new data for the update corresponding to the address information of the collation match is read from the buffer memory, and the read data is sent to the destination specified by the instruction and at the same time. A memory content updating circuit having a data operating means for writing to a memory address in the data storing memory specified by address information. 2. A memory content update circuit for updating the memory content of a program storage memory in a digital signal processing device in response to a request from an external control device, wherein the update target in the program storage memory is Address information storage means for storing in advance address information representing a memory address, receiving means for receiving new program data for updating transmitted from the external control device, and the receiving means for receiving the program data. Buffer means for holding new program data for updating, interrupt request generating means for generating a predetermined interrupt request for updating, and address information from the address information storage means in response to the interrupt request. Previously read to the memory address in the program memory specified by the read address information. Memory contents update circuit having, an interrupt processing means for transferring the new program data for the update stored in the buffer means. 3. The memory content updating circuit according to claim 2, wherein the address computing unit increments or decrements the address information read from the address information storage unit by a predetermined value, and the address computing unit. A memory content updating circuit having address writing means for writing the obtained new address information in the address information storage means.