JPH0812939B2 - Method for manufacturing jjosephson integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an integrated circuit including a Josephson element, and more particularly to a method for highly accurately forming a resistor which is a circuit element.

Since a logic circuit using a Josephson element operates at high speed and consumes very little power, research and development is being carried out on the assumption that there is a high possibility of realizing an ultrahigh-density integrated circuit for an ultralarge computer.

Ordinary Josephson integrated circuits have a Si buffer layer.
A ground plane of niobium (Nb), which is a superconductor material, is formed on a silicon substrate coated with an O ₂ film, and the ground plane is formed with SiO 2.
A circuit is constructed by forming a Josephson element and a resistance element on the insulating material layer as described above.

As a unit forming this circuit, a combination of a Josephson element and a resistor as shown in FIG. 3 is widely used. 9A is a plan view thereof, FIG. 9B is a sectional view taken along the line XX ', and FIG. 9C is a circuit symbol thereof. In the figure, 1 is a SiO layer, 2 is a resistor, and 3 is a part of which the base electrode of the Josephson element is formed Nb
A film, 4 is an Nb film on which a counter electrode of the Josephson element is formed, 5 is a SiO film that insulates the two Nb films, 6
Is a junction forming portion of the Josephson element, and the Nb ground plane, silicon substrate and the like below these are not shown.

The resistor used here has a resistance value of 1 to 1.5Ω.
It is made by shaping an aluminum (Al) film. This is connected to superconductor wiring such as Nb, but parasitic resistance similar to contact resistance occurs at this connection,
The value may be about 0.5Ω, which makes it difficult to control the resistance value of the resistor formed.

It is more important that the parasitic resistance is caused by the Al oxide film existing between the Al film and the Nb film than by the contact between different metals. That is, Al, which is the material of the resistor
When a method of depositing a film by sputtering and patterning this to form a resistor is used, a natural oxide film is generated on the surface of the Al film as a result of being exposed to the atmosphere, and this occurs between the Nb film and this film. It intervenes to bring about parasitic resistance.

This can be mitigated by sputter etching before sputter depositing the Nb film, but it is not a complete solution. In addition, since the value of this parasitic resistance is not constant, it is difficult to design the resistor in anticipation of an increase. Therefore, if a method of forming a resistor that does not generate such an oxide film is developed, it will have a favorable effect on the manufacturing of the Josephson integrated circuit.

[Conventional technology]

Conventionally, as described above, the method of removing the natural oxide film by sputter etching the surface of the Al film before depositing the Nb film by sputtering has been adopted. Although this has some effect, it does not sufficiently suppress variations in resistance value.

[Problems to be solved by the invention]

The conventional method that includes the step of exposing the Al film to the atmosphere once cannot prevent the occurrence of parasitic resistance, so the Nb film is deposited on the Al film without exposing it to the atmosphere. However, a method of forming the resistor must be developed.

[Means for solving problems]

This problem is solved by the method of the present invention described in the claims, but when the present invention is summarized in accordance with the examples described below, the Nb film is deposited successively to the deposition of the Al film, By dry etching under the condition that the Al film is not etched
This is a method for manufacturing a Josephson integrated circuit, which includes a step of forming a resistor by patterning Al by dry etching under the condition that the Nb film is not etched after patterning the Nb film.

[Action]

In the method of the present invention, since the Nb film is deposited on the Al film without being exposed to the atmosphere, there is no intervening oxide film, and the resistance value of the resistor is only its size. Therefore, the resistance value can be controlled with high accuracy. Incidentally, when the low antibody is formed by the method of the present invention, the Al film remains under the Nb superconductor, but as will be considered later, even if the strip line having such a structure is used, the Josephson integrated circuit will not be disturbed. It is possible to form.

〔Example〕

FIG. 1 shows an embodiment of the present invention. In the figure, the steps of forming the structure shown in FIG. 2 are shown in a sectional view and a plan view. In each step, (a) to (d) are plan views and are arranged on the right side of each. (A ')-(d') is the X-
It is a X'sectional view. 2A is a plan view, and FIG. 2B is a sectional view taken along line XX '. This embodiment will be described below with reference to FIG.

First, Al and Nb are continuously deposited by sputtering on a substrate having a surface on which a resistor is to be formed. The processing condition is Al
Of sputtering, Ar gas pressure 8 mm Torr., High frequency output
200 W, deposition rate 60 Å / min, thickness 200 Å, Nb sputtering has Ar gas pressure 15 mm Torr., High frequency output 500 W, deposition rate 800 Å / min, thickness 2500 Å. This state is shown in FIGS. In the figure, 1 is Si
The O layer, 2 is an Al film, and 3 is an Nb film.

It is a requirement of the present invention to carry out the sputtering deposition of these two types of films continuously, that is, without taking them out into the atmosphere.

Then, the formation of the resistor is started, but the Nb film is first patterned. That is, as shown in (b) and (b '), the resist 4 is deposited on the portion where Nb should be left, the reaction gas CF ₄ and the pressure 50
Reactive ion etching (RIE) is performed under the conditions of millitorr. And high frequency output of 100 W to remove unnecessary portions of the Nb film 3. Under this condition, Nb is etched at a rate of 1000 Å / min, while Al is hardly etched, the etching progresses at the Al surface 2, and the substrate surface after the step is (c),
As shown in (c '), it has an Nb pattern 3 and an Al surface 2. By this process, the Nb strip line, the base electrode of the Josephson element, etc. are formed.

Next, a resist 4'is deposited on the portion of the Al film 2 to be left as a resistor as shown in FIGS.
RIE is performed in Ar gas atmosphere of Torr. In a high frequency output of 100W. Under this condition, the Nb film is hardly etched, so that the Al film in the portion forming the resistor is left and the other Al films are removed by etching. In addition, since the etching rate for SiO is small and the Al film is thin, the Al film is completely removed by etching, and the SiO layer is hardly etched.
It is possible to stop.

The Al film resistor is formed by the above steps, and the structure shown in FIG. 2 is realized. As is apparent from FIG. 2B, the Al film 2 remains under the Nb film 3, but the reason why the strip line having such a structure can be used will be described below.

The resistor used in the Josephson integrated circuit is preferably formed by patterning a film having a sheet resistance of 1 to 1.5 Ω / □ in consideration of restrictions such as photolithography. The Al film of the above example has a resistivity ρ of 2.45 μΩ.
・ Since the film thickness is cm and the film thickness is 200Å, the sheet resistance R _□ ≈1.2
Then, this condition is satisfied.

On the other hand, the strip line formed according to the present invention has a shape in which a resistor is connected in parallel to the superconductor. In order to suppress the AC loss in the strip line to a sufficiently small level,
_Let I _L and I _R be the currents flowing in the superconductor and resistance conductor, respectively. It is necessary to satisfy. Here, L _□ is the inductance per unit area of the strip line, and R _□ is the sheet resistance of the resistive conductor.

Further, the following approximate expression holds for L _□ .

L _□ = μ ₀ {h + λ ₁ cot (t ₁ / λ ₁ ) + λ ₂ cot (t ₂ / λ ₂ )} ≈μ ₀ h where μ ₀ is the vacuum magnetic induction, λ ₁ and λ ₂ are the ground plane and Stripline magnetic field penetration distance, t ₁ , t ₂
Is the film thickness and h is the thickness of the SiO insulating layer on the ground plane. The SiO insulating layer and the ground plane are shown as 1 and 9 in FIG. 2, respectively.

Now, when calculating the value of L _{□ with} h = 3000Å, it is L _□ ≒ 4 × 10 ^-13 Ω ・ s, and the rise of the voltage of the strip line is 10 μs.
Then, ωL _□ = 0.3Ω / □ and R _□ = 1.2Ω / □, so R _□ >> ωL _□ and the above expression (1) is satisfied.

As discussed above, even a stripline having a structure in which an Al film is left under the Nb film does not seriously affect the operation of the circuit. Considering that in the manufacture of a normal Josephson integrated circuit, the Nb film is deposited several times, and the present invention is applied only to the formation of the Nb film connected to the Al resistor. The effect of the presence of the Al film is even smaller.

In the above embodiment, the patterning is performed in the state where only one layer of Nb film is deposited on the Al film, but not only one layer of Nb film but also the bonding film and the counter electrode for forming the Josephson element are formed. After depositing a second Nb film to
The method of the present invention can also be applied to patterning. Further, the method of the present invention can be generally applied to the case where the resistance conductor and the superconductor are connected, not limited to the combination of Al and Nb.

〔The invention's effect〕

As described above, according to the method of the present invention, the Al low antibody and the Nb film that is a superconductor can be connected without causing a parasitic resistance. It is possible to form the body.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a process of the present invention, FIG. 2 is a plan view and a sectional view showing a structure formed by the present invention, and FIG. 3 is a Josephson element and a resistor are connected. In the figure, 1, 5 is a SiO layer 2, 2 is an Al film 3, 3 is an Nb film 4, 4'is a resist 6, and a junction forming part 9 is an Nb ground plane.

Claims (2)

[Claims] 1. A step of continuously depositing a resistive conductor material coating and a superconducting material coating, and under the condition that an etching rate for the superconductor material is higher than an etching rate for the resistive conductor material. Patterning the superconductor material film by dry etching; forming a resist pattern on the resistance conductor film exposed by the patterning process; using the patterned superconductor film and the resist pattern as a mask A step of patterning the resistive conductor film by dry etching under the condition that the etching rate for the resistive conductor material is higher than the etching rate for the superconductor material. Production method. 2. The method for manufacturing a Josephson integrated circuit according to claim 1, wherein the superconductor material is niobium and the resistive conductor material is aluminum.