JPH0813105B2 - Semiconductor scanning circuit - Google Patents

Description

The present invention relates to a semiconductor device in which a scanning circuit including a large number of flip-flop circuits is integrated on a semiconductor substrate.

[Outline of Invention]

According to the present invention, a third field effect transistor for control (hereinafter a field effect transistor is referred to as FET) and a fourth FET are added to a flip-flop of a semiconductor scanning circuit, so that the delay of the semiconductor scanning circuit is delayed by a control signal from the outside. The number of steps can be changed.

[Prior Art] FIG. 3 shows a circuit diagram of a conventional semiconductor scanning circuit. In the conventional semiconductor scanning circuit, one flip-flop is composed of a first FET1, a second FET2, a first inverter 5 and a second inverter 6, and the flip-flops are connected in series according to the required number of scanning circuits to form a scanning circuit. It was a thing.

The operation of the scanning circuit will be described. The signal input by the data input 13 is input by the first FET 1 and the first clock 1 and is held at the input of the first inverter by turning the first clock from the ON state to the OFF state. It Next, the signal transmitted by the first inverter is held at the input of the second inverter by opening and closing the second FET and the second clock. The signal transmitted to the output of the second inverter is input to the flip-flop of the next stage. By the above operation, the signal input to the data input 13 is transmitted to each flip-flop and passes through the required number of stages, whereby an output signal delayed by the desired number of stages is obtained.

[Problems to be solved by the invention]

In the conventional semiconductor scanning circuit, for example, when the semiconductor scanning circuit is configured by 100 stages of flip-flops,
If you want to obtain the output from the 50th stage in the middle, wiring to take the output of the 50th stage is required. Further, when each output of the scanning circuit having a certain number of stages is connected, in order to change the delay time of the scanning circuit at each output, the connection must be changed or the number of delay stages of the scanning circuit must be changed. did not become. Therefore, an object of the present invention is to solve the above problems and provide a semiconductor scanning circuit capable of changing the delay time by an external control signal without changing the wiring or changing the number of delay stages of the semiconductor scanning circuit. It is a thing.

[Means for solving problems]

The semiconductor scanning circuit of the present invention comprises: a) a semiconductor scanning circuit having a plurality of two-dimensionally arranged flop-flop circuits, and b) a flip-flop having a first FET, a second FET, a third FET and a fourth FET.
ET and a first inverter and a second inverter, and c) the sources of the first FET and the fourth FET are connected to the input of the first inverter, the output of the first inverter is connected to the drains of the second FET and the third FET, The sources of the 2FET and the 3rd FET are connected to the input of the 2nd inverter, the gate of the 1st FET is connected to the 1st clock, the gate of the 2nd FET is connected to the 2nd clock, and the gates of the 3rd FET and the 4th FET are control inputs. It is characterized in that it is configured to be connected to.

[Action]

To describe the operation of the present invention, as shown in FIG.
It is composed of 4 FETs and first and second inverters. First
Although the figure shows only four stages of flip-flops,
For example, when operating these four stages as a two-stage semiconductor scanning circuit, the control input 22 and the control input 24 may be turned on. When the control inputs 22 and 24 are turned on, the third FET and the fourth FET of the flip-flop circuit are turned on, the flip-flop circuit at this stage acts as a mere buffer, and the output lines 14 and 15 have the same delay output and the output line. 16 and 17 also have the same delayed output. This state is shown in the timing chart of the semiconductor scanning circuit of FIG.

〔Example〕

 FIG. 1 shows an embodiment of the present invention.

The semiconductor scanning circuit of the present invention is composed of a plurality of one-dimensionally arranged flip-flop circuits, and the flip-flop circuits are the first FET-1, the second FET-2, the third FET-3, and the fourth FET.
-4, the first inverter 5 and the second inverter 6. The gate of the first FET is connected to the first clock 11 and the gate of the second FET is connected to the second clock 12,
The gates of the 3FET and the 4th FET are connected to the control inputs 21 to 24 for each flip-flop. 1st FET and 1st
The source of the 4FET is connected to the input of the first inverter 5,
The drains of the second FET and the third FET are connected to the output of the first inverter 5, the sources of the second FET and the third FET are connected to the input of the second inverter 6, and the output of the second inverter 6 becomes the input of the next stage. When all the control inputs 21 (V21) to 24 (V24) are off, the signal V13 input to the data input 13 is the first
The signal is sequentially delayed by the clock 11 (V11) and the second clock 12 (V12) and delayed by each stage as shown in the timing chart of FIG. 4, and the signals of different timings are output to the output lines 14-17. V14, V15, V16, V17 are output. 22 when control inputs 21 (V21) and 23 (V23) are off
When (V22) and 24 (V24) are on, the second and fourth flip-flop circuits act as simple buffers, and the output line 15 has the same signal V14,
V15 is output, and the signals V16 and V17 at the same timing as the output line 16 are output to the output line 17, and the total number of delay stages is half that when the control inputs 21 to 24 are all off.

In the embodiment of the present invention shown in FIG. 1, the control input is 21.
It is composed of four to four, but may be composed of any number if necessary. Although the first FET to the fourth FET are composed of N channels for convenience of description, they may be composed of P channels, or a combination of P channels and N channels can constitute a circuit having the same operation.

FIG. 2 shows an embodiment in which the semiconductor scanning circuit of the present invention is applied to a solid-state image pickup device. Reference numeral 200 and 300 in FIG. 2 is composed of the semiconductor scanning circuit of the present invention, and 31 horizontal switches are signal line selection switches arranged in plural one-dimensionally.
33 are vertical switches and photodiodes, 32 and 3
A plurality of 3s are arranged two-dimensionally.

In the conventional solid-state imaging device using the semiconductor scanning circuit, wiring change or the like had to be performed to change the number of bits in the horizontal direction and the vertical direction. 21 to 24 by electric signal from
By controlling the control inputs 211 and 214, the number of bits on the horizontal and vertical sides can be freely changed.

Therefore, it becomes possible to take out a plurality of optical characteristics from one solid-state imaging device, and the range of application is greatly expanded.

〔The invention's effect〕

Since the semiconductor scanning circuit of the present invention can change the number of delay stages of the scanning circuit by electrical control from the outside, it is not necessary to make design changes such as wiring changes and changes in the number of delay stages, and there is a margin of design. It also has a great effect on the spread and cost reduction.

Further, when applied to a solid-state imaging device, the optical characteristics can be freely changed, so that there is an effect that the application range is greatly expanded.

[Brief description of drawings]

 1 is a circuit diagram of a semiconductor scanning circuit showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional semiconductor scanning circuit. Timing chart of scanning circuit 1 …… First FET 2 …… Second FET 3 …… Third FET 4 …… Fourth FET 5 …… First inverter 6 …… Second inverter 11 …… First clock 12 …… Second clock 13 ...... Data input 14 ...... First output line 15 ...... Second output line 16 ...... Third output line 17 ...... Fourth output line 21 ...... First control input 22 ...... Second control input 23 ...... Second 3 control input 24 ... 4th control input 200 ... horizontal semiconductor scanning circuit 300 ... vertical semiconductor scanning circuit 111 ... 1st clock 121 ... 2nd clock 131 ... data input 211 ... 1st control input 212 …… Second control input 213 …… Third control input 214 …… 4th control input 141 …… 1st output line 151 …… 2nd output line 161 …… 3rd output line 171 …… 4th output line 31 …… Horizontal switch 32 …… Vertical switch 33 …… Photodiode 34,44,54,64 …… Vertical signal line 60 …… Output signal line 100 …… Flip-flop circuit 1 stage V11 …… First clock signal V12 …… Second clock signal V13 …… Data input signal V14, V15, V16, V17 …… Output line output signal V21, V22, V23, V24 …… Control input signal V5, V51, V52, V53 …… First inverter output signal

Claims (1)

[Claims] 1. A semiconductor scanning circuit having a plurality of one-dimensionally arranged flip-flop circuits, wherein: (b) the flip-flop circuits are a first field effect transistor, a second field effect transistor and a third field effect transistor. An effect transistor, a fourth field effect transistor, a first inverter and a second inverter, and (c) sources of the first field effect transistor and the fourth field effect transistor are connected to an input of the first inverter, The output of the first inverter is connected to the drains of the second field effect transistor and the third field effect transistor, the sources of the second field effect transistor and the third field effect transistor are connected to the input of the second inverter,
The gate of the first field effect transistor is connected to the first clock, and the gate of the second field effect transistor is the second clock.
A semiconductor scanning circuit connected to a clock, wherein the gates of the third field effect transistor and the fourth field effect transistor are connected to a control input.