JPH0815260B2 - Error count circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error count circuit, and more particularly to an error count circuit for counting the number of error data in a continuous data string for each predetermined section.

[0002]

2. Description of the Related Art Conventionally, this type of error counting circuit is
It is used for the purpose of continuously measuring the data of a continuous data string for each section of m units and counting the number of error data for each section.

FIG. 4 is a circuit diagram showing an example of a conventional error count circuit. Each of the first section counter 5a of the first counter 5 and the second section counter 6a of the second counter 6 is a down counter and counts the number m of measurement data of one section. Further, the first error counter 5b of the first counter 5 and the second error counter 6b of the second counter are both down counters and count the number of error data in one section. When the number of error data becomes n, O
An alarm is generated via the R gate 14. The first error counter 5b and the second error counter 6b operate in pairs with the first section counter 5a and the second section counter 6a, respectively, and the first counter 5 and the second counter 6 operate alternately.

Next, the operation will be described with reference to the waveform chart of FIG. First, consider a case where the second section counter 6a has completed counting the measurement data m. When the second section counter 6a finishes counting, an H (high) level carry is generated. The generated carry is stored in FF (flip-flop) 7 after half a clock, and as a result, FF
Q output of 7 changes from L (low) to H and SR latch 8
Is reset. When the SR latch 8 is reset, its Q inversion output becomes H level, the second section counter 6a is loaded with the initial value m, and the second error counter 6b is loaded with the initial value n + 1 to start counting the second counter 6. State. This is shown in (f), (g), and (h) of FIG. By setting the second counter 6 to the counting initial state, the carry of the second section counter 6a changes to the L level, the FF 7 stores the L level at the next CLK (clock), and as a result, the Q output of the FF 7 becomes the L level. Change to level, SR
The reset of the latch 8 is released. In this case, since the SR latch 8 holds the output level until it is set,
The loaded states of the second section counter 6a and the second error counter 6b are held and counting is not performed.

The H level of the Q inverted output of the SR latch 8 further opens the OR gate 9a to enable (ENB) the first section counter 5a, and is also supplied to the AND gate 10 to be supplied to the first gate via the OR gate 9b. 1 Error signal input to the error counter 5b is enabled. Accordingly, the counting operation is performed from the second counter 6 to the first counter 5.
Move on to.

When the first section counter 5a finishes counting the data of one section, the same operation as that of the second section counter 6a described above is performed. That is, a carry is generated in the first section counter 5a and the carry is taken into the FF 11. The Q output of the FF 11 sets the SR latch 8 to the set state, the Q output of the SR latch 8 becomes the H level, and the first section counter 5a is loaded with the initial value m and the first error counter 5b is loaded with the initial value n + 1. To the initial state of counting, and the second section counter 6a and the second error counter 6b are enabled via the OR gates 12a and 12b and the AND gate 13, and the counting operation is the first.
The counter 5 moves to the second counter 6. This state is shown in Figure 5.
(B), (c), and (d).

By repeating the above series of operations, the first counter 5 and the second counter 6 operate alternately.

[0008]

Since this conventional counting circuit has two sets of the same counting circuit, when the number of digits to be counted must be increased to two sets, the circuit scale is remarkably large. It had the drawback of increasing.

Further, when the error count circuit of this type is constituted by one set of error count circuits, there are the following problems. This will be described with reference to FIGS. 6, 7 and 8.

In FIG. 6, the section counter 15 completes counting and the generated carry is used as a load signal to load the section counter 15 with an initial value m and the error counter 2 with an initial value n + 1 to count. If there is no error in the data at the time of returning to the initial state, the error is correctly counted as shown in the waveform chart of FIG. However, if there is an error in the data at the timing of returning to the counting state, the first error is not counted as shown in the waveform diagram of FIG. Therefore, conventionally, two sets of counters are operated alternately as shown in FIG. 4 to correctly count.

The object of the present invention is to solve the abovementioned drawbacks, and
An object of the present invention is to provide an error count circuit which has a simple structure limited to a set of count circuits and which does not generate a count error even in the initial count state (during load).

[0012]

The circuit of the present invention comprises a section counter for repeatedly counting the number of data of a preset data string for each predetermined section, and the number of errors contained in the data of the data string in the predetermined section. An error count circuit for determining whether or not the count value of the error counter is within a limit by a repeated count for each of the predetermined intervals, which includes an error counter that counts for each predetermined interval. There is provided means for suppressing the occurrence of a count error in the error counter by switching the initial value of the error counter in accordance with the presence / absence of error data at the time of starting the repeated counting.

Further, the circuit of the present invention has a structure in which the section counter and the error counter are each one and are down counters.

[0014]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The section counter 1 is a down counter and counts the number m of measurement data in one section. Error counter 2
Is a down counter and counts the number of error data in one section. The selector 3 switches the initial value to be loaded into the error counter 2, and selects either the number n of error data or the value n + 1 obtained by adding 1 to the number n of error data. The OR gate 4 supplies the enable input of the error counter 2.

Next, the operation of this embodiment will be described.
First, a carry occurs when the section counter 1 completes the counting of data for one section. The carry is used as a load signal, and the load signal 101 loads initial values to the section counter 1 and the error counter 2, respectively. The initial value of the section counter 1 is m, while the initial value of the error counter 2 is different when there is no error and when there is an error. This will be described with reference to the waveform diagrams of FIGS. 2 and 3.

FIG. 2 is a waveform diagram when there is no error during loading. When there is no error at the time of loading, the number n + 1, which is one greater than the number n of errors, is loaded and the error counting is started from the clock timing next to the loading.

FIG. 3 is a waveform diagram when an error occurs during loading. At some load time, load the number n of errors. This is the same state as when an error is counted at the time of loading, which is the same operation as when the error counting is started from the load clock timing.

By the above operation, the error in the initial state of counting can be counted without error.

[0020]

As described above, according to the present invention, when the counter is loaded with no error, the number of errors to be down-counted is increased by one rather than the error. It has an effect that it can be constituted by one set of section counter and error counter, and that the increase of the constituent elements in the increase of the number of digits can be significantly suppressed.

[0021]

[Brief description of drawings]

FIG. 1 is a circuit diagram of an error count circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining an operation when there is no error during loading according to the embodiment of this invention.

FIG. 3 is a diagram for explaining an operation when an error occurs during loading according to the embodiment of this invention.

FIG. 4 is a circuit diagram showing an example of a conventional error count circuit.

FIG. 5 is a waveform diagram for explaining the operation of a conventional error count circuit.

FIG. 6 is a circuit diagram of an error count circuit in the case where one set of counters is used.

FIG. 7 is a waveform diagram for explaining an operation in the case where there is an error when loading the error count circuit including one set of counters.

FIG. 8 is a waveform diagram showing an operation when there is no error when loading the error count circuit with one set of counters.

[Explanation of symbols]

 1 section counter 2 error counter 3 selector 4 OR gate

Claims (2)

[Claims] 1. A section counter for repeatedly counting the number of data of a preset data string for each predetermined section, and an error counter for counting the number of errors contained in the data of the data string for each of the predetermined section. An error count circuit for judging whether or not the count value of the error counter is within a limit by the repeated count for each of the predetermined sections, wherein the error data of the error data at the start point of the repeated count for each of the predetermined sections is An error count circuit comprising means for switching the initial value of the error counter in accordance with the presence or absence of the error counter to suppress the occurrence of a count error in the error counter. 2. The error counter circuit according to claim 1, wherein each of the section counter and the error counter is configured as a single down counter.