JPH0817450B2 - Noise reducer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a noise reducer that digitally processes an input signal such as an image signal to reduce noise.

[Conventional technology]

A noise reducer utilizing 1) interline correlation, 2) field correlation, or 3) interframe correlation in the image signal is known as one for reducing noise in the image signal.

Also, in recent years, semiconductor technology has advanced rapidly, and high-speed A / D (analog / digital) converters, D / A (digital / analog) converters and memories for image signals have been developed, and noise reducers using digital technology have been developed. It has become possible. In particular, a delay circuit to which a memory is applied realizes a field delay and a frame delay, and a field correlation and frame correlation noise reducer which could not be realized by an analog circuit in the related art can be realized.

For noise reducers using these digital techniques, please refer to the blow-out. "Digital signal processing of images". It is discussed on pages 115 to 118, published by Nikkan Kogyo Shimbun, May 25, 1981.

[Problems to be solved by the invention]

At present, there are some problems to be solved when constructing a noise reducer by a digital technique, but one of the major problems is the number of quantization bits of an A / D converter.

When an analog signal is digitalized, a gradation error (quantization error) occurs due to the quantization.

In the image signals (for example, color difference signals RY, BY, etc.), it is said that the number of quantization bits is generally required to be 8 bits in order to make the quantization error a visually insignificant amount. . However, high bit rate and high speed for image signals
With the current semiconductor technology, A / D converters have not yet reached the stage of full-scale practical use, and are becoming expensive. Therefore, the conventional noise reducer using the above-mentioned high bit number A / D converter has a problem that it becomes an expensive system.

It is an object of the present invention to provide a noise reducer configured to obtain a high quality image while using an A / D converter with a low bit number.

[Means for solving problems]

The above objects are: an A / D converter whose number of quantization bits is N bits, a delay circuit (for example, one field delay line) for delaying data of [N + m] bits (m is a positive integer), and an A / D converter.
The output signal of the N bit of the converter and the output signal of the [N + m] bit of the delay circuit are [1-K] and K times (0 <K
<1, for example, K = 0.75), and outputs an added [N + m] -bit signal and supplies it to the delay circuit, and D / A-converts the [N + m] -bit output signal of the arithmetic circuit. A noise converter is composed of A converter and A / D converter.
Noise of the converted N-bit data is reduced and at the same time, the [N + m] -bit pseudo high-bit data is obtained.
This is achieved by performing D / A conversion to obtain a noise-reduced image signal.

[Action]

The most important factor in the operation of the noise reducer according to the present invention is the arithmetic circuit for increasing the N bit data into the [N + m] bit data.

The operation of the arithmetic circuit will be described below. here,
If the data after A / D conversion at time ti is X (ti), the data of the [N + m] bit of the delay circuit is Y (ti), and the delay amount of the delay circuit is τ, then Y (ti) = [1 + K] * X (ti) + K * X (ti- [tau]) ... (1) Perform the calculation.

Now, assuming that K = 0.75, [1-K] = 0.025 = ^2-2 , and [1-K] .X (ti) has data up to 2 bits after the decimal point. In this case, since m = 2, the signal Y (ti) obtained by the above equation (1) is [N + m] = [N
+2] will have bit data. The m can be set larger as the feedback amount (feedback coefficient) K is closer to 1, that is, as [1-K] is smaller.

In this way, the noise reducer depends on the feedback coefficient K in its signal processing, and can make the m bit pseudo high bit. The present invention makes use of this feature, and the data of the [N + m] bits that can be obtained as a result of the above calculation is directly converted into D /
By performing A conversion, the pseudo high bit of data is performed and the image quality is improved.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which 1 is an A / D converter, 2 is an arithmetic circuit, 3 is a D / A converter, 4,
6 is a coefficient multiplication circuit, 5 is an addition circuit, and 7 is a delay circuit.

 The operation of the embodiment shown in FIG. 1 is as follows.

First, the video signal Si as an input image signal is supplied to the A / D converter 1. Here, the video signal Si is not particularly limited, and is, for example, a luminance signal or color difference signals RY, BY,
Alternatively, although it is a color signal after balanced modulation, it will be simply referred to as a video signal hereinafter.

In the A / D converter 1 (quantization bit number: N bits), the input image Si is quantized and the N bit digital signal X (ti) is quantized.
Is output and supplied to the coefficient multiplication circuit 4. Coefficient multiplication circuit 4
Then, the input signal X (ti) is multiplied by [1-K] (K is a feedback amount, and 0 <K <1. Generally, K = 0.5.
˜0.75), and outputs [1-K] · X (ti).

As described above, this [1-K] .X (ti) is the [N + m] bit with m bits after the decimal point (1.ltoreq.m and m is an integer. For example, when K = 0.75, m = 2). The data is supplied to the adder circuit 5. In the adding circuit 5, the output signals of the coefficient multiplying circuits 4 and 6 are added [N + m].
The bit signal Y (ti) is supplied to the delay circuit 7 and the D / A converter. In the delay circuit 7, the input signal Y
After delaying (ti) by τ (τ is one field period in the case of a field correlation noise reducer, for example), it is supplied to the coefficient multiplication circuit 6. The coefficient multiplying circuit 6 multiplies the inputted [N + m] -bit signal Y (ti) by K, rounds it to [N + m] -bit data, and supplies it to the adding circuit 5.

As a result, the arithmetic circuit formed by the coefficient multiplying circuits 4 and 6 and the adding circuit 5 is represented by the above equation (1).

Y (ti) = [1-K] .X (ti) + K.Y (ti-.tau.) (2) The following calculation is performed. Finally, the noise is reduced by a high bit rate and a feedback loop (comb filter) [N +
m] The bit signal Y (ti) is D / A converted by the D / A converter 3 and a signal So is output.

FIG. 2 is an input / output waveform diagram showing the waveform response when K = 0.75 and m = 2 in the configuration of FIG. 1, where (a) is the input waveform diagram and (b) is the output waveform diagram. 8 is 1LSB at t = τ
Is the input waveform and 9 is the output waveform at this time.

It can be seen from the figure that, in the present embodiment, the output signal has a high bit rate, so that the signal gradually changes and the quantization error is less visible.

As described above, according to the present embodiment, in the noise reducer using the A / D converter having a relatively small number of quantization bits, the output signal can be increased in bit rate and a high quality room can be realized.

FIG. 3 is a block diagram showing a second embodiment of the present invention, in which the same symbols as in FIG. 1 correspond to the same parts, and 10 is a subtraction circuit.

In the figure, the arithmetic circuit 2 is composed of an adding circuit 5, an arithmetic circuit 10 and a coefficient multiplying circuit 6. The arithmetic expression of the arithmetic circuit 2 of the present embodiment is as follows.

Y (ti) = X (ti) + K ・ {-X (ti) + Y (ti-
τ)} = [1−K] · X (ti) + K · Y (ti−τ) (3) This is the same as the arithmetic circuit 2 of the first embodiment. Therefore, also in this example, the same effect as that of the first example can be obtained.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

In the noise reducer, the greater the feedback amount K, the greater the noise reduction amount, but on the other hand, the afterimage increases, which is a problem. In the embodiment shown in FIG. 4, in order to reduce the afterimage, a motion adaptive circuit is added to the configuration of the second embodiment.

 In FIG. 4, 11 is a non-linear circuit.

FIG. 5 is a characteristic diagram showing an example of response characteristics of the non-linear circuit.

In the present embodiment, the amount of movement is detected by the amount of change (difference amount) during the τ period, and the feedback amount K is reduced in a region where the amount of change is large. That is, when the difference output of the subtraction circuit 10 is large, the gain (feedback amount) is reduced by the non-linear circuit 11 having the characteristics shown in FIG.

As a result, in the present embodiment, the number of bits is effectively reduced in the area where the image signal greatly changes, but the number of bits is hard to see in the area where the amount of change is large, and substantially in the present embodiment as well as the above-mentioned embodiment. The same effect can be obtained.

Although the motion amount is detected from the signal itself to be processed in the third embodiment, it may be detected from a signal having another correlation.

〔The invention's effect〕

As described above, according to the present invention, by using the A / D converter having a relatively small number of quantization bits, the pseudo high-bitization processing is performed, thereby reducing the apparent quantization error. It is possible to reproduce a high-quality image, solve the problems of the prior art described above, and provide a noise reducer with excellent functions.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, FIG. 2 is an input / output waveform diagram of the noise reducer, FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIG. 4 is the present invention. The third
A block diagram showing an embodiment and FIG. 5 are characteristic diagrams of a non-linear circuit. 1 ... A / D converter, 2 ... arithmetic circuit, 3 ... D / A converter,
4, 6 ... Coefficient multiplication circuit, 5 ... Addition circuit, 7 ... Delay circuit, 10 ... Subtraction circuit, 11 ... Non-linear circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiro Owase 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Inventor Akifumi Sanbe 292 Yoshida-cho, Totsuka-ku, Yokohama Household Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Michio Masuda, 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Household Appliances Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-60-85630 (JP, A) Special Kaisho 61-224573 (JP, A)

Claims (1)

[Claims] 1. A noise reducer for reducing the noise of an input image signal by digital processing, the A / D converting means for converting the input image signal into an N-bit digital signal, and an N-bit signal from the A / D converting means. The output signal is (1-
K) times (K is a feedback coefficient, 0 <K <1), and has m bits after the decimal point (where m is an integer of 1 or more) [N
+ M] -bit signal for outputting a first coefficient multiplying means, delay means for inputting an [N + m] -bit signal having data of m bits after the decimal point and delaying it by a fixed time, and [N + m] from the delay means. ] Multiply the bit signal by K,
Second coefficient multiplying means for outputting a [N + m] bit signal having m bit data after the decimal point, and [N + m] output from the first and second coefficient multiplying means.
Adder means for adding the bit signals and outputting the [N + m] bit adder signal as the input signal of the delay means, and a D / A for converting the adder signal output from the adder means into an analog signal. A noise reducer characterized by comprising a conversion means for reducing the quantization error of the A / D conversion means and for realizing a pseudo high bit rate.