JPS6449376A - Noise reducer - Google Patents

Abstract

PURPOSE:To obtain a high quality image by the use of the A/D converter of the number of low bits by using an arithmetic circuit to make the output data of the N bit of the A/D converter into the high bit of the data of [N+m] bits. CONSTITUTION:An A/D converter 1 inputs a video signal, outputs a digital signal X of an N bit and supplies it to a coefficient multiplying circuit 4. The circuit 4 makes the signal X [1-K]-fold (K is a feedback quantity and 0<K<1 is obtained.) The output signal of the circuit 4 is the data of the [N+m] bits having the data of an (m) bit less than a decimal point (1<=m and (m) are integers). An adder circuit 5 supplies a signal Y of the [N+m] bit to add the output signal of coefficient multiplying circuits 4 and 6 to a delaying circuit 7 and a D/A converter 3. The delaying circuit 7 delays the signal Y for a constant time and supplies it to the circuit 6. The circuit 6 makes K-fold the signal Y, rounds it to the data of the [N+m] bit, and thereafter, the circuit supplies it to the adder circuit 5. For this reason, an arithmetic circuit composed of the coefficient multiplying circuits and the adder circuit 5 executes the prescribed operation. Finally, the signal Y of the [N+m] bit, in which the high bit is executed and a noise is reduced by a feedback loop, is given to the D/A converter 3.