JPH0818005A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a stable semiconductor integrated circuit from which two outputs, positive phase and opposite phase outputs, of a differential amplifier can be taken out in good balance. CONSTITUTION:Collectors 6 and 26 of NPN type transistors 1 and 2 constituting a differential amplification circuit, and load resistors 7 and 27 are connected together with wirings 17 and 37, respectively, and further, both resistors are connected to a power supply with a wiring 40, and then, width and shape of wirings 19 and 20 for connection to both resistors from the middle point 39 of wiring are made about the same, and again, those of contact apertures 12 and 32 far both resistors and wirings are made about the same, so that, positive and opposite phase outputs from the amplifier are taken out in balance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit suitable for a high frequency signal amplifier circuit, and more particularly to a differential amplifier circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have come to be used also in high frequency signal processing circuits.

The gain of the differential amplifier in the case of forming the differential amplifier in the conventional semiconductor integrated circuit will be described below.

FIG. 5 is a circuit diagram of a conventional differential amplifier,
In FIG. 5, 111 and 112 are first and second transistors, 113 is a voltage source, 114 and 115 are first and second load resistors, 116 and 117 are bias resistors, 120 is a coupling capacitor, and 121 is an input. Signal source, 122 is bias power supply, 123
Is a current source, and 124 and 125 are output terminals.

The operation of the differential amplifier configured as above will be described. The voltage Vo at the output terminal 124 of the differential amplifier of FIG.
1 and a gain G1 between the input signal source 121, a voltage Vo2 at the output terminal 125 of the differential amplifier and a gain G2 between the input signal source 121,
If the resistance values of the load resistors 114 and 115 are Rc, the current value of the current source 123 is Io, and the impedance value of the coupling capacitor 120 for the input signal is sufficiently lower than the output impedance of the input signal source 121, The gains G1 and G2 are

[0006]

## EQU1 ## G1 = -Rc / (4Vt / Io)

[0007]

## EQU2 ## G2 = Rc / (4Vt / Io).

Here, "-" of G1 indicates that the phase of the output signal is opposite to that of the input signal, Vt is called thermoelectromotive force, which is obtained by Vt = kT / q, and k is Boltzmann. Constant, T is absolute temperature, q is electron charge, V
t is about 26 mV at room temperature.

[0009]

However, in the above conventional structure, when the semiconductor integrated circuit is formed into a semiconductor integrated circuit, the impedance of the metal wiring for connection used in the semiconductor integrated circuit cannot be ignored.

A conventional semiconductor integrated circuit will be described below. FIG. 6 is a pattern plan view showing a part of a differential amplifier composed of a conventional semiconductor integrated circuit, and 1 is a first N
PN type transistor, 21 is a second NPN type transistor, 2 and 22 are N type epitaxial layers grown on a P type semiconductor substrate, 3 and 23 are P type semiconductor regions for separating elements, and 4 and 24 are The P-type semiconductor regions for base 5 and 25 diffused in the N-type epitaxial layers 2 and 22, which are insulated and isolated by the P-type semiconductor regions 3 and 23, are in the P-type semiconductor regions 4 and 24, respectively. N for diffused emitter
Type semiconductor regions, 6 and 26 are N type semiconductor regions for collector contact diffused in the N type epitaxial layers 2 and 22, and 7 and 27 are N type epitaxial layers different from the N type epitaxial layers 2 and 22. Load resistors 8 and 38 composed of diffused P-type semiconductor regions are collectors 6 and 26 of the first and second NPN type transistors 1 and 21, respectively.
A metal wire for connection electrically connected with 14, a metal wire for connecting a semiconductor resistance element 14, 34, an emitter 5 of the first NPN transistor 1 and an emitter 25 of the second NPN transistor 21 From the first NPN transistor 1 to the current source, 16 is a metal wire for connecting the base 4 of the first NPN transistor 1 to the input and bias resistor, and 36 is the second NPN transistor 21. base
24 is a connecting metal wire for connecting the bias resistor, 17 is a first connecting metal wire for connecting the collector 6 of the first NPN transistor 1 and the load resistor 7, and 37 is the second metal wire. A second connection metal wire for connecting the collector 26 of the NPN transistor 21 and the load resistor 27, 18 a third connection metal wire for connecting the load resistor 7 and the load resistor 27, Reference numeral 19 is a metal wire for connection for connecting the load resistance 27 and the voltage source, 9, 10, 11, 12, 13, 29, 30, 31, 32, 33
Are P-type semiconductor regions (bases) 4 and 24 and N-type semiconductor regions
(Emitter) 5,25 and N-type semiconductor region (collector) 6,26
And metal wiring 8,15,16,17,18,3 for connection for load
It is a contact window that electrically connects 6, 37 and 38.

The operation of the semiconductor integrated circuit configured as described above will be described.

First, the impedance of the metal wiring for connection used in the semiconductor integrated circuit will be described. FIG. 8 is a plan view of the metal wiring for connection used in FIG. 6, 41 is a metal wiring for connection, and 42 and 43 are contact windows. FIG.
In general, the resistance component R of the metal wiring for connection in
It is represented by.

[0013]

## EQU00003 ## In R = .rho.L / W + .rho.n / 2 (Equation 3), ρ is the specific resistance of the metal wiring, L is the length of the metal wiring, W is the line width of the metal wiring, and n is the metal wiring bent at a right angle. It is the number of corners when it is cut, and this corner part can be converted with a sheet resistance of 1/2 based on the experimental value.

Similarly, the inductance component H of the metal wiring is
Is calculated by (Equation 4).

[0015]

## EQU00004 ## In H = log (L / W) + 0.224W / L + 1.193 (Equation 4), L is the length of the metal wiring, W is the width of the metal wiring, and the unit is [nH].

In FIG. 6, in the first and second NPN type transistors 1 and 21, the P type semiconductor regions 4 and 24 are base regions, the N type semiconductor regions 6 and 26 are collector regions, and the N type semiconductor regions 5 and 25. As an emitter region. Of these, the P-type semiconductor regions 4 and 24 (base) are electrically connected to the connecting metal wirings 16 and 36 through the contact windows 10 and 30, respectively. Similarly, the N-type semiconductor regions 5 and 25 (emitter) and the N-type semiconductor regions 6 and 26 (collector) are connected through the contact windows 9 and 29 and 11 and 31, respectively, to the metal wiring 1 for connection.
Electrically connected with 5, 17 and 37. The resistors 7 and 27 for the load formed of the P-type semiconductor region are connected through the contact windows 12, 13, 32 and 33 with the metal wirings 17, 37 and 37 for connection, respectively.
It is electrically connected to 18.

Correspondence between FIG. 5 and FIG.
The second transistors 111 and 112 are the first and second NPs of FIG.
The N-type transistors 1 and 21 and the load resistor 11 of FIG.
Reference numerals 4 and 115 are resistances 7 and 27 for the load in FIG. 6, and the metal wiring 16 for connection in FIG. 6 is the bias resistance 116 in FIG.
Is connected to the input signal source 121 via the coupling capacitor 120. The metal wiring 36 for connection in FIG. 6 is connected to the bias resistor 117 referred to in FIG. The connecting metal wiring 15 in FIG. 6 is connected to the current source 123 in FIG. 5, and the connecting metal wiring 17 in FIG. 6 is connected to the output terminal 124 in FIG. The metal wiring 37 for connection in FIG. 6 is connected to the output terminal 125 in FIG. The metal wiring 18 for connection in FIG. 6 is connected to the voltage source 113 referred to in FIG.

Next, an equivalent circuit is written as shown in FIG. 7 in consideration of the impedance of the metal wiring for connection in FIG. The resistance component of the metal wiring for connection between the contact window 13 and the contact window 33 of the metal wiring 18 for connection shown in FIG.
1 (171), the inductance component is L1 (170), the resistance component of the connection metal wiring between the contact window 33 of the connection metal wiring 18 and the voltage source 153 is R2 (173), and the inductance component is L2 (172). ), The resistance component of the metal wiring for connection between the contact windows 11 and 12 of the metal wiring 17 for connection is R
3 (181), the inductance component is L3 (180), the resistance component of the metal wiring for connection between the contact window 31 and the contact window 32 of the metal wiring 37 for connection is R4 (183), and the inductance component is L4 (182). ).

Further, in FIG. 7, 151 and 152 are the first and second
Transistor, 153 is a voltage source, 154 and 155 are resistors (RC) for load, 156 and 157 are bias resistors, 160 is a coupling capacitor, 161 is an input signal source, 162 is a bias power source,
163 is a current source, and 164 and 165 are output terminals.

The gain G51 between the input signal source 161 and the voltage Vo51 at the output terminal 164 of the differential amplifier constructed as shown in FIG.
The phase difference P51, the gain G52 between the voltage Vo52 of the output terminal 165 of the differential amplifier and the input signal source 161, the phase difference P52, the resistance values of the load resistors 154 and 155 are Rc, and the current value of the current source 163 is Io. ,
Assuming that the impedance value of the coupling capacitor 160 with respect to the input signal is sufficiently lower than the output impedance of the input signal source 161,

[0021]

[Equation 5] G51 =-(Rc + R1 + ωL1 + R3 + ωL3)
/ (4Vt / Io)

[0022]

## EQU6 ## P51 = tan to ¹ (-(ωL1 + ωL3) / (Rc + R1
+ R3))

[0023]

[Equation 7] G52 = Rc / (4Vt / Io)

[0024]

## EQU8 ## P52 = tan to ¹ (-.omega.L4 / (Rc + R4)) However, .omega. = 2.pi.f.

Here, "-" of G51 indicates that the phase of the output signal is opposite to the input signal, ωL1 is impedance 2πfL1 at frequency f, and Vt is kT / kT /.
It is represented by q, k is the Boltzmann constant, T is the absolute temperature, q is the amount of electron charge, and Vt is about 26 mV at room temperature.

Next, R1 and L in the actual semiconductor integrated circuit
When the values of 1, R3, L3, R4 and L4 are obtained, ρ = 16 mΩ, L = 60 μm, W = in the metal wiring 18 for connection.
If 10 μm and n = 0, then R1 = 0.096Ω from (Equation 3). Similarly, in (Equation 4), when L = 60 μm and W = 10 μm are substituted, L1 = 2.98 (nH).

In the metal wiring 17 for connection, ρ =
If 16 mΩ, L = 30 μm, W = 10 μm, and n = 0, then R3 = 0.048Ω from (Equation 3). Similarly, in (Equation 4),
Substituting L = 30 μm and W = 10 μm gives L3 = 2.37 (nH).

In the metal wiring 37 for connection, ρ = 16
If mΩ, L = 30 μm, W = 10 μm, and n = 0, then (Equation 3)
Therefore, R4 = 0.048Ω. Similarly, in (Equation 4), L
= 30 μm and W = 10 μm, L4 = 2.37 (nH).

Now, when the DC gain is obtained, the impedances ωL1, ωL3, ωL4 are 0Ω. Here, assuming that the resistance value Rc of the load resistors 154 and 155 is 200Ω and the current value Io of the current source 163 is 1 mA, G51 is 5.74 dB and G52 is 5.70 dB.
Becomes

Next, when the frequency is 200 MHz, the impedance ωL1 becomes 3.8Ω. Here, resistors for load 154, 155
Assuming that the resistance value Rc is 200 Ω and the current value Io of the current source 163 is 1 mA, G51 becomes 6.03 dB and G52 becomes 5.83 dB. In the above-mentioned conventional configuration, the output that should be the same originally is different, especially at high frequency. It will be noticeable. Similarly, the phase difference P51 is 181.9
°, P52 becomes 0.9 °, and the phase difference between P51 and P52 is 180
What should be ° is 181 °. When these two signals are used for further amplification, there is a drawback that an ideal signal cannot be extracted because of imbalance.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of taking out two outputs, a positive-phase output and a negative-phase output, of a differential amplifier in a well-balanced manner. .

[0032]

In order to achieve this object, the semiconductor integrated circuit of the present invention is configured such that the collector of the first transistor and the first load resistor constituting the differential amplifier circuit are made of the first wiring material. And connecting the collector of the second transistor and the second load resistance with the second wiring material, and connecting the first load resistance and the second load resistance with the third wiring material. Connecting to a power supply point, the width, shape, of the wiring material from near the center of the third wiring material to the first load resistor,
The size and the width, shape and size of the wiring material from the vicinity of the center of the third wiring material to the second load resistance are made substantially the same, and the first wiring material and the first load resistance are The shape and size of the contact part and the shape and size of the contact part of the second wiring material and the second load resistor are formed to be substantially the same. Further, the width and shape of the first wiring material and the second wiring material and the shape and size of the contact portion between the first load resistance and the second load resistance are formed to be substantially the same.

[0033]

According to the present invention, regardless of the magnitude of impedance of the metal wiring for connection which is inserted in series between the load and the power source of the differential amplifier configured by the semiconductor integrated circuit according to the above configuration, the differential The output levels of the positive-phase output and negative-phase output of the amplifier can be made almost equal.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a pattern plan view showing a part of a differential amplifier composed of a semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 1, the same parts as those in the conventional example shown in FIG. 6 are denoted by the same reference numerals, and the points different from the conventional example will be mainly described. In FIG. 1, 40 is a metal wire for a third connection for connecting the load resistance 7 and the load resistance 27 to a voltage source, and 39 is a contact window on the third connection metal wire 40.
The middle points 13 and 19 of the contact window 33 are metal wires for connection between the load resistance 7 and the middle point 39 of the third connection metal wire 40, and 20 is the third connection metal wire 40. The metal wiring 40 is a metal wiring for connection between the load resistance 27 and the midpoint 39. Then, one output is from the first connection metal wiring 17 connecting the load resistance 7 and the collector 6 of the first NPN transistor 1 to the connection metal wiring 8 from a position close to the load resistance 7. Take it out. Similarly, the other output also has a load resistor 27 and a collector 26 of the second NPN transistor 21.
The second connecting metal wiring 37 that connects the
Take out with a metal wire 38 for connection from a place near.

In the first and second NPN transistors 1 and 21, the P-type semiconductor regions 4 and 24 are base regions, the N-type semiconductor regions 6 and 26 are collector regions, and the N-type semiconductor regions 5 and 25.
As an emitter region. The P-type semiconductor regions 4 and 24 are electrically connected to the connecting metal wirings 16 and 36 through the contact windows 10 and 30, respectively. Similarly, the N-type semiconductor regions 5, 6 and 25, 26 are respectively provided with contact windows 9,
The metal wires 15, 17, 37 for connection are electrically connected through 11 and 29, 31. The resistors 7 and 27 for the load formed of the P-type semiconductor region are connected to the metal wirings 17, 37 and 40 for the first, second and third connection via the contact windows 12, 13, 32 and 33, respectively.
Electrically connected to.

Next, a description will be given by contrasting FIG. 1 which is a configuration diagram of a semiconductor integrated circuit in which a differential amplifier circuit is integrated with FIG. 2 which shows an equivalent circuit in consideration of line impedance of metal wiring for connection.

First, the metal wiring 40 for the third connection in FIG.
Is a wiring for a power supply, the power supply voltage from the voltage source 153 is supplied toward the midpoint 39, and has a resistance component R13 (179) and an inductance component L13 (178). Then, at the middle point 39 as a boundary, the metal wires 19 and 20 for connection having the same quality are branched.

Next, the metal wiring 19 for connection in FIG. 1 is connected to the contact window 13 at one end of the P-type semiconductor region 7 (resistance for load of the transistor 151) in FIG. It is a wiring that connects the two and has a resistance component R11 (175) and an inductance component L11 (174).

Next, the metal wiring 20 for connection in FIG. 1 connects the contact window 33 at one end of the P-type semiconductor region 27 (the load resistance of the transistor 152) in FIG. It is a wiring that connects the two and has a resistance component R12 (176) and an inductance component L12 (177).

Next, the metal wiring 17 for the first connection in FIG.
Is a wiring that connects between the contact window 12 at the other end of the P-type semiconductor region 7 in FIG. 1 and the collector contact window 11 of the first NPN transistor 1 (transistor 151 in FIG. 2). Yes, it has a resistance component R3 (181) and an inductance component L3 (180).

Next, the metal wiring 37 for the second connection in FIG.
Is a wiring that connects between the contact window 32 at the other end of the P-type semiconductor region 27 in FIG. 1 and the collector contact window 31 of the second NPN transistor 21 (transistor 152 in FIG. 2). Yes, it has a resistance component R4 (183) and an inductance component L4 (182).

Next, the connection metal wiring 15 in FIG. 1 connects the contact window 9 for the emitter of the first NPN transistor 1 and the contact window 29 of the second NPN transistor 21 in common. Then, the current of the current source 163 is supplied.

The metal wiring 16 for connection in FIG. 1 is
The first NPN transistor 1 (transistor 15 in FIG.
1) is a base input wiring, and the connection metal wiring 36 in FIG. 1 is a base input wiring of the second NPN transistor 21 (transistor 152 in FIG. 2), and both connections are connected. Input signals are obtained from the metal wires 16 and 36 for connection, and the metal wire 8 for connection (the output terminal 164 in FIG. 2) and the metal wire 38 for connection
An output signal is taken out from (output terminal 165 in FIG. 2).

Although the lengths of the first connecting metal wiring 17 and the second connecting metal wiring 37 in FIG. 1 are unbalanced, they are not intentionally unbalanced.
When the peripheral circuits other than the differential amplifier circuit, such as the current source 163 and the bias voltage source 162, are integrated, the resulting unbalanced state is depicted due to the layout.

Next, the operation of the circuit will be described based on the equivalent circuit of FIG. The voltage Vo at the output terminal 164 of the differential amplifier circuit of FIG.
The gain G151 between the input signal source 161 and 51, the phase difference P151, the gain G152 between the voltage Vo52 of the output terminal 165 of the differential amplifier and the input signal source 161, and the phase difference P152 are the resistances of the load resistors 154 and 155. If the value is Rc, the current value of the current source 163 is Io, and the impedance value of the coupling capacitor 160 for the input signal is sufficiently lower than the output impedance of the input signal source 161,

[0047]

[Formula 9] G151 =-(Rc + R11 + ωL11) / (4Vt / Io)

[0048]

## EQU10 ## G152 = (Rc + R12 + .omega.L12) / (4Vt / Io).

Here, "-" of G151 means that the phase of the output signal is opposite to the input signal, ωL11 is impedance 2πfL11 at frequency f, ωL12 is impedance 2πfL12 at frequency f, and Vt is kT. / Q
Where k is the Boltzmann constant, T is the absolute temperature, q is the charge of electrons, and Vt is about 26 mV at room temperature.

Next, referring to FIGS. 1 and 2, the operation will be described. In FIG.
A constant current is applied to the common emitter connection point of 1, 152, and a common bias voltage from a voltage source 162 is applied to their bases through resistors 156 and 157. 1/2 of the current value of 163
Operates with a large emitter current. The signal source 161 generates an AC signal and supplies the AC signal between the bases of the transistors 151 and 152 via the coupling capacitor 160. Then, the transistors 151 and 152 amplify the AC component of the collector current according to the AC input signal. Since the AC components of the collector currents of the transistors 151 and 152 have the same amplitude and opposite phases, at the midpoint 39 of the connecting metal wirings 19 and 20 for commonly connecting the load resistors 7 and 27 in FIG. Two
The two alternating currents are offset, and the current flowing through the connecting metal wiring 40 becomes the same direct current as the current source 163. Therefore,
The metal wiring 40 for connecting the power supply has an inductance component L13.
Even if it has (178), since an alternating current does not flow in the metal wiring, the voltage drop due to the resistance component R13 (179) causes the potential at the midpoint 39 to slightly decrease,
That does not directly affect the AC operation of the differential amplifier circuit.

On the other hand, for the AC operation, the output amplitude of the first output terminal 164 (the connecting metal wiring 8 in FIG. 1 ₎ is equal to the AC component Ic _{1 (AC)} of the collector current of the transistor 151.
It is determined by the product of the impedance from the contact window 12 to the midpoint 39 in FIG. 1, and the output amplitude of the second output terminal 165 (metal wiring 38 for connection in FIG. 1) is the collector current of the transistor 152. AC component Ic _{2 (AC)} and contact window in Fig. 1
Determined by the product of impedance from 32 to midpoint 39,
The gain G151 between the signal source 161 and the output terminal 164 and the gain G152 between the signal source 161 and the output terminal 165 are expressed by the above-mentioned (Equation 9) and (Equation 1).
It depends on 0).

Therefore, the first embodiment shown in FIG.
Even if the lengths of the metal wiring 17 for connection and the metal wiring 37 for connection are different, the metal wires 19 and 20 for connection have the same shape, such as length and line width, so that the output from the midpoint 39. Terminal 164, 165
The impedances up to are equal and a well-balanced differential output amplitude is obtained. Also, the metal wiring 40 for connection is
Since only a direct current flows, if the voltage drop of the resistance component R13 (179) can be ignored, the line width of the minimum rule determined by the processing accuracy of the manufacturing process does not matter.

In the above description, the differential amplifier circuit having a one-stage structure has been described. However, when a differential amplifier circuit having the same structure is connected in cascade to obtain a high gain, the differential amplifier circuits are extended from the power supply pad and extended. If the wiring corresponding to the metal wiring 40 for connection of each circuit block is connected to the power supply backbone wiring 40 'for supplying the power supply voltage to the circuit block, the power supply backbone wiring 40'
It is possible to avoid superposition of alternating current at. When the differential amplifier circuits are connected in cascade, mixing of an AC signal from the differential amplifier circuit on the rear stage side to the differential amplifier circuit on the front stage side is avoided, and waveform distortion, crosstalk, and a feedback loop via the power line are avoided. It is possible to realize high-gain differential amplification without causing problems such as an oscillation phenomenon due to.

In the above embodiment, all the metal wirings for connection are made up of only one wiring layer, but the first wiring layer and the second wiring layer are combined. It is also possible to use. In this case, it is convenient to configure the connecting metal wirings 19 and 20 in FIG. 1 in the first wiring layer and the power supply backbone wiring 40 'in the second wiring layer.
For example, a through hole may be provided at the position of the middle point 39, and the metal wirings 19 and 20 for connection of the first layer and the power supply backbone wiring 40 ′ of the wiring layer of the second layer may be connected. Plays the same role as the connecting metal wiring 40 of the above embodiment, and the connecting metal wiring 40 is not necessary. In this case, the shape of the through hole should be the one with the minimum rule, and care should be taken so that the contact area between the first layer and the second layer does not become large. The power supply main wiring 40 ′ may be arranged in the same direction as the connecting metal wirings 19 and 20 or in the crossing direction, and the main wiring 40 ′ is arranged so as to straddle the blocks of the differential amplifier circuit. However, there is no problem. In addition, the layout is simplified by making a single-stage differential amplifier circuit into cells, arranging the same cells continuously, and commonly connecting them to the power supply backbone wiring 40 'arranged along them through through holes. There is also an advantage that you can.

Next, the values of R11, R12 and L11, L12 in the actual semiconductor integrated circuit of this embodiment are obtained. In the above (Formula 3), ρ = 16 mΩ, L = 60 μm, W = 10 μ
If m and n = 0, then R11 = R12 = 0.096Ω. As well
Substituting L = 60 μm and W = 10 μm in (Equation 4) yields L
11 = L12 = 2.98 (nH). Now, when the DC gain is obtained, the impedances ωL11 and ωL12 are 0Ω. Here, the resistance value Rc of the resistors 154 and 155 for the load is 200Ω, and the current source 163
If the current value Io of is 1 mA, G151 is 5.684 dB and G152 is
It will be 5.684 dB. Next, when the frequency is 200 MHz, the impedances ωL11 and ωL12 are 3.8Ω. Here, assuming that the resistance value Rc of the resistors 154 and 155 for loads is 200Ω and the current value Io of the current source 163 is 1 mA, G151 is 5.848 dB and G152 is 5.848d.
It becomes B.

As described above, according to the present embodiment, it is possible to provide a semiconductor integrated circuit which can take out two outputs of the differential amplifier, which are the positive phase output and the negative phase output, in a well-balanced manner.

FIG. 3 is a pattern plan view showing a part of a differential amplifier composed of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 3, the same parts as those of the first embodiment shown in FIG. 1 and the conventional example shown in FIG. 6 are designated by the same reference numerals, and different points from FIG. 1 will be mainly described.

In the second embodiment shown in FIG. 3, the metal wiring 17 for connection and the metal wiring 37 for connection have the same length, and
The impedance from 39 to the output terminals 164 and 165 is made more equal than that of the embodiment of FIG. 1 so that a well-balanced differential output amplitude can be obtained.

Further, when the metal wirings 8 and 38 for connection for output are taken out from the vicinity of the contact windows 11 and 31 of the collectors of the transistors 151 and 152 shown in FIG. 4 which is the equivalent circuit of FIG. In addition to balancing the shapes of the power source side connecting metal wirings 19 and 20 connected to one ends of the P type diffusion regions 7 and 27, the metal wirings 19 and 20 for connecting to the other ends of the P type diffusion regions 7 and 27 are connected. The metal wirings 17, 37 also balance the shapes such as the length and the line width.

In this way, the load resistance including the wiring material is balanced on the left and right, and a well-balanced differential output amplitude can be obtained as in the first embodiment.

Next, a description will be given by contrasting FIG. 3 which is a configuration diagram of a semiconductor integrated circuit in which a differential amplifier circuit is integrated with FIG. 4 which shows an equivalent circuit in consideration of line impedance of a metal wiring for connection.

First, the metal wiring 40 for connection in FIG. 3 is a wiring for power supply, and the power supply voltage from the voltage source 153 is at the midpoint 39.
And has a resistance component R13 (179) and an inductance component L13 (178). Then, at the middle point 39 as a boundary, the metal wires 19 and 20 for connection having the same quality are branched.

Next, the metal wiring 19 for connection in FIG. 3 connects the contact window 13 at one end of the P-type semiconductor region 7 (resistance for load of the transistor 151) in FIG. It is a wiring that connects the two and has a resistance component R11 (175) and an inductance component L11 (174).

Next, the metal wiring 20 for connection in FIG. 3 connects the contact window 33 at one end of the P-type semiconductor region 27 (resistance for load of the transistor 152) in FIG. It is a wiring that connects the two and has a resistance component R12 (176) and an inductance component L12 (177).

Next, the metal wiring 17 for connection in FIG. 3 includes a contact window 12 at the other end of the P-type semiconductor region 7 in FIG. 3 and the first NPN transistor 1 (transistor 1 in FIG. 4).
51) is a wiring that connects between the collector contact window 11 and the resistance component R3 (181) and the inductance component L.
3 (180).

Next, the metal wiring 37 for connection in FIG. 3 includes the contact window 32 at the other end of the P-type semiconductor region 27 in FIG. 3 and the second NPN transistor 21 (transistor 1 in FIG. 4).
52) is a wiring connecting between the collector contact window 31 and the resistance component R4 (183) and the inductance component L.
4 (182).

Next, the metal wiring 15 for connection in FIG. 3 has a contact window 9 for the emitter of the first NPN transistor 1 and a contact window 29 for the second NPN transistor 21.
And are commonly connected, and the current of the current source 163 is supplied.

The metal wiring 16 for connection in FIG. 3 is
First NPN transistor 1 (transistor 1 in FIG. 4
51) is a wiring for base input, and the metal wiring 36 for connection in FIG. 3 is a wiring for base input of the second NPN transistor 21 (transistor 152 in FIG. 4). Input signals are obtained from the metal wirings 16 and 36 for connection, and output signals are taken out from the metal wiring 8 for connection (output terminal 164 in FIG. 4) and the metal wiring 38 for connection (output terminal 165 in FIG. 4). .

As described above, this embodiment is suitable for integration because the lengths of the metal wirings 17 and 37 for connection including peripheral circuits other than the differential amplifier circuit are balanced.

The gain G151 between the voltage Vo51 at the output terminal 164 and the input signal source 161 of the differential amplifier constructed as shown in FIG.
The voltage Vo52 at the output terminal 165 of the differential amplifier and the input signal source 161
The gain G152 between the resistance values of the resistors 154 and 155 for the load is R
c, the current value of the current source 163 is Io, and the impedance value of the coupling capacitor 160 with respect to the input signal is sufficiently lower than the output impedance of the input signal source 161.

And

G151 =-(Rc + R11 + ωL11) / (4Vt / Io)

[0072]

## EQU12 ## G152 = (Rc + R12 + ωL12) / (4Vt / Io).

Here, "-" of G151 indicates that the phase of the output signal is opposite to that of the input signal, and ωL11 is the frequency f.
Impedance 2πfL11, ωL12 at frequency f
In this case, the impedance 2πfL12, Vt is represented by kT / q, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge amount, and Vt is about 26 mV at room temperature.

Next, R11 and R12 in an actual semiconductor integrated circuit
And the values of L11 and L12 are obtained.

In (Equation 3), ρ = 16 mΩ, L = 60 μm,
If W = 10 μm and n = 0, then R11 = R12 = 0.096Ω. Similarly, by substituting L = 60 μm and W = 10 μm in (Equation 4), L11 = L12 = 2.98 (nH). Now, when the DC gain is obtained, the impedances ωL11 and ωL12 are 0Ω. When the resistance value Rc of the load resistors 154 and 155 is 200Ω and the current value Io of the current source 163 is 1 mA, G151 is 5.684 dB, G
152 becomes 5.684 dB. Next, when the frequency is 200 MHz, the impedances ωL11 and ωL12 are 3.8Ω. The resistance value Rc of the load resistors 154 and 155 is 200Ω, and the current value Io of the current source 163 is
Is 1 mA, G151 is 5.848 dB and G152 is 5.848 dB.

As described above, according to this embodiment, it is possible to provide a semiconductor integrated circuit which can take out two outputs of the differential amplifier, which are the positive phase output and the negative phase output, in a well-balanced manner.

In this embodiment, the differential amplifier is constructed by NPN type transistors, but it may be constructed by PNP type transistors or MOS transistors.

Further, in the above embodiment, the differential amplifier has been described as an example, but it goes without saying that the present invention can be widely applied to the case where it is used in a current mirror circuit.

[0079]

According to the present invention, there is provided a first differential amplifier circuit.
The collector of the transistor and the first load resistance are connected by the first wiring material, and the collector of the second transistor and the second load resistance are connected by the second wiring material. further,
The first load resistance and the second load resistance are connected by a third wiring material and connected to a power supply point, and the width and shape of the wiring material from the vicinity of the center of the third wiring material to the first load resistance. , The width and shape and size of the wiring material from the vicinity of the center of the third wiring material to the second load resistance are made substantially the same, and the contact portion between the first wiring material and the first load resistance is Since the shape and size and the shape and size of the contact portion between the second wiring material and the second load resistor are made substantially equal to each other, the positive-phase output and the negative-phase output of the differential amplifier can be obtained. It is possible to provide a stable semiconductor integrated circuit that can take out two outputs in a well-balanced manner.

[Brief description of drawings]

FIG. 1 is a pattern plan view showing a part of a differential amplifier composed of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the semiconductor integrated circuit of FIG.

FIG. 3 is a pattern plan view showing a part of a differential amplifier composed of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the semiconductor integrated circuit of FIG.

FIG. 5 is a circuit diagram of a conventional differential amplifier.

FIG. 6 is a pattern plan view of a differential amplifier configured by a conventional semiconductor integrated circuit.

7 is an equivalent circuit diagram of a differential amplifier of the conventional semiconductor integrated circuit shown in FIG.

FIG. 8 is a plan view of the metal wiring for connection shown in FIG.

[Explanation of symbols]

1, 21 ... NPN type transistor, 2, 22 ... N type epitaxial layer, 3, 4, 23, 24 ... P type semiconductor region,
5, 6, 25, 26 ... N-type semiconductor region, 7, 27 ... Load resistance composed of P-type semiconductor region, 9, 10, 11, 12, 13,
29,30,31,32,33 ... Contact window, 8,15,16,1
7, 18, 19, 20, 36, 37, 38, 40 ... Metal wiring for connection,
14, 34 ... Semiconductor resistance element, 40 '... Basic wiring for power supply,
111, 112, 151, 152 ... Transistor, 113, 153 ... Voltage source, 114, 115, 154, 155 ... Load resistance, 116, 1
17, 156, 157 ... Bias resistor, 120, 160 ... Coupling capacitor, 121, 161 ... Signal source, 122, 162 ... Bias power source, 123, 163 ... Current source, 124, 125, 164, 165 ...
Output terminal.

Claims (3)

[Claims] 1. In a semiconductor integrated circuit, a collector of a first transistor and a first load resistor forming a differential amplifier circuit are connected by a first wiring material, and a collector of a second transistor and a second load resistor are connected. The load resistance is connected by a second wiring material, the first load resistance and the second load resistance are connected by a third wiring material, and they are connected to a power supply point. The width, shape, and size of the wiring material from the vicinity of the center to the first load resistance and the width, shape, and size of the wiring material from the vicinity of the center of the third wiring material to the second load resistance are substantially the same. And the shape and size of the contact portion between the first wiring material and the first load resistor and the shape and size of the contact portion between the second wiring material and the second load resistor are substantially the same. A semiconductor integrated circuit having the above-mentioned configuration. 2. The width of the first wiring material and the second wiring material,
2. The semiconductor integrated circuit according to claim 1, wherein the shape and the shape and size of the contact portion with the first load resistance and the second load resistance are formed to be substantially the same. 3. The semiconductor integrated circuit according to claim 1, wherein the output of the differential amplifier circuit is taken out from a wiring material as close as possible to the collectors of the first and second transistors.