JPH0820912B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, in which the characteristics of a filter, a phase circuit, etc. are corrected or desired by detecting a variation value of the element characteristics. It is a circuit designed to have characteristics.

(Problems to be Solved by Conventional Techniques and the Invention) As the degree of integration of semiconductor circuits increases, there is a tendency to realize circuits that also include filters and phase circuits. However, as is well known, the characteristics of elements on a semiconductor substrate (hereinafter referred to as a semiconductor chip) can be made with high accuracy between elements of similar type, but the absolute value characteristics of each element are large. Even if it fluctuates, the characteristics of the filter, the phase circuit, and the like fluctuate even if it is made into an IC, which is inferior to that of the configuration using discrete components. For this reason, the use of ICs has the advantage of simplifying the configuration of electronic circuits by reducing the number of peripheral components, but there is the problem that ICs cannot be used to obtain filters or phase circuits with stable characteristics or within certain characteristics. .

Therefore, an object of the present invention is to obtain a semiconductor integrated circuit having a characteristic stabilizing circuit that can automatically correct the characteristic deterioration due to the variation factor element even when the filter, the phase circuit, and the like are integrated into an IC.

[Structure of the Invention] (Means for Solving Problems) In the present invention, for example, as shown in FIG. 1, a controlled element including a variation factor element (resistor and / or capacitor) formed on a semiconductor substrate 1 is controlled. A control circuit (detection circuit) that generates an output proportional to the value of the variation factor element formed on the same semiconductor substrate 1 in order to suppress the variation of the characteristics due to the variation of the value of the variation factor element of the circuit (functional circuit) 2. 3 is provided and the functional circuit is controlled by this output to reduce the fluctuation of the characteristics.

(Operation) By the above means, the characteristics of the controlled circuit (filter, phase circuit, etc.) are controlled to characteristics within a predetermined range by desired correction and switching, and the accuracy of the characteristics is improved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the simplest controlled circuit, for example, a low pass filter (hereinafter referred to as LPF), and FIG. 3 shows an example of a low pass active filter.

P ₁ and P ₂ are the input and output pins respectively, and the signals e ₁ and
Considering the signal e ₂ at the output, the characteristics of each circuit are as follows. However, the part number also indicates the characteristic value.

In the circuit of FIG. In the circuit of FIG. However, ω is 2π and angular frequency On the semiconductor chip, the resistance value and the capacitance value of the resistor R and the capacitor C respectively fluctuate greatly (variation) in the manufacturing process, for example, there is a fluctuation range of 30%. Moreover, since the values of R and C vary independently, the frequency characteristics and phase characteristics of each circuit vary greatly as is apparent from the equations (1) and (2). Therefore, if each circuit realizes a certain function, the effect is large and the function is impaired.

Now, as a method of expressing a variable in which R and C independently change by one variable T, think of. T is the ratio between the resistance value and the impedance value of the capacitor. Applying the variable T to equation (1), However, T ₃ = ωC ₃ R ₃ This value of T ₃ will fluctuate within a certain range in semiconductor manufacturing.

FIG. 4 is a simple example for explaining the basic operation of the present invention. The output e _OSC of the reference oscillator OSC has a constant amplitude and is input to the base of the transistor Q ₂ of the transistor amplifier A. Transistor Q ₂ is a constant current source I _s1 is connected to the emitter, the capacitor C _X1 is connected in parallel thereto. The collector of transistor Q ₂ is connected to current V _CC via resistor R _X1 . The output e _X of the collector is added to the amplitude detector DET to obtain a detection DC signal E _C proportional to the amplitude. SW ₁ is a switch for connecting the LPF of the same type shown in FIG. 2 and resistors R _3a , R _3b , R _3c of F ₁ shown in FIG. 2 to the capacitance C ₃ , and depending on the signal E _C , contacts a, b, Switch c.

From the figure However, T _X1 = ω _{C X1} R _X1 E _C is a value proportional to T _X1 .

Characteristics of the filter F ₁ is the common but is expressed by equation (4), switched T ₃ within the following three by the switching of the switch SW _1.

T _X1 and T _a3 , T _ab , and T _3c fluctuate in the same direction at almost the same rate.

FIG. 5 is a diagram showing the correspondence between the fluctuations of T _X1 , T _3a , T _3b and T _3c and the switching of the switch SW ₁ . The center values of T _X1 , T _3a , T _3b , T _3c which do not change are T _X1O , T _3aO , T _3bO , T _3cO
And Further, T _3aO <T _3bO <T _3cO is set.

Further, for convenience of explanation, the following schematic representation is made. That is,
_Set T _X1O = T _3bO . _T 3aO, T 3cO its variation width T _3BO and size are different assumed to be equal. It is assumed that the plus and minus fluctuation widths of each T are also equal.

Now, as shown in FIG. 5, the fluctuation is ΔT _P and the fluctuation width is ± ΔT _P1 with T _3bO as a reference. When T _X1 fluctuates, that is, when ΔT _P fluctuates, the switch SW ₁ switches to each contact of a, b, and c.

In the section B (-ΔT _P3 <T _P <ΔT _P3 ) shown in FIG. 5, the switch SW ₁ is switched to the contact b, and the section A (ΔT _P3 ≤ΔT _P ≤
In the case of ΔT _P1 ), the contact point b is switched to the contact point a, and the section C (−ΔT
_{When P1} ≦ ΔT _P ≦ −ΔT _P3 ), the contact b is switched to the contact c. Here, set T _3bO −T _3aO = ΔT _P2 , T _3cO −T _3bO = ΔT _P2 , , The correction of T is in a mode as shown in FIG. That is, Fig. 5 (a) shows the fluctuation of T _X1 , and Fig. 5 (b) shows T _X1 .
The variation of _3b and T _3a is shown in relation to T _3, and the figure (c) shows T _3b and
The variation of T _3a is shown in relation to T ₃ . (D)
Shows the variation of T ₃ after correction.

Now, it is assumed that the fluctuations of T _X1 and the resistances R _3a and R _3b are the same.
If T _x1 fluctuates and changes to the q ₁ point (marked with a circle) in the figure, that is, to + ΔT _P3 , T _3b and T _3a also fluctuate. Here, when the switch SW ₁ is switched from R _3b to R _3a , the variation position of T _3a is the variation position −ΔT _P3 indicated by the circle in FIG. 5 (b). Therefore, the variation of T ₃ is the lower limit of the B region.

Even if T _X1 further fluctuates in this state and reaches r ₁ point (□) shown in the figure, that is, ΔT _P1 , the fluctuation of T _3a falls within the upper limit of the B region.

Conversely, T _X1 fluctuates in the direction of −ΔT _P3 , and now q ₂ points (marked with ○)
Is located at Now switch SW ₁ from R _3b to R _3c
When is switched, the fluctuation position of T _3c is the fluctuation position ΔT _P3 indicated by the circle mark in FIG. 5 (c). Thus variation of T ₃ is the upper limit of the B region.

Even if T _X1 further fluctuates in this state and changes to the illustrated _r2 point (square mark), that is, -ΔT _P1 , the fluctuation of T _3c falls within the lower limit of the B region.

In other words, when only R _3b is used for filter F ₁ ,
There is a variation in all sections of A, B, C (± ΔT _P1 ),
By appropriately selecting R _3a and R _3c , it can be suppressed within the section B (± ΔT _P3 ) and the width of fluctuation can be reduced to about 1/3. Therefore, the characteristic variation of the filter can also be stabilized in proportion thereto. In the embodiment of FIG. 4, switching is performed with three contacts, but if the number of switching is further increased, the fluctuation range can be reduced.

FIG. 4 shows a control signal generated by generating a control signal proportional to a variable that fluctuates in the same direction at substantially the same rate as the variable that determines the filter characteristic, and stabilizes the filter characteristic by this signal. In addition to this, various circuits can be implemented for the circuit for generating and the circuit for changing the filter characteristic.

FIG. 6 is another circuit example for controlling the variable T of the filter. The capacitance value may be changed by the control voltage E _C using the junction capacitance of the variable capacitance diode C ₃ . When the range of change of the variable capacitance diode C ₃ is small, different variable capacitance diodes C _3a and C _3b are provided as shown in FIG. 7, and the change range of the capacitance is equivalently expanded by switching with the switch SW _2. You can also

FIG. 8 shows another embodiment of a circuit for obtaining a control signal proportional to the variable T.

This is an example of a differential amplifier type using transistors Q ₃ and Q ₄ . A capacitor C _X1 is connected between the emitters of the transistors Q ₃ and Q ₄ , and current sources I _S2 and I _S3 are connected between the respective emitters and the ground. The collectors of the transistors Q ₃ and Q ₄ are _supplied with power via resistors R _Xa and R _Xb , respectively.
Is connected to V _CC, to the base of the transistor Q ₃ is an oscillator OSC
Output, to the base of the transistor Q ₄ are the bias V _B1 is applied. The collector of each transistor Q ₃ and Q ₄ has
A signal proportional to ω C _X1 R _Xa and ω C _X1 R _Xb can be taken out, and this signal is supplied to the amplitude detector DET.

FIG. 9 shows a circuit of the type in which the circuit of FIG. 4 is connected in series between a power supply and ground. That is, Q ₅ and Q ₆ are transistors and I
_S4 and I _S5 are constant current sources, C _X1 and C _X2 are capacitors, and R _X1 and R _X2 are resistors.

According to this circuit, at the input of the amplitude detector DET, However, T _X1 = jωC _X1 R _X1 , T _X2 = jωC _X2 R _X2 (9) Here, since T _X1 and T _X2 fluctuate in the same direction and at the same rate, It can be melted. Therefore, in the equation (9), e _X = −KT _X1 ² · e _OSC (11) In the case of the circuit of FIG. 9, a signal proportional to the square of the variable can be obtained, and even if the fluctuation is small, A large control signal can be obtained, and it is effective for making a fine discrimination.

FIG. 10 is a circuit for detecting a change in C and R as a variable of T = C · R. Figure 10 shows the basic principle and the signal waveform of each part. The pulse T _g is applied to the terminal P _4, and the switch SW ₃ is closed and the switch SW ₄ is opened during the application period of T _g . T _g
Has a pulse duration t ₁ and time t ₂ until the next pulse as shown in Figure No. 10 (a).

During the application period of the pulse T _g, the current I _SX is charged in the capacitor C _X3 from the current source I _SX . BF is a buffer circuit and its input impedance is sufficiently large. The voltage V _CX3 across the capacitor C _X3 is as shown in FIG. 10 (b). the period of t _1, And becomes the maximum value at the last time of t ₁ , and the value of equation (12) at this time is passed through the buffer circuit BF to the capacitor C _X4
It is charged at high speed, and both ends of C _X4 become V _CX3 = V _CX4 . Next, at the start of the period of t ₂ , the pulse Tg disappears, the switch SW ₄ closes, and the switch SW ₃ opens. Therefore, the electric charge of the capacitor C _X3 is discharged and V _CX3 = 0. At the same time, the buffer circuit BF is cut off, and the electric charge of the capacitor C _X4 is discharged from the terminal P ₃ to the circuit of the next stage. At this time, if sufficiently large input impedance of the next-stage circuit to obtain a DC voltage proportional to the almost V _CXT1 as in FIG _(C).

In equation (12), I _S4 is K _SK ; If set as a proportional constant, Therefore, it is possible to obtain V _CR proportional to the fluctuation of C _X3 and R _SX .

It is necessary to make V _CC , t ₁ stable.
V _CC may alternatively use a voltage source that does not depend on the power supply.
According to the above method, the oscillator is unnecessary.

 FIG. 11 is an embodiment of another CR value detection circuit.

The switches SW ₃ , SW ₄ , and SW ₅ are provided in FIG. 11 (a), (b),
When the gate pulses T _g1 , T _g2 , T _g3 as shown in (c) are applied and the pulse waveform in the figure is at the high level, the switch is turned on. That is, when the gate pulse T _g1 is applied,
The switch SW ₃ is on, the switches SW ₄ and SW ₅ are off, and the current I _SX flows through the capacitor C _X3 as a charging current for a period of t ₁ . The current I _{SX at} this time is expressed by equation (13). At this time, the voltage V _CX across the capacitor C _X3 is
11 Ascends as shown in Fig. 11 (d). Then after the end time of t _1, the switch SW ₃ is turned off, the switch SW ₅ is turned in the period of t _3. If the input impedance of the buffer circuit BF is sufficiently high, the value of the voltage V _CX remains held as shown in FIG. 11 (d). During this time, V _CX is output to the buffer circuit BF.
And the capacitor C _X4 is charged to produce a voltage equal to V _CX . (See waveform in FIG. 11 (e)).

Next, when the pulse T _g3 arrives, the switch SW ₄ turns on,
Switch SW ₅ turns off. Therefore, the electric charge of the capacitor C _X3 is discharged through the switch SW ₄ , and the voltage V _CX becomes the ground potential. By contrast switch SW _5, and the path is off the capacitor C _X4, capacitor C _X4 is discharged to the next stage of the input circuit, by increasing the input impedance of the next stage circuit, seen in FIG. (E) So that the potential of the output terminal P ₃
V _P3 can be held at a value approximately equal to V _CX in the high voltage state. V _CX is a function of C _X3 , R _S3 as shown in equation (14).

FIG. 12 is a circuit diagram showing the circuit of FIG. 10 more specifically. Portions corresponding to those in FIG. 10 are designated by corresponding reference numerals.

Transistors Q _8, Q ₉ is a differential amplifier type switches forming the switch SW _3, the collector of the transistor Q ₇ to the interconnection emitter of the transistor Q _8, Q ₉ is connected, the emitter of the transistor Q ₇ is resistance Connected to ground through R _X3 . The series circuit of the resistor R ₅ , the diodes D ₄ , D ₂ and the resistor R ₆ is a base bias setting circuit of the transistor Q ₇ for flowing a predetermined current through the resistor R _X3 . Diodes D ₁ and D ₂ are
Each is actually a composite diode in which m and n diodes are connected in series. A predetermined bias V _B2 is applied to the base of the transistor Q ₉ , and a gate pulse T _g from the input point P ₄ is applied to the base of the transistor Q ₈ . During the high level period of the pulse T _g , the transistor Q ₈ is conductive and the transistor Q ₉ is in the cutoff state. When there is no pulse T _g , that is, during the low level period, the transistor Q ₈ is off,
Transistor Q ₉ is turned on.

Transistors Q _10, Q ₁₁ and Q _12, Q ₁₃ form a current mirror circuit, respectively, to convert the collector current of the transistor Q _8, Q ₉ and flows out from the collector of the transistor Q _11, Q _13.

Transistors Q ₁₄ and Q _{15 form} a current mirror circuit, the collector of transistor Q ₁₃ is connected to the base and collector of transistor Q ₁₄ , and the collectors of transistors Q ₁₁ and Q ₁₅ are both the base of transistor Q ₁₆ and capacitor C _X3.
Connected to one end of. The other end of the capacitor C _X3 is grounded. The collector current of the transistor Q ₁₃ is current-converted by the transistors Q ₁₄ and Q ₁₅ , and the difference current flowing in the collectors of the transistors Q ₁₁ and Q ₁₅ is supplied to the capacitor C _X3 as a charging current.

The transistor Q ₁₆ acts as a buffer circuit BF, and the emitter is grounded via the capacitor C _X4 and connected to the base of the transistor Q ₂₀ . The transistors Q ₁₉ , Q ₁₇ , and Q ₁₈ are compensating circuits for the base current of the transistor Q ₂₀ . The collector of the transistor Q ₂₀ is connected to the emitter of the transistor Q _19, the transistor Q ₁₉
Collectors are grounded. Transistors Q ₁₇ and Q ₁₈
Is a current mirror circuit, and converts the base current of the transistor Q ₁₉ to the collector of the transistor Q _18. Therefore, by the collector of the transistor Q ₁₈ is connected to the base of the transistor Q _20, likely draw collector current of the transistor Q ₁₈ that approximates the base current of the transistor Q _20, a charging current to the capacitor C _X4 I am making it small. The transistor Q ₁₆ turns on when the transistor Q ₈ turns on, and transfers the potential of the capacitor C _X3 to the capacitor C _X4 .

The emitter of the transistor Q ₂₀ is supplied with the current from the constant current source I _S6 . The transistors Q ₂₀ and Q ₂₁ are emitter follower circuits using complementary transistors, and apply a voltage substantially equal to the base potential of the transistor Q ₂₀ to P ₃
Output to.

The operation will be described below. During the arrival period of the gate pulse T _g , the transistor Q ₈ is on and the transistor Q ₉ is off, so that the collector current of the transistor Q ₁₁ is equal to the current flowing through the resistor R _X3 and the transistor Q ₁₅
Since it is cut off, the collector current of the transistor Q ₁₁ is charged in the capacitor C _X3 . Transistor Q ₁₁
The collector current of, that is, the current I _RX3 flowing through the resistor R _X3 is However, V _F is assumed here base-emitter forward voltage of the diodes and transistors If you choose I _RX3 is charged in the capacitor C _X3 , and its charging time is the gate pulse width t ₁ , the voltage V across the capacitor C _X3
CX3 is Since t ₁ , V _CC , and the ratio of R ₅ and R ₆ can be given stably, It can be melted.

When V _CX3 is applied to the base of the transistor Q ₁₆ , the charging action on C _X4 is instantaneously performed until the voltage reaches almost this voltage. Strictly speaking, between the emitter and the base of the transistor Q ₁₆ , the impedance increases as the charging voltage V _{CX4 of} C _X4 approaches V _CX3 , so V _CX4 does not become exactly equal to V _CX3 , but it is practically almost equal. It can be melted.

Therefore, in the emitter of the transistor Q ₂₁ Is established.

Next, when the gate pulse disappears, the transistor Q ₈
Turns off and transistor Q ₉ turns on. In this case, the transistor Q ₁₁ is turned off, the transistor Q ₁₅ is turned on, the charge of the capacitor C _X3 is discharged through the transistor Q _15, the approximately V _CX3 transistor Q ₁₅ is saturated eventually to ground potential Reach At this time, the emitter of the transistor Q ₁₆ is at the level of equation (19), and its base is at the ground potential, so this transistor Q ₁₆ is cut off. The charged electric charge of the capacitor C _X4 is substantially held, and the voltage of formula (19) is held until the arrival of the period of the next gate pulse. Therefore, the potential of formula (20) always appears in P ₃ .

FIG. 13 shows a circuit state in which the output of the circuit of FIG. 10 is further developed and used. For P ₃ , C given by equation (20)
Obtain an output that is inversely proportional to _X3 , R _X3 . A ₁ is an inverse function unit, and a filter F is connected to its output point P ₅ . Filter F is an example of the same LPF as the second view, C ₃ control signal from P ₄ is applied to one end a capacitor formed by the junction capacitance. It is assumed that C _{X3 in} Eq. (20) also has a junction capacitance.

Assuming that the junction capacitance of the semiconductor is a junction capacitance utilizing a reverse bias between the base and the emitter, the capacitance C depends on the voltage V _C across the capacitor. That function is generally Shown in the form of. K ₂ is a deciding factor for obtaining a predetermined capacity, and varies depending on changes in manufacturing processes.

Therefore, from equation (21), C _X3 , C ₃ is It can be melted. However, K _X3 and K _C3 are the capacity setting coefficients, and V
_X3 and V _C3 are applied voltages across C _X3 and C ₃ , respectively.

Substituting equation (22) into equation (20), Therefore If the relationship of A ₁ is K ₃ / _X (K ₃ is a proportional coefficient, _X is an input),
The output V _A1 of this inverse function unit is Assuming that the value of V _A1 is equal to the voltage across C ₃ , V _A1 = V _C3 (26) Therefore, from equations (26) and (25) From equation (5) Becomes

K ₁ can be treated as a constant value from Eq. (19). K ₃ is 2 of voltage
It is the dimension of the power, and the voltage can be set as a constant value because it can be set by dividing the value of V _CC as a basic value (which can be made by the value of resistance ratio).

Therefore, ω · (K ₁ / K ₃ ) is a constant coefficient.

The ratio of both K _C3 and K _X3 is constant even if they individually change depending on the coefficient of the junction capacitance. R ₃ and R _X3 are both resistors,
Similarly, it becomes constant.

T ₃ This result may be a constant value irrespective of the fluctuation of the element.

Junction capacitance C _J are generally as follows by the applied voltage V _C.

K _J is a coefficient determined by the capacitance setting, and m is a value determined by the junction structure. In the general case as shown in Eq. (28), the compensation system is as shown in Fig. 14.

In FIG. 14, the output of the element characteristic variation detection circuit A ₂ that obtains an output proportional to the product of the capacitor C _X and the resistor R _X is
It is processed by the (m-1) th function circuit A _{3 of the} inverse function, and its output is added to a part or all of the capacitors which determine the characteristics of the desired filter or phase circuit A ₄ . A ₄ figure 6
The configuration is the same as that shown in FIG.

The output V _X of the detection circuit A ₂ has the following relationship.

The function of the inverse function circuit A ₃ is output as V _C C _T, R _T is assumed to capacitor A _4, any one Tsutoshi in resistance, V _C is applied to both ends of the C _T.

C _X and C _T are as follows from Eq. (28).

K _JX and K _JT are coefficients that determine the capacitance value. V _X is applied to both ends of C _X.

Substituting equation (30) into equation (29) and rearranging Substituting equation (32) into equation (30) Therefore And K _JT / K _JX is a value proportional to the ratio of the capacitance values, and R _T / R _X is a ratio of the resistance values and does not fluctuate in the manufacturing process.

FIG. 15 is a more specific example of the circuit of FIG. Further, as the detecting circuit A ₂ employs specifically illustrates the block structure of Figure 11.

The series circuit of resistors R ₈ and R ₇ has a transistor Q
Is connected to the _23-based, the emitter of the transistor Q _23, the collector and the transistor Q ₂₄ of the transistor Q ₂₂
Connected to the base of. The emitter of the transistor Q ₂₂ is grounded via a resistor R _10. A constant current flows at the time turned on to the transistor Q _22. The collector of the transistor Q _{24 is connected to} the base of the transistor Q ₂₆ , the collector of the transistor Q ₂₅ , and one end of the capacitor C _X3 . The other end of the capacitor C _X3 is grounded. The transistor Q ₂₅ has a gate pulse T _g applied to its base via the resistor R ₁₁ , and obtains a switching operation. When the gate pulse Tg ₁ is applied through the resistor R ₉ , the transistors Q ₂₂ , Q ₂₃ , Q ₂₄
Turns on, and transistor Q ₂₅ cuts off. Charging current flows through capacitor C _X3 when transistor Q ₂₅ is cut off. After charging for period t _{1 in} Figure 11, transistor Q
₂₂ , Q ₂₃ , Q ₂₄ are turned off, charging is completed, and charged voltage V _CX3
Is held until the gate pulse T _g2 is applied.

The voltage V _CX3 is applied to the base of transistor Q ₂₆ . The emitter of the transistor Q ₂₆ is connected to the collector of the transistor Q ₂₉ via the transistor Q _27, Q ₂₈ of the diode operation directly connected to the base-collector. The transistors Q ₃₀ and Q ₂₉ form a current mirror circuit, and the collector of the transistor Q ₃₁ is connected to the base and collector of the transistor Q _{30 and} the base of the transistor Q ₂₉ . Transistor Q ₃₁ has its base connected to the anode side of the transistor Q _28, its emitter, the base of the transistor Q _33, is connected to one end of the capacitor C _4. Capacitor
The other end of the C ₄ is grounded. The gate pulse T _g3 is supplied to the base of the transistor Q ₃₂ via the resistor R ₁₂ to obtain the switching operation. The transistor Q ₃₂ discharges the electric charge of the capacitor C ₄ when on, substantially the transistor Q
_Set the base of ₃₃ to ground potential.

Configuration of the transistors Q ₂₆ through Q _31, the transistor Q ₂₆
An emitter follower operation is obtained in which the base potential of is shifted by 2 V _F level and converted to the emitter of the transistor Q ₃₁ with low impedance. However, when the transistor Q ₃₂ is off, the emitter follower does not work, and it becomes cut off.
It functions as the switch SW ₅ shown in FIG. Transistor Q ₃₃ operates as an emitter follower.

The above is an explanation of the detection circuit A _2, then the inverse function circuit A ₃ will be described.

The emitter of the transistor Q ₃₃ is connected to the current mirror circuit composed of the transistors Q _34, Q ₃₅ through a resistor R _13. Current supplied to the base of the transistor Q _34, Q ₃₅ is, appears to be converted to the collector of the transistor Q _35. The collector of the transistor Q ₃₅ is connected via a transistor Q ₃₆ of the diode configuration is connected to the base of the emitter and the transistor Q ₃₈ of the transistor Q _37.

The base of transistor Q ₃₇ is connected to the emitter of the transistor Q _40, the base of the transistor Q ₄₀ is biased V
Connected to _B3 . Transistors Q ₃₈ and Q ₃₉ form a differential amplifier whose emitter is connected to a constant current source I _S7 , and the base of transistor Q ₃₉ is the emitter of transistor Q ₄₃ via diode-configured transistors Q ₄₁ and Q _42. Connected to the collector of transistor Q ₄₄ . Transistor Q ₄₃
The base of is connected to bias V _B3 .

The base of transistor Q ₄₄ is connected to the emitter of the transistor Q _45, the emitter of the transistor Q ₄₅ is connected to the constant current source I _S8, the base is connected to a bias is supplied to the connection point of the resistors R _15, R ₁₆ . The collector of the transistor Q ₃₉ is connected to the emitter of the transistor Q _40, substantially make equal the current flowing through the current and the transistor Q ₄₀ flowing through the transistor Q _39. The collector of the transistor Q ₃₈ is connected to the base and the collector of the transistor Q ₄₆ which constitute a current mirror circuit. The collector of the transistor Q ₄₇ is connected to a bias V _B4 via the resistor R _17, also connected to the base of the transistor Q _48. Transistor Q
The emitter of ₄₈ is connected to the constant current source I _S9 and
It is connected to one end of the capacitor C ₃ of the next-stage filter A ₄ .

 The operation of the above circuit is as follows.

Since the collector current of the transistor Q ₂₄ is charged to the capacitor C _X3 for the period of t _1, After I ₂₄ is cut off, V _CX3 is held for t ₃ period,
When the switch SW ₅ is turned on, the emitter potential of the transistor Q ₃₁ , that is, V _CX4 becomes V _CX4 = V _CX3 + 2V _F (37). C ₄ ends reach the emitter potential of the transistor Q ₃₁ by a quick charge. Charge of C ₄ is held by the off switch SW _5.

Therefore, the R ₁₃ at all times Flows.

I _R13 is current-converted by a current mirror circuit composed of transistors Q ₃₄ and Q ₃₅ and becomes equal to I _Q35 , I _Q36 and I _Q37 .
The code added to I indicates each element.

I _Q37 = I _Q3 = I _R13 (39) Next, I _Q36 (= I _Q37 ) and I flowing through the transistor Q _47.
Find the relationship with _Q47 .

The base-emitter voltage of the transistor Q _n is V _Fn , and the current is
_Given I _Qn , the following equation holds from the figure.

A path from V _B3 to the emitter of the transistor _{Q 40, Q 37, Q 36} , Q 38, since the potential of the path from V _B3 to the emitter of the transistor _{Q 43, Q 42, Q 41} , Q 39 equal, V _{F 46} + V _F37 + V _F36 + V _F38 = V _F43 + V _F42 + V _F41 + V _F39 (40) The base-emitter junction of the transistor is given by the following relational expression.

Where K is the Boltzmann constant, T is the absolute temperature, q is the electron charge, I _n (even equal substantially collector current) emitter current of the transistor, I _S is the saturation current of the transistor.

Transistors on the same semiconductor chip can be configured approximately, and assuming that each transistor is approximately equal to I _S (41)
Substituting into equation (40) using the equation yields the following.

I _Q40 / I _Q37 / I _Q36 / I _Q38 = I _Q43 / I _Q42 / I _Q41 / I _Q39 (4
2) where Substituting equation (43) into equation (42) Substituting equations (38) and (44) for calculation, the emitter of transistor Q ₄₈ Now choose the DC voltage applied to P ₁ as V _P1 = V _B4 −V _F (46). The voltage across C ₃ is V _{C3 Let} C _X3 , C ₃ be From equation (48) and equation (36) Put this in equation (47) So the variable Get.

By transforming the Distant K ₄ Becomes From Eq. (53), K ₄ is a value determined by the ratio of V _CC , t ₁ to resistance, and if V _CC , t ₁ is given constant, K ₄ can be given as a constant value. Therefore, (52) becomes T ₃ constant regardless of the element value.

If the filter of Fig. 3 is set as T ₁ = ωC ₁ R ₁ T ₂ = ωC ₂ R ₁ (54) from equation (2), Is determined by the ratio of C ₁ / C ₂ and R ₁ / R ₂ , so if T ₁ / T ₂ = K _T , then K
_T can be treated as a constant. Using K _T in Eq. (54), (2)
ceremony (56) as seen in equation characteristics of equation (2) because varies with T _1, can be corrected characteristic by controlling T _1. T ₁ can be changed by controlling C ₁ .
However, as can be seen from equation (55), the ratio between C ₁ and C ₂ needs to be kept constant, so both C ₁ and C ₂ need to be controlled.

FIG. 16 shows an embodiment for controlling the capacitor shown in FIG. Resistors R ₁ and R ₂ , capacitors C ₁ and C ₂ , transistors
Q ₁ and resistor R ₄ correspond to elements equivalent to the elements in FIG.
The emitter of the transistor Q ₁ is, via a resistor R ₄ is connected to the collector of the transistor Q _49, the emitter of the transistor Q ₄₉ is grounded via a resistor R _18. Transistor Q
₄₉ based is connected to a control terminal P _4. Transistor
The base of Q ₅₀ is connected to the connection point of the collector of the transistor Q ₄₉ and the resistor R ₄ , and the emitter is connected to the constant current source I _S10 . The emitter of the transistor Q ₅₀ is connected to one end of the capacitor C _1. The emitter signal of the transistor Q ₁ is,
The resistance R ₄ is fed back to the capacitor C ₁ via the transistor Q ₅₀ , and becomes equivalent to the case of FIG. A bias V _B5 is connected to the base of the transistor Q ₅₂ , and the emitter thereof is connected to the base of the transistor Q ₅₃ and the collector of the transistor Q ₅₁ via the resistor R ₂₀ . Transistor Q ₅₁
Its emitter is grounded through resistor R ₁₉ and its base is P ₄
Connected to. The emitter of the transistor Q ₅₃ is connected to the constant current source I _S11 and also connected to one end of the capacitor C ₂ . A signal proportional to C _X R _X applied to P ₄ changes the DC current of transistors Q ₄₉ and Q ₅₁ , which changes the voltage drop across resistors R ₄ and R _26. It is given to C ₁ and C ₂ and its capacitance value is changed. If the element values or bias conditions are set so that the voltages applied to both ends of the capacitors C ₁ and C ₂ are equal, the capacitance of C ₁ and C ₂ changes, but the ratio can always be kept constant. it can.

Other than the above, various detection circuits for detecting fluctuations proportional to C, R or CR (horizontal) on the semiconductor chip can be implemented. For example, FIG. 17 is a phase detection waveform detection circuit, and FIG. 18 is a vector diagram thereof.

In FIG. 17, P ₆ is an input terminal, P ₇ is a detection output terminal. A ₅ and A ₆ are differential amplifiers, and A ₇ is a multiplication circuit. When a constant continuous wave e _a is supplied to P ₆ , _a signal e _b appears at the element connection point of the series circuit of the resistor R ₂₁ and the capacitor C _{5, and} a signal at the element connection point of the resistors R ₂₂ and R _23. e _c appears. The signals e _b and e _c are supplied to the differential input section of the differential amplifier A ₆ . The signal e _c is also supplied to one end of the differential amplifier A ₅ . The outputs e _d and e _e of the differential amplifiers A ₅ and A ₆ are multiplication circuits A _{7 and}
Is supplied to.

 The phase relationship of the above signals is as shown in FIG.

The signal e _a is delayed by the resistor R ₂₁ and the capacitor C ₅ (for example, 45
)) And becomes the signal e _b . The signal e _c is the signal e _a when the resistors R ₂₂ and R
_When divided by ₂₃ , when it corresponds to 45 ° Equivalent to. Then, the difference between the signals e _c and e _b (e _{cb in the} figure)
Is amplified by the differential amplifier A ₆ and becomes a signal e _e . Further, e _c is amplified by the differential amplifier A ₅ and becomes a signal e _d . E _{e at a} given value
And e _d are at right angles. At this time, if an output after being multiplied by the multiplication circuit A ₇ and a smoothed output are generated, this is a 90 ° detection output.

Next, a case where the capacitor C ₅ and the resistor R ₂₁ change will be described. Delayed phase signal e _b is proportional to C ₅ × R _21, C ₅
When R ₂₁ and R ₂₁ fluctuate in the direction of increasing, the delay becomes large, and at this time, it becomes the signal e _b1 as shown in FIG.
Conversely, if it fluctuates in a small direction, it becomes a signal e _b2 .
Since the signal e _c is determined by the voltage division ratio of the resistors R ₂₂ and R ₂₃ , the e _c phase is constant regardless of the change in the resistance value. Therefore, the signal
e _e is caused by the difference between the signals e _c and e _b1 or the difference between e _c and e _b2 ,
The signals are e _e1 and e _e2 .

Therefore, if C ₅ or R ₂₁ fluctuates toward a larger value, e _e and e _d are multiplied by a relationship of less than 90 °, and if C ₅ or R ₂₁ fluctuates toward a smaller value, 90 °. Multiplied by a larger relationship, the output V _P7 at the output point P ₇ has the characteristic shown in FIG.

Therefore, it is possible to retrieve C _5, the direction of variation of the C _5, R ₂₁ around the output when the center value of the R _21, a detection output proportional to the magnitude. By using this detection output, the characteristics of the filter, the phase circuit, and the like can be compensated for to be stable.

The circuit of FIG. 17 may have a configuration in which the capacitor C ₅ and the resistor R ₂₁ are replaced. Further, the circuit formed by the resistor R ₂₁ and the capacitor C ₅ may be a phase circuit in general, and e _b at the input point of the differential amplifier A ₆ causes fluctuations in the values of the resistors and capacitors forming the phase circuit. It suffices to be converted into the phase fluctuation of the motion (e _b −e _c ) in proportion. Therefore, a circuit that satisfies this can be implemented in various ways, and is not limited to the circuit in FIG. Resistance R
_22, the series circuit of the R ₂₃ acts as a voltage divider circuit at the input and phase.

In the above description, the circuit for generating the control signal or the controlled circuit is not limited to this embodiment, and various embodiments are possible. As the controlled circuit, there are various correction targets such as the amplification degree, the current value, the phase, the frequency characteristic, the voltage value, and the input / output impedance.

[Effects of the Invention] As described above, according to the present invention, the following effects are obtained. It is possible to suppress fluctuations in circuit characteristics regardless of fluctuations in absolute values (C, R) of elements on a semiconductor integrated circuit, and to achieve stable and high reliability. Due to this performance, more circuits can be integrated into ICs than in the past.
It is economical because it improves the retention of IC. Easy to design for IC. No adjustment required. Fluctuations can be suppressed even with temperature changes, and the reliability of the circuit can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 each show a filter, FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. FIGS. 6 and 7 are diagrams each showing a controlled circuit of FIG. 1, FIGS. 8 and 9 are diagrams each showing an element variation detection circuit according to the present invention, 10 and 11 also show a specific example of the detection circuit and operation waveforms, respectively. FIG. 12 is a circuit diagram showing the circuit of FIG. 10 more specifically, and FIG.
FIG. 14 and FIG. 14 are diagrams showing still another embodiment of the element variation detection circuit, respectively, and FIG. 15 is a circuit diagram showing the circuit of FIG. 14 more specifically, FIG.
The figure is a circuit diagram showing still another example of the controlled circuit (filter), FIG. 17 is a circuit diagram showing an example of the detection circuit according to the present invention, FIG. 18 is a signal vector diagram of the circuit of FIG. FIG. 19 is a characteristic diagram of the circuit of FIG. 1 ... Semiconductor substrate, 2 ... Functional circuit, 3 ... Detection circuit.

Claims (4)

[Claims] 1. A circuit for obtaining predetermined electrical characteristics formed on a semiconductor substrate, comprising a resistance element and a capacitance element as variation factor elements, and at least the resistance and capacitance elements forming the circuit. A controlled circuit capable of controlling one value, the variation factor element forming the controlled circuit, or another variation factor element formed on the semiconductor substrate and having a characteristic proportional to the characteristic of the variation factor element A control circuit that generates a control signal that represents a variation in the value of the variation factor element that is used, and corrects a change in the electrical characteristic that accompanies the variation in the value of the variation factor element in the controlled circuit. Therefore, a correction unit that changes the value of at least one of the resistance and the capacitance element in response to a control signal from the control circuit is provided, and the characteristic of the controlled circuit changes. The semiconductor integrated circuit being characterized in that so as to suppress. 2. The semiconductor integrated circuit according to claim 1, wherein the capacitance element as the variation factor element is a variable capacitance diode. 3. The correction means equivalently changes the electrical characteristics of the variation factor element of the controlled circuit in response to the control signal. The semiconductor integrated circuit according to the item. 4. The controlled circuit includes a plurality of fluctuation factor elements, and the correction means includes a switch means for selecting any one of the plurality of fluctuation factor elements, and is responsive to a control signal from the correction means. 2. The semiconductor integrated circuit according to claim 1, wherein the switching means is controlled to select any one of the fluctuation factor elements.