JPH0822068B2 - Digital signal generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel digital signal generating circuit, and more particularly to a novel digital signal generating circuit capable of generating a digital signal of a plurality of bits whose digital value changes intricately with a very simple circuit configuration. It is intended to provide a digital signal generating circuit.

BACKGROUND ART With the development of digital signal processing technology, digital technology is becoming the mainstream in various fields of electronic technology, and for example, in color video cameras as well, there is a tendency to process images by digital technology. By the way, for example, when such image processing is performed by a digital technique, it is inevitably necessary to generate various digital signals. FIG. 1 shows a part of a so-called black burst signal required in a color video camera, that is, a video signal consisting of only a synchronization signal excluding video information. It is clear that it is necessary to generate a digital signal corresponding to an analog signal whose amplitude changes intricately.

Prior Art There are the following techniques for generating such a digital signal, for example, a black burst signal. This was filed by the applicant of the present application [Japanese Patent Application No. 197438 (1983)
No. 99085)], one black burst signal is decomposed into a plurality of signals, information about each pattern is stored in a memory, and information about each pattern is read out in a predetermined order to obtain one black. A burst signal is obtained. In this technique, even if a black burst signal having a complicated pattern is divided into time units of 1 / 2H (H; horizontal period), for example, signals of relatively few patterns are combined. According to this technique, a relatively small-capacity memory is provided, the information of each pattern signal is stored in each area of the memory, and the information of each pattern signal is read out in a fixed order. It is possible to obtain a black burst signal or other digital signals whose digital values change intricately.

However, providing the pattern signal storage memory and program control circuit in the color video camera
Not only when they are formed on an independent integrated circuit (IC), but also when they are formed on an IC on which a color encoder circuit and the like are formed, it becomes a factor for suppressing downsizing and cost reduction of the camera.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a novel digital signal generating circuit capable of generating a digital signal of a plurality of bits whose digital value changes intricately with an extremely simple circuit configuration.

In order to achieve the above object, the digital signal generating circuit of the present invention comprises a plurality of delay elements that shift one input signal of 1 bit, and has a plurality of output terminals connected to the output terminals of the respective delay elements. And a plurality of logic gates such as AND, OR, and / or knots, each of which has a plurality of input terminals, each input terminal being connected to one of the output terminals of the delay element, A logic circuit for forming a digital signal, which generates one digital signal consisting of bits at a plurality of output terminals for each bit,
The logic circuit is configured such that each time the input signal is shifted through the shift register bit by bit, the digital value of the digital signal of a plurality of bits output from the logic circuit changes according to a predetermined pattern. It is characterized in that logic gates are arranged.

Embodiment Hereinafter, a digital signal generating circuit of the present invention will be described in detail according to an embodiment shown in the accompanying drawings.

FIG. 2 is a block diagram showing the entire internal circuit of a color video camera using the digital signal generating circuit of the present invention as a part of a black burst signal generating circuit, wherein 1 is a solid-state image pickup device for obtaining an R signal component, Reference numeral 2 is a solid-state image sensor for obtaining a G signal component, and 3 is a solid-state image sensor for obtaining a B signal component, and these are, for example, CCDs. Discrete output signals R, G, B of the solid-state image pickup devices 1, 2, 3 are appropriately amplified by the preamplifiers 4, 5, 6 in sampling hold circuits 7, 8, 9 having both a sampling function and a waveform shaping function. It is sampled and input to the A / D converters 10, 11 and 12, where it is converted into a digital signal. The signals R, G and B converted into the digital signals are γ-corrected in the process circuits 13, 14 and 15.
Signal processing such as pedestal level adjustment, clamp, and clip is performed and the signal is input to the matrix 16. The matrix 16 outputs a luminance signal Y and chroma signals I and Q represented by Y = 0.30R + 0.59G + 0.11B I = 0.60R−0.28G−0.32B Q = 0.21R−0.52G−0.31B It is supposed to be done. Chroma signals I and Q are band limiting circuits
After being limited to a predetermined band in 17 and 18, it is input to the NTSC color encoder 19 together with the luminance signal Y. The color encoder 19 is: E = Y + Qsin (ωcsc · t + 33 °) + Icos (ωcsc · t +
33 °) (where ωcsc is the angular velocity of the color subcarrier signal) is used to obtain a signal E by adding the signal from the black burst signal generating circuit 20 to the signal E. It provides a desired pedestal level and serves to add horizontal and vertical sync signals H / V-Sync and burst signal Burst. Then, an NTSC composite signal is output from the color encoder 19, and this composite signal is converted into an analog signal in the D / A converter 21.

FIG. 3 is a block diagram showing the black burst signal generating circuit 20, in which 22 is a synchronizing pulse signal H / V-S.
23 is a burst flag signal, a digital sync signal generating circuit for obtaining an 8-bit digital sync pulse signal S from ync
It is a burst forming signal generating circuit which receives the Burst Flag and generates two digital signals BI for forming a burst. The digital signal BI has a digital value of the magnitude when the I component of the burst signal Burst having a predetermined level is sampled, and the digital signal ▲ ▼ also has a digital value of the magnitude when the component of the burst signal Burst is sampled. Have. 24 is a switching circuit which outputs digital signals BI and ▲ ▼ alternately by being controlled by a switching circuit signal Csc ′ having a frequency 2fcsc which is twice the frequency fcsc of the color subcarrier signal Csc, and 25 is output from the switching circuit 24. Is an exclusive OR circuit that receives the digital signals BI and ▲ ▼ that are output and the color subcarrier signal Csc. When the color subcarrier signal Csc is "0", the output signal of the switching circuit 24 is sent as it is, and the color subcarrier is output. Signal Csc is "1"
At the time of, it plays a role of inverting and outputting the output of the switching circuit 24. That is, the exclusive OR circuit 25 receives the digital signal BI, ▲ ▼ from the switching circuit 24 and outputs the digital signal BI, ▲ ▼, ▲ ▼, BQ when receiving the subcarrier signal Csc. B
It is for inverting I and ▲ ▼ by making their complements. It should be noted that eight exclusive OR circuits are provided corresponding to each bit of the digital signals BI and ▲ ▼, and each exclusive OR circuit receives the signal of the bit corresponding to one input terminal and receives the signal of the other. The input terminal receives the color subcarrier signal Csc, but in the drawing, one exclusive OR circuit 25 is used to represent eight. In order to invert the digital signals BI, ▲ ▼ by forming their 2's complement, it is not enough to invert each bit signal of the digital signals BI, ▲ ▼ by the exclusive OR circuit 25. Although it is necessary to add 1 to the signal, in the present embodiment, the output signal of the exclusive OR circuit 25 and the pedestal level signal of the digital value "60" generated from the pedestal level signal generation circuit 26 are added. The color subcarrier signal Csc is used as a carry in the least significant bit portion of the adding circuit 27.
The required addition of 1 is performed by applying. Here, the pedestal level signal having a digital value of "60" is applied to the exclusive OR circuit 25 by the digital signal BI to which the pedestal level generated from the burst forming signal 23 is not given and the pedestal level by ▲ ▼. The digital signal S to which the pedestal level is applied in the digital synchronizing signal generating circuit 22
Is output, it is unnecessary when 28 is an adder. Reference numeral 28 denotes a selector for forming a black burst signal from the digital synchronization signal S and the burst signal Burst, which uses an appropriate switching signal by utilizing the difference between the generation of the digital synchronization signal S and the generation of the burst signal Burst. Digital sync signal generator 22
And the addition circuit 27 are alternately selected to generate a black burst signal.
BlackBurst is formed and sent to the NTSC color encoder 19 of FIG.

FIG. 4 shows the digital synchronizing signal generating circuit 22 of the black burst signal generating circuit 20 of FIG. 3, and FIG. 5 shows the burst forming signal generating circuit 23, which are shown in FIGS. The present invention is applied to the digital synchronizing signal generating circuit 22 and the burst forming signal generating circuit 23 shown.

First, the digital synchronization signal generation circuit 22 will be described. The digital synchronizing signal generating circuit 22 is a 4-bit shift register 29 for shifting the synchronizing signal H / V-Sync inputted thereto, and a logic circuit 30 for forming a digital synchronizing signal.
Consists of 31 _{1-31 4} is the delay elements constituting the shift register 29, one bit at a same period as the signal by four times the frequency of the signal of the frequency fcsc of the shift register 29 is a color sub-carrier signal Csc Sync signal
Shift H / V-Sync.

The logic circuit 30 is composed of seven AND circuits 32 to 38 and four OR circuits 39 to 42. The signals S0 to S7 of each bit of the 8-bit digital synchronizing signal S output from the logic circuit 30 are output. It is output from the terminals TS0 to TS7. The output terminal TS0 for outputting the signal S0 of bit 0 is grounded, and the signal S0 is always kept at "0". The bit S1 signal S1 output from the output terminal TS1 is formed by the AND circuits 32 and 33 and the OR circuit 39. The AND circuit 32 inverts the output signal d of the delay element 31 ₄ at one input terminal, receives the output terminal c of the delay element 31 _{3 at} the other input terminal as it is, and outputs the output signal c. To the input terminal of. or,
AND circuit 33 to one input terminal receiving the output terminal b of the delay element 31 _2, receives and inverts the output signal a of the other input terminal to the delay element 31 _1, the other of the OR circuit 39 the output terminal b · Send to the input terminal. Therefore, the signal S1 output from the OR circuit 39 becomes c. +. B.

The bit 2 signal S2 output from the output terminal TS2 is formed by the AND circuits 34 and 35 and the OR circuit 40. AND circuit 34 receives delay elements 31 _1, 31 ₄ of the output signal a, the d, sends an output signal a · d to one input terminal of the OR circuit 40, also the AND circuit 35 is the signal a, d respectively The inverted signal is received and the output signal is sent to the other input terminal of the OR circuit 40. Then, the signal S2 output from the OR circuit 40
Becomes a · d + ·.

The bit S3 signal S3 output from the output terminal TS3 and the bit S5 signal S5 output from the output terminal TS5 are output by the OR circuit 41 that receives the output signals b and c output from the delay elements 31 ₂ and 31 _3. Since it is formed, it becomes b + c.

The signal S4 of bit 4 output from the output terminal TS4 is composed of AND circuits 36 to 38 and an OR circuit 42 receiving the output signal thereof. The AND circuit 36 receives the signals b and c, and the AND circuit 37 receives the signal c. And the signal d as it is, and the AND circuit 38 inverts the signal b and receives the signal a as it is. Then, the signal S4 output from the OR circuit 42 becomes b.c + .d + .a.

The output terminals TS6 and TS7 are both grounded, and the bit 6 signal S6 and the bit 7 signal S7 output from them are output.
Always keeps "0".

Then, the signals S0 to S7 of each bit of the digital synchronizing signal S output from the digital synchronizing signal generating circuit 22 shown in FIG. 4 are summarized as follows.

S7 = "0" (always 0) S6 = "0" (always 0) S5 = b + c S4 = a. + D. + B.c S3 = b + c S2 =. + A.d S1 = .b + c.S0 = "0" ( Always 0) Next, the burst forming signal generating circuit 23 shown in FIG. 5 will be described. This burst forming signal generating circuit 23 has 9
It is composed of a bit shift register 43 and a logic circuit 44 for generating a digital signal BI for burst formation and {circle around (4)}. The shift register 43 is composed of nine delay elements 45 _{1 to} 45 ₉ and uses a signal having a frequency four times the frequency fcsc of the color subcarrier signal Csc to set the burst flag signal BurstFlag to 1 bit at the same cycle as this signal. Shift one by one.

The logic circuit 44 is a part 44I which forms the digital signal BI.
And a portion 44Q forming a digital signal ▲ ▼, 44I is composed of AND circuits 46 to 51, an inverter 52 and OR circuits 53 and 54, and signals BI0 to BI7 of each bit of the digital signal BI are from TI0 to TI7. Is output. The signal BI0 of bit 0 output from the output terminal TI0 is the AND circuits 46, 47, 4
8 and the OR circuit 53. AND circuit 46 receives and inverts the output signal i of the delay element 45 g, it receives the output signal g of the delay element 45 ₅ therewith, and sends an output signal · g to the OR circuit 53. The AND circuit 47 receives the output signal g and inverts the output signal e of the delay element 45 ₁ . Further, the AND circuit 48 outputs the output signals e and i.
Each inversion and receive. And AND circuit 46 ~
Signal BI output from OR circuit 53 which receives the output signal of 48
0 becomes * g + g * + *. Output terminals TI1 and TI
Bit 1 and bit 3 signals BI1 and BI output from 3
3 is a signal obtained by inverting the output signal g of the delay element 45 ₅ by the inverter 52.

The bit 2 signal BI2 output from the output signal TI2 is the AND circuits 49 to 51 and the OR circuit 54 receiving these output signals.
Formed by. The AND circuit 49 inverts the output signal h of the delay element 45 ₇ and receives the output signal g of the delay element 45 ₅ as it is. The AND circuit 50 receives the signal g and inverts and receives the output signal f of the delay element 45 _3. The AND circuit 51 inverts and receives the signals f and h. Then, the signal BI2 output from the OR circuit 54 receiving the output signals of the AND circuits 49 to 51 is
It becomes g + g.

Further, the output terminals TI4 to TI7 are grounded, respectively, and the signals BI4 to BI7 of bit 4 to bit 7 output therefrom are all always "0".

The logic circuit 44Q includes AND circuits 55 to 62 and OR circuits 63 to 65.
And each bit signal ▲ ▼ to ▲ of the 8-bit digital signal ▲ ▼ output from the logic circuit 44Q.
▼ is output from the output terminals TQ0 to TQ7. Output terminal
Bit 0 and bit 1 signals {circle around (1)} and {circle around (1)} output from TQ0 and TQ1 are formed by AND circuits 55 and 56 and an OR circuit 63 receiving output signals from these. The AND circuit 55 inverts the signal g and receives the signal f as it is. The AND circuit 56 receives the signal i and inverts the signal h. Thus, the signals ▲ ▼ and ▲ ▼ output from the OR circuit 63 which receives the output signals of the AND circuits 55 and 56 become .f + .i.

The signal {circle around (1)} output from the output terminal TQ2 is formed by AND circuits 57 and 58 and an OR circuit 64 receiving this output signal. The AND circuit 57 receives the signal i by inverting and receiving the signal g as it is. Further, the AND circuit 58 receives the signal h and also the inverted output signal f. Then, the OR circuit which receives the output signals of the AND circuits 57 and 58
The signal ▲ ▼ output from 64 is · g + h ·. The signal {circle around (1)} output from the output terminal TQ3 is formed by AND circuits 59 to 61 and an OR circuit 65 receiving these output signals. The AND circuit 59 inverts and receives the signal h, and receives the signal g as it is. The AND circuit 60 conversely inverts and receives the signal g, and receives the signal h as it is.
Further, the AND circuit 61 inverts and receives the signals f and i, respectively. Then, the signal ▲ ▼ output from the OR circuit 65 that receives the output signals of these AND circuits 59 to 61 is
g + h · + ·. Further, the signal ▲ ▼ output from the output terminal TQ4 is formed by the AND circuit 62 which receives and inverts the signals g and h, respectively.

The output terminals TQ5 to TQ7 are grounded, and the bit 5 to bit 7 signals ▲ ▼ to ▲ output from them are output.
▼ is always “0”.

Here, the burst forming signal generating circuit 23 shown in FIG.
The burst forming signal BI and the signals BI0 to BI7 and ▲ ▼ to ▲ ▼ of each bit of ▲ ▼ are summarized as follows.

BI7 = "0" (always 0) BI6 = "0" (always 0) BI5 = "0" (always 0) BI4 = "0" (always 0) BI3 = BI2 = · + · g + g · BI1 = BI0 = · g + ・ g + ・ ▲ ▼ ＝ “0” (always 0) ▲ ▼ ＝ “0” (always 0) ▲ ▼ ＝ “0” (always 0) ▲ ▼ = ・ ▲ ▼ = ・ g + h ・ + ・ ▲ ▼ = ・g + h ・ ▲ ▼ ＝ ・ f + i ・ ▲ ▼ ＝ ・ f + i ・ The black burst signal generation circuit 20 shown in FIG. 3 below.
The operation will be described with reference to the time chart shown in FIG.

When the synchronizing signal H / V-Sync is input to the shift register 29 of the digital synchronizing signal generation circuit 22, the output signals a, b of the delay elements 31 ₁ , 31 ₂ , 31 ₃ , 31 ₄ constituting the shift register 29 are input. , C, d, the synchronizing signal S whose digital value changes in response to the change in the digital signals is output from the logic circuit 30. Table 1 below
Shows changes in the synchronizing signals H / V-Sync, a, b, c, d and the digital synchronizing signal S.

Also, the shift register of the burst forming signal generating circuit 23
When the burst flag signal Burstflag is input to 43,
Burst signal forming digital signals BI and ▲ ▼ whose digital values change corresponding to changes in the output signals e, f, g, h, i of the shift register 43 are output from the logic circuits 44I and 44Q. It Table 2 below shows the changes in the burst flag signals BurstFlag, e, f, g, h, i and the burst forming digital signal BI, ▲ ▼.

By the way, the digital signal BI for burst formation, ▲
∘ is input to a selector 24 controlled by a switching signal Csc ′ having a frequency 2fcsc which is twice the frequency fcsc of the color subcarrier signal Csc. Therefore, from the selector, the digital signal BI for burst signal formation, ▲
▼ is output alternately. And from this selector 24
The digital signals alternately output in the order of ▼, BI, ▲ ▼, BI, ▲ ▼ are color subcarrier signals Cs.
When c is "1", it is inverted, and when it is "0", it is input from the exclusive OR circuit 25 to the adding circuit 27 as it is. Then, the signals input to the adder circuit 27 are ▲ ▼, BI, BQ,
It changes in the order of ▲ ▼, ▲ ▼, BI, BQ, ▲ ▼, ▲ ▼, and forms the digital burst signal Burst. This digital value is 0, 0, 0, 1, -4,-
5, 12, 10, -19, -14, 24, 15, -24, -15, 24, 1
5, -24, -15 ... -24, -15, 24, 15, -24, -15, 2
4, 14, -19, -10, 12, 5, -4, -1, 0, 0,
It changes like 0, 0 ... "60" is added to the digital burst signal Burst by the signal from the pedestal level signal generating circuit 26 in the adding circuit 27 and the signal is sent to the selector 28. The selector 28 is supplied with the digital burst signal generating circuit 2 together with the black burst signal Burst.
The digital synchronizing signal S from 2 is also inputted, and the black burst signal Bl as shown in FIG.
ack Burst is output. Then, this black burst signal Black Burst is input to the NTSC color encoder 19 shown in FIG.

It should be noted that I, ..., Q described in the portions showing the signals Csc ′ and Csc in FIG. 6 are the selector 24 and the exclusive OR circuit 25.
BI output at each time from, ▲ ▼, ▲
▼, BQ is shown, and B is simply omitted for convenience.

Further, FIG. 7 shows the portion of the black burst signal, particularly the portion corresponding to the horizontal synchronizing signal Hsync and the portion following it, but the portion corresponding to the vertical synchronizing signal Vsync also has a predetermined pattern.

Since the subcarrier signal Csc (a) in one horizontal scanning period and the subcarrier signal Csc (b) in the next horizontal scanning period have opposite phases as shown in FIG. As shown in FIG. 7, it is possible to reverse the phase relationship between the burst signal Burst (a) in one horizontal scanning period and the burst signal Burst (b) (shown by a broken line) in the next horizontal scanning period. it can.

As described above, the black burst signal generation circuit 20 can generate the black burst signal Black Burst.

By the way, as is clear from FIG. 7, the black burst signal Black Burst has a very complicated digital value change. However, a black burst signal Black Burst generating a black burst signal Black Burst whose digital value changes in a complicated manner is generated. The circuit 20 itself can be easily constructed by a combination of logic gates such as AND, OR, and NOT. That is, the digital synchronizing signal generating circuit 22 for generating the digital synchronizing signal S of the black burst signal Black Burst and the digital signal BI for forming the burst signal,
The burst forming signal generating circuit 23 for generating ▼ is, as described above, the shift registers 29, 43 and the logic circuit 30,
As described above, the logic circuits 30 and 44 are composed of a combination of a plurality of logic gates.

In addition, the delay elements 31 _{1 to} 3 constituting the shift registers 29 and 43
1 _4, 45 ₁ to 45 ₉ can also be formed by the flip-flop which combined a plurality of logic gates. Therefore, the digital synchronizing signal generating circuit 22 and the burst forming signal generating circuit 23 can be formed by a combination of logic gates such as AND, OR, and NOT.

It is also clear that the selector 24 can also be formed by combining a plurality of logic gates. That is, the selector 24 is basically BI · Csc ′ + ▲ ▼ ・ ▲ ▼
Therefore, eight logic circuits composed of AND circuits 66 and 67, a knot circuit (inverter) 68, and an OR circuit 69 as shown in FIG. 9 are simply provided by providing eight logic circuits according to the number of bits. be able to. This also applies to the selector 28.

Further, the exclusive OR circuit 25 can naturally be formed by combining a plurality of logic gates without needing to explain it again.

Further, the pedestal level signal generation circuit 26 only needs to have a function of generating a 6-bit signal "111100" having a digital value of 60. Therefore, for example, two grounded output terminals,
It can be configured by providing four output terminals installed on the power supply voltage terminal, and does not require even a logic gate. Since the adder circuit 27 can also be formed by providing an adder composed of a plurality of logic gates by the same number as the number of bits, the adder circuit 27 can also be formed by a combination of logic gates.

Therefore, the entire black burst signal generation circuit 20 can be configured by a combination of basic logic gates such as AND, OR, and NOT. Therefore, a black burst signal generating circuit 2 is used by a commercially available programmable logic array (PLA) as shown in FIG.
Can be configured as 0. That is, such a programmable logic array (PLA) has a structure in which an appropriate intersection of a matrix of vertical and horizontal lines in FIG.
An arbitrary logic circuit can be obtained by connecting by writing with a writer. Therefore, it is not necessary to specially design the circuit for generating the black burst signal, and the cost of the color video camera can be reduced. Of course, in order to obtain a black burst signal, the black burst signal is decomposed into a plurality of patterns of signals, information about the signals of each pattern is stored in a memory, and the information is read out in a predetermined order. Needless to say, therefore, a relatively complicated circuit such as a pattern signal storage memory and a program control circuit for reading the pattern signals in a predetermined order is not required.

As described above, the digital signal generation circuit of the present invention is connected to a shift register having a plurality of output terminals for shifting one input signal of 1 bit, and a plurality of output terminals of the shift register, and a plurality of logic terminals. And a logic circuit for forming a digital signal composed of a gate, wherein one digital signal having a plurality of bits is generated by the arrangement of output signals of the logic circuit. Therefore, by shifting one input signal of 1 bit by the shift register, it is possible to generate a digital signal whose multi-bit digital value changes as set in advance by the arrangement of the output signals of the logic circuit. Therefore, a digital signal whose digital value changes very complicatedly can be obtained by a circuit having a simple structure including a shift register of several bits and a logic circuit formed by combining several logic gates. You can

FIG. 11 shows a main part of another color video camera circuit to which the digital signal generating circuit of the present invention is applied. This color video camera circuit is designed to cause each digital signal input to the NTSC color encoder 19 to have a delay such that the higher the number of bits, the larger the delay amount. The reason for causing such a delay is that the adding circuit in the NTSC color encoder 19 can be formed by a low-speed logic element.

That is, in a digital color video camera circuit including the color video camera circuits shown in FIGS. 2 to 5, an adder circuit for adding data of a plurality of bits, for example, 8 bits, generally has a very high speed logic element, for example. TT
It is necessary to use L or ECL. This is because, when adding signals of multiple bits, generally, the least significant bits are first added, the presence or absence of a carry is determined, and then the one bit higher than that is added. After the addition is completed, it is necessary to move to the addition of the upper bits, and all the bits cannot be added at the same time. Of course, if an adder circuit having a carry look ahead circuit is used, all bits can be added at the same time. However, in this case, since the carry look ahead circuit must be provided, the adder circuit becomes extremely large and the color video This is not preferable because miniaturization of the camera circuit is significantly restricted. Therefore, when an adder circuit that performs addition from the lower bit to the higher bit is used, for example, 8-bit data is added in one cycle of a clock pulse having a frequency that is, for example, four times the frequency of the color subcarrier signal. Must be done in-house. Therefore, it is necessary to use a high-speed logic element such as TTL or ECL for the adder circuit, which restricts high integration and low power consumption of the adder circuit. Therefore, the color video camera circuit of FIG. 11 enables the use of low-speed CMOS as the logic element of the adder circuit, thereby achieving high integration and low power consumption.

In FIG. 11, 70, 71, 72 and 73 are delay circuits,
The delay circuit 70 is provided in the transmission path of the chroma signal I input to the NTSC color encoder 19, the delay circuit 71 is also provided in the transmission path of the chroma signal Q, and the delay circuit 72 is also provided in the transmission path of the luminance signal Y. Has been. Delay circuit 70,
As shown in FIG. 12, each of 71 and 72 is composed of a large number of delay elements 74 and 74 for delaying the signal by one cycle of the clock pulse, and the delay amount increases as the higher order bits. Specifically, bit 0 has a delay amount of 0, bit 1
The delay amount is one clock pulse cycle, and the bit 2 is two clock pulse cycles, so that the higher the bit, the more the delay amount increases by one clock pulse cycle.

On the other hand, the delay circuit 73 is interposed between the NTSC color encoder 19 and the D / A converter 21, and like the delay circuits 70 to 72, a large number of delay elements 74, 74 for delaying the signal by one cycle of the clock pulse. It consists of ... However, this delay circuit 73
Contrary to the delay circuits 70 to 72, the delay amount is increased by one cycle of the clock pulse as the delay amount of the most significant bit becomes 0 and the lower bit becomes, and the delay amount of the least significant bit is 7 times the period of the clock pulse. Doubled.

In this way, the chroma signals I, Q and the luminance signal Y input to the NTSC color encoder 19 are passed through the delay circuits 70, 71, 72 in the NTSC color encoder for processing one bit per one cycle of the clock pulse. This is because it is done at speed. That is, since the chroma signals I and Q and the luminance signal Y are inputted to the NTSC color encoder 19 through the delay circuits 70, 71 and 72, all the digital signals are not all bits at the same time but one clock pulse. The bits are sequentially input to the NTSC color encoder 19 one bit at a time from the least significant bit at the same time intervals as the cycle.
Therefore, it is sufficient for each bit portion of the adder circuit in the NTSC color encoder 19 to be able to perform arithmetic processing for one bit within one cycle of the clock pulse. Therefore, NT
The calculation speed of the adder circuit in the SC color encoder 19 may be low. Therefore, the NTSC color encoder 19 can use CMOS, which is a low-speed logic element, and high integration and low power consumption can be achieved. It should be noted that the method of providing the difference in delay amount depending on this bit is not limited to the relationship of 1 bit for each bit, and there may be various cases.

The delay circuit 73 interposed between the NTSC color encoder 19 and the D / A converter 21 eliminates the above-mentioned delay between the bits of the signal output from the NTSC color encoder 19. That is, as is clear from the above, the output signal of the NTSC color encoder 19 is output in order from the least significant bit, so the delay circuit 73 delays the least significant signal the most, and the higher the bit, the smaller the delay amount. Thus, all bits of one digital signal are simultaneously input to the D / A converter 21. By the way, the black burst signal Black Burst output from the black burst signal generation circuit 20 is Y + Qsin (ωcsc · t + 33 °) + Icos (ωcsc · t + 33) in the NTSC color encoder 19.
The signal E obtained by the color encoding represented by (°) is added. Therefore, the black burst signal Blac
Similarly to the luminance signal Y and the chroma signals I and Q, a delay must be generated in k Burst so that the amount of delay increases as the higher order bits. The black burst signal generation circuit 20a shown in FIG. 11 is adapted to generate a black burst signal with such a delay.

FIG. 14 shows the digital synchronizing signal generating circuit 22a of the black burst signal generating circuit 20a.
The difference in the amount of delay due to bits as shown in FIG. 13 and FIG. 13 is in the case of the ratio of one amount of delay per 2 bits. The circuit 22a includes a 6-bit shift register 76 including delay elements 75 ₁ to 75 ₆ and a logic circuit 77. The logic circuit 77 includes AND circuits 78 to 84 and OR circuits 85 to 89.

The signal S0 of the least significant bit of the digital synchronizing signal S output from the logic circuit 77 always keeps "0". The signal S1 of bit 1 is formed by AND circuits 78 and 79 and an OR circuit 85 which receives the output signal thereof. AND circuit 78 is a delay element
The output signal d'of 75 ₄ is inverted and received, and the delay element 75 ₃
Of the output signal c '. AND circuit 79 is a delay element 75 ₂
Output signal b'of the delay element 751 and the output signal a'of the delay element 75 ₁ are inverted and received. Then, the output signal S1 of the OR circuit 85 which receives the output signals of the AND circuits 78 and 79 is ▲ ▼ ・
c ′ + b ′ · ▲ ▼. The signal S2 of bit 2 is formed by AND circuits 80 and 81 and an OR circuit 86 which receives the output signal thereof. The AND circuit 80 inverts and receives the output signals b'and e'of the delay elements 75 ₂ and 75 ₅ , respectively, and the AND circuit 81 receives the signals b'and e'as they are. Then, the output signal S2 of the OR circuit 86 which receives the output signals of the AND circuits 80 and 81 is ▲ ▼ ・ ▲ ▼ +
b ′ · e ′. The signal S3 of bit 3 is formed by the OR circuit 87 which receives the output signals c'and d'of the delay elements 76 ₃ and 76 ₄ and therefore becomes c '+ d'. Signal S ₄ bits 4 are formed by an OR circuit 88 which receives the AND circuits 82 to 84 and then the output signal. AND circuit 82 receives and inverts the "signal d with receiving the 'signal c, the AND circuit 83 receives and inverts the' output signal e of the delay element 76 ₅ with receiving an 'output signal f of the delay elements 76 _6, The AND circuit 84 receives the output signals d'and e'of the delay elements 75 ₄ and 76 ₅ . Then, the signal S4 output from the OR circuit 88 which receives the output signals of the AND circuits 82 to 84 is c '.
f ′ ▲ ▼ + d ′ · e ′. Also, the signal of bit 5
S5 is output from the OR circuit 89 which receives the output signals d'and e'of the delay elements 75 ₄ and 75 ₅ , so that S5 is d '+ e'.
Is. The signal S6 of bit 6 and the signal S7 of bit 7 are always kept "0".

The signals S0 to S7 of each bit of the signal S output from the digital synchronizing signal generating circuit 20a are summarized and shown as follows.

S7 = "0" (always "0") S6 = "0" (always "0") S5 = d '+ e' S4 = c '・ ▲ ▼ + ▲ ▼ ・ f' + d '・ e' S3 = c ' + D 'S2 = b' ・ e '+ ▲ ▼ ・ ▲ ▼ S1 = ▲ ▼ ・ c' + ▲ ▼ ・ b 'S0 = "0" FIG. 15 shows the input signal of the digital sync signal generating circuit 22a, that is, the synchronization. The signal H / V-Sync and the signals S0 to S7 of each bit of the output signal S are shown. In the figure, broken lines indicate signals S0 to S7 required when the above-mentioned delay between bits is not added to the signal input to the NTSC color encoder 19 as in the embodiment shown in FIGS. Is.

In the embodiment shown in FIG. 11, the burst signal
It is necessary to generate a delay with a different amount of delay in Burst as in the digital synchronization signal S. Therefore, the burst forming signal generating circuit 23a is also designed to generate such a delay in the output signal. Illustration and description of the configuration are omitted.

The digital synchronizing signal generating circuits 22 and 22a and the burst forming signal generating circuit 23 described above are merely embodiments of the present invention, and various embodiments of the present invention are conceivable, and the present invention is not limited to those described above. .

As described above, the digital signal generating circuit of the present invention comprises a plurality of delay elements for shifting one input signal of 1 bit, and has a plurality of output terminals connected to the output terminals of the respective delay elements. And a plurality of logic gates such as AND, OR, and / or knots, each of which has a plurality of input terminals, and each of the input terminals is connected to one of the output terminals of the delay element. And a logic circuit for forming a digital signal for generating one digital signal consisting of bits at a plurality of output terminals for each bit, the logic circuit shifting the input signal bit by bit in the shift register. The logic gates are arranged so that the digital value of the digital signal of a plurality of bits output from the logic circuit changes for each predetermined pattern. Therefore, by shifting one input signal of 1 bit by the shift register, it is possible to generate a digital signal that changes as set in advance at the output of the logic circuit.

Also, a digital signal whose digital value changes very complicatedly can be obtained by a simple configuration including a shift register of several bits and a logic circuit formed by combining several logic gates.

[Brief description of drawings]

FIG. 1 is a time chart showing a part of a black burst signal, FIGS. 2 to 10 are for explaining an example of an embodiment of a digital signal generating circuit of the present invention, and FIG. 2 is an entire color video camera circuit. FIG. 3 is a block diagram showing a black burst signal generating circuit to which the present invention is applied, which is a part of the circuit shown in FIG. 2, and FIG. 4 shows a digital signal generating circuit of the present invention. FIG. 5 is a circuit diagram showing a digital synchronizing signal generating circuit, FIG. 5 is a circuit diagram showing a burst forming signal generating circuit embodying the digital signal generating circuit of the present invention, and FIG. 6 is an operation of the black burst signal generating circuit. FIG. 7 is a time chart for explaining, and FIG. 7 is a time chart showing a black burst signal output from the black burst signal generating circuit. FIG. A time chart for explaining the principle of generating a strike signal, FIG. 9 is a circuit diagram showing an example of a selector, and FIG. 10 is an example of a programmable logic array which can be used for implementing the digital signal generating circuit of the present invention. Circuit diagrams, FIGS. 11 to 15 are for explaining another embodiment of the digital signal generating circuit of the present invention.
FIG. 11 is a block diagram showing the main part of the video camera circuit.
12 and 13 are block diagrams showing a delay circuit, FIG. 14 is a circuit diagram showing a digital synchronizing signal generating circuit which implements the digital signal generating circuit of the present invention, and FIG. 15 is a signal generated from the digital synchronizing signal generating circuit. 7 is a time chart showing a change in signal of each bit of the generated digital signal. Explanation of symbols 22, 22a, 23 ... Digital signal generating circuit, 29, 43, 76 ...
Shift register, 30, 44, 77 ... Logic circuit, 31, 45, 75,
... Delay element, 32-38, 46-51, 55-62, 78-84 ... AND circuit, 39-41, 53, 54, 63-65, 85-89 ... OR circuit, 52
... knot circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-52-3353 (JP, A) JP-A-53-140961 (JP, A) JP-A-54-101076 (JP, A) Edited by The Institute of Electronics and Communication Engineers Digital signal processing "August 10, 1980 Published by The Institute of Electronics, Communication and Communication, P. 71 ~ 76

Claims (3)

[Claims] 1. A plurality of delay elements for shifting one input signal of 1 bit consists (31 ₁ to 31 _4, 45 ₁ to 45 ₉₎ respective delay elements (31 ₁ to 31 _4, 45 ₁ to 45 ₉ ), A shift register (29, 43) having a plurality of output terminals connected to the output terminal, and a plurality of logical gates (32-42, 46-65) such as AND, OR, and / or knot, Input terminals, each of which is connected to the delay element (31 _{1 to} 3).
Logic circuit for forming digital signals (30, 44I) that is connected to any one of the output terminals (1 ₄ and 45 _{1 to} 45 ₉ ) and generates one digital signal consisting of multiple bits at multiple output terminals for each bit. , 44Q), and the logic circuit (30, 44I, 44Q) is configured such that each time the input signal is shifted in the shift register (29, 43) by one bit, the logic circuit (30, 44I, 44Q). The digital pattern signal generating circuit is characterized in that the logic gates are arranged so that the digital value of the digital signal of a plurality of bits output from (1) changes according to a predetermined pattern. 2. A digital pattern signal generating circuit according to claim 1, wherein one 1-bit input signal is a burst flag signal and one digital signal is a digital burst signal. 3. A digital pattern signal generating circuit according to claim 1, wherein one 1-bit input signal is a horizontal or vertical synchronizing signal, and one digital signal is a digital synchronizing signal.