JPH08227143A - Reticle used for manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics - Google Patents

Abstract

(57) Abstract: A reticle used for manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics, which can expose a resist with a mask pattern corresponding to transistor groups having different characteristics in one step. To do. A memory cell section (2) having a plurality of mask patterns corresponding to a plurality of memory cell transistors is provided on a main surface of a reticle body (1). These memory cell units 2 are composed of two first and second blocks 3, 4
Is divided into The mask pattern 5 corresponding to the memory cell transistors belonging to the first block 3 and the mask pattern 6 corresponding to the memory transistors belonging to the second block 4 have different areas. Further, the reticle body 1 is also formed with a mask pattern 7 for forming a logic portion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reticle used in a method of manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics.

[0002]

2. Description of the Related Art A memory cell is a minimum unit circuit for storing information in a semiconductor memory device. The memory cell is composed of a combination of a transistor and a capacitor. In a normal semiconductor memory device, in order to minimize variations in stored information, memory cells are formed in a memory cell array so that memory cells of the same type and the same size have as uniform characteristics as possible.

In a manufacturing process of a memory cell transistor, a conductive film is patterned into the same type and the same size to form a floating gate and a control gate. For this reason, a resist is applied on the conductive film, and the resist is exposed and developed to form a resist pattern having a shape corresponding to the floating gate and the control gate. In order to form this resist pattern, a reticle on which a mask pattern having a shape corresponding to the resist pattern is formed is used.

In order to reduce variations in stored information written in the semiconductor memory device as described above, the conventional reticle has a plurality of mask patterns of the same shape and the same size corresponding to each memory cell transistor. Has been formed.

[0005]

As the degree of integration of semiconductor memory devices increases, the semiconductor memory devices are required to have a system function integrated with a CPU from a simple storage medium. This tendency is especially
This is remarkable in non-volatile semiconductor memory devices such as M, EEPROM and flash memory.

In response to such a demand, it has been proposed to divide a memory cell array in a semiconductor memory device into a plurality of blocks and give each block a different function, for example, as in a boot block method of Intel Corporation. There is. In this method, each block has different functions,
The characteristics required for the memory cells are different. That is, a block to which a basic code such as system activation is input requires a mask ROM-like memory cell because data is not rewritten so much. On the other hand, in a block where data is frequently rewritten, a memory cell having excellent program characteristics is desirable.

However, in the conventional semiconductor memory device, the memory cell arrays are all composed of memory cells having the same characteristics. Therefore, it is not possible to meet the various demands described above. If the memory cells are formed so as to have characteristics suitable for one block, there is a risk that other blocks may be disturbed. For example, if all the memory cells of the memory cell array are made to have a large gate couple ratio in order to improve the program characteristics, problems such as gate disturb and soft write occur in the memory cells of the block for inputting the basic code. Easier to do.

Therefore, it is conceivable to divide a plurality of memory cell transistors in the same non-volatile semiconductor memory device into transistor groups having different characteristics. However, in manufacturing a nonvolatile semiconductor memory device having such transistor groups having different characteristics, when a reticle having a plurality of mask patterns of the same shape and the same size is used as in the conventional case, each transistor group is It is necessary to prepare a plurality of reticles each having a different mask pattern size. Further, since it is necessary to perform the exposure processing according to the number of reticles, there is a disadvantage that the number of steps increases.

The present invention has been made in view of the above point, and a non-volatile semiconductor memory having a transistor group having different characteristics, which can expose a resist with a mask pattern corresponding to the transistor group having different characteristics in one step. A reticle used for manufacturing a device is provided.

[0010]

SUMMARY OF THE INVENTION The present invention is a non-volatile semiconductor memory device having a plurality of memory cell transistors, wherein the plurality of memory cell transistors is a transistor group composed of at least one memory cell transistor. A reticle that is divided and is used for manufacturing a nonvolatile semiconductor memory device in which the characteristics of the memory cell transistor are different between the transistor groups, and a mask pattern corresponding to each of the memory transistors is formed, and the mask. A reticle used for manufacturing a non-volatile semiconductor memory device having transistor groups having different characteristics, wherein the pattern areas are different between the transistor groups.

In the reticle of the present invention, for example, a memory cell transistor is provided between a source / drain region of opposite conductivity type provided on a main surface of a semiconductor substrate of one conductivity type and separated from each other, and the source / drain region. A floating gate provided on the channel region via a first gate insulating film, a cap made of a conductive material and having an area larger than the area of the floating gate formed on the surface of the floating gate, And a control gate provided on the surface of the mask via a second gate insulating film, which is used for exposing a resist for patterning the conductive material to be the cap, and the mask pattern Area is different between the transistor groups.

In the reticle of the present invention, for example, memory cell transistors are provided on the main surface of a semiconductor substrate of one conductivity type, the source / drain regions of opposite conductivity type being provided apart from each other, and the source / drain regions. A first gate insulating film provided on the channel region between the first and second gate insulating films so as to partially or entirely cover the source / drain region;
The first conductive layer, which comprises a floating gate made of a conductive layer and a control gate made of a first conductive layer provided on the surface of the floating gate via a second gate insulating film, and becomes the floating gate. And is used for exposing a resist for patterning, and the area of the mask pattern is different between the transistor groups.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of a reticle used for manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics according to the present invention. In the figure, 1 is a reticle body. A memory cell portion 2 having a plurality of mask patterns corresponding to a plurality of memory cell transistors is provided on the main surface of the reticle body 1. These memory cell units 2 are divided into the first and second
It is divided into blocks 3 and 4. The mask pattern 5 corresponding to the memory cell transistors belonging to the first block 3 and the mask pattern 6 corresponding to the memory cell transistors belonging to the second block 4 have different areas. However, the mask patterns belonging to the same block have the same shape and the same size. In this embodiment, the mask patterns 5 and 6 are each rectangular, and the short sides (the length in the y direction shown in FIG. 1) have the same length, but the long sides (the length in the x direction shown in FIG. 1). Are different lengths. However, the shape of the mask patterns 5 and 6 is not limited to this, and the lengths in the y direction may be different, the lengths in the x direction may be the same, and the shapes are not rectangular. May be.

A mask pattern 7 for forming a logic portion is also formed on the reticle body 1.

A method of manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics using the reticle 8 described above will be described. First, a non-volatile semiconductor memory device having transistor groups having different characteristics will be described with reference to FIG. In the figure, 11 is a memory cell array. The memory cell array 11 includes the first block 1
It is divided into two and second blocks 13. In the first block 12, a plurality of first type memory cells 14 are formed in a matrix. FIG. 3 shows a sectional view of the first type memory cell 14. In the figure, 21 is a p-type silicon substrate.
A source region 22 and a drain region 23, which are high-concentration impurity diffusion regions (n ⁺ ) formed by doping n-type impurity ions, are formed on a p-type silicon substrate 21. A tunnel oxide film 24 is formed on the surface of the silicon substrate 21 including the source region 22 and the drain region 23. A floating gate 26 made of a polysilicon film is formed on the surface of the tunnel oxide film 24 and above the channel region 25 between the source region 22 and the drain region 23. An interlayer insulating film 27 made of silicon oxide is formed on the surface of the tunnel oxide film 24 except the region where the floating gate 26 is formed.

A cap 28 made of polysilicon is formed to cover the exposed surface of the floating gate 26 and to cover the surface of the interlayer insulating film 27 and the regions above the source region 22 and the drain region 23. There is. The cap 28 has a length Lx1 along the direction in which the source region 22 and the drain region 24 are arranged (hereinafter, referred to as x-direction length), and a direction orthogonal to the direction in which the source region 22 and the drain region 24 are arranged. It has a length (hereinafter, y-direction length) Ly1. Therefore, the area S1 of the substantially rectangular cap 28 is represented by Lx1 × Ly1.

On the surface of the interlayer insulating film 27 including the cap 28, an ONO film 29 is formed by laminating silicon oxide / silicon nitride / silicon oxide. A control gate 30 made of polysilicon is formed on the surface of the ONO film 29.

The second block includes a second type memory cell 15
Are formed in a matrix. FIG. 4 shows a sectional view of the second type memory cell 15. Second type memory cell 15
Covers the exposed surface of the floating gate 26, and
The first cap shown in FIG. 3 is different from the first cap shown in FIG. 3 except that the cap 31 made of polysilicon formed on the surface of the interlayer insulating film 27 so as to cover the regions above the source region 22 and the drain region 23 is different. The memory cell 14 has the same structure as the memory cell 14.

The length Lx2 of the cap 31 in the x direction is the length Lx1 of the cap 28 of the first-type memory cell 14 in the x direction.
Longer than. In addition, the y-direction length Ly2 of the cap 31
Is the same as the y-direction length Lx2 of the cap 28 of the first-type memory cell 14. Therefore, the substantially rectangular cap 31
Area S2 is represented by Lx2 × Ly2 and is larger than the area S1 of the cap 28 of the first-type memory cell 14.

The gate coupling ratios of the first type memory cell 14 and the second type memory cell 15 are as follows: the capacitance ratio between the channel region 25 and the floating gate 26 and the capacitance ratio between the floating gate 26 and the control gate 30. The larger it gets, the bigger it gets. In the first type memory cell 14 and the second type memory cell 15, since the area where the channel region 25 and the floating gate 26 overlap each other is the same, the channel region 25 and the floating gate 2 are the same.
The capacitance between 6 is constant between each memory cell. On the other hand, the capacitance between the floating gate 26 and the control gate 30 increases as the overlapping area of the floating gate 26 and the control gate 30 increases. In the first-type memory cell 14 and the second-type memory cell 15, the overlapping area is determined by the areas S1 and S2 of the caps 28 and 31, because the control gate 30 covers all the caps 28 and 31. Since the y-direction lengths Ly1 and Ly2 of the caps 28 and 31 are the same, the areas S1 and S2 increase in proportion to the x-direction lengths Lx1 and Lx2 of the caps 28 and 31.

Therefore, in the first-type memory cell 14, since the length Lx1 of the cap 28 is relatively short, the cap 28
Area S1 becomes smaller. Therefore, the overlapping area where the cap 28 forming a part of the floating gate 26 and the control gate 30 overlap each other is relatively small.
Floating gate 26 and control gate 3
The capacitance between 0 is smaller than that of the second type memory cell 15. As a result, the first-type memory cell 14
Since the gate couple ratio of is smaller, it is possible to obtain a mask ROM-like characteristic with read priority.

On the other hand, in the second type memory cell 15, since the length Lx2 of the cap 31 is relatively long, the area S2 of the cap 30 is large. Therefore, the cap 28 forming a part of the floating gate 26 and the control gate 3
Since the overlapping area where 0s overlap each other is relatively large, the floating gate 26 and the control gate 30
The capacitance between the two becomes large. As a result, the gate couple ratio of the second type memory cell 15 becomes large,
Excellent program characteristics can be obtained.

As described above, in the non-volatile semiconductor memory device according to the first embodiment, the first block 12 and the second block 13 have different characteristics in the first block 12 and the second block 13, respectively. Are formed respectively. Therefore, in the first block 12, the first type memory cell 14 has a relatively small gate couple ratio and the mask RO.
Since it has M-like characteristics, it is possible to prevent the occurrence of read disturb. On the other hand, in the second block 13, since rewriting is preferentially performed, a long-term error such as read disturb hardly poses a problem. Therefore, in the second-type memory cell 15, the rewrite characteristic can be improved by increasing the gate couple ratio.

An example of a method of manufacturing a nonvolatile semiconductor memory device having a transistor group having different characteristics as described above will be described below with reference to FIGS. In FIGS. 5, 6, 7 and 8, (A) is the first block 1
The second manufacturing process of the first type memory cell 14 is as follows.
The respective manufacturing steps of the second type memory cell of the block are shown.

First, as shown in FIG. 5, a tunnel oxide film 24 is formed on the surface of a p-type silicon substrate 21, and a first polysilicon film for a floating gate is formed thereon. The first polysilicon film is etched by a general photolithography process so that each memory cell 14,
A floating gate 26 corresponding to 15 is formed.
Next, the source region 22 and the drain region 23 of each memory cell 14, 15 are formed on the main surface of the silicon substrate 21 by ion implantation.

Next, as shown in FIG. 6, the silicon substrate 2
After a silicon oxide film is formed on the entire surface of 1, the interlayer insulating film 27 is formed between the adjacent floating gates 26 of each memory cell 14 and 15 by etching back.

Next, a second polysilicon film is formed on the entire surface of the interlayer insulating film 27 including the exposed surface of the floating gate 26. Next, a resist is applied on the second polysilicon film. After that, the second reticle 8 shown in FIG.
The polysilicon film is exposed. The reticle 8 has a plurality of mask patterns 5 and 6 corresponding to the caps 28 and 31 of the memory cells 14 and 15 and having different areas, that is, lengths in the x direction. The resist is exposed through this reticle. After that, the resist is developed according to a conventional method to form a cap 2 on the second polysilicon film.
A resist pattern corresponding to 8 and 31 is formed. Using this resist pattern as a mask, the second polysilicon film is etched to form caps 28 and 31 having different areas so as to project from the floating gate 26, as shown in FIG.

Next, as shown in FIG.
An ONO film 29 is formed on the interlayer insulating film 27 including 31, and a control gate 30 made of polysilicon is further formed on the ONO film 29.

Through the above steps, a non-volatile semiconductor memory device including the first memory cell 14 and the second memory cell 15 having different gate couple ratios can be formed.

As described above, according to the reticle 8 used for manufacturing the nonvolatile semiconductor memory device of this embodiment, x of the mask patterns 5 and 6 corresponding to the caps 28 and 31.
By using the first block 3 and the second block 4 having different directional lengths, that is, areas, a resist pattern can be formed by one exposure process using one reticle 8, so that a normal memory cell can be formed. 1st block 12 and 2nd block 1 without increasing the manufacturing process of
It is possible to form three memory cells having different characteristics.

A memory in which the gate couple ratio is changed by changing the size of the floating gate as shown in FIG. 9 in place of the first and second type memory cells 14 and 15 having the caps 28 and 31 described above. It may be a cell. In the memory cell 92, a thick oxide film 94 is formed on the surface of the silicon substrate 93. This oxide film 94
On the lower side, a source region 95 and a drain region 96 are formed so that a part thereof is exposed on the surface of the silicon substrate 93. A floating gate 98 made of polysilicon is formed on the surface of the channel region 97 defined by the source region 95 and the drain region 96 so as to cover the exposed surface of the source region 95 and the drain region 96 and a part of the oxide film 94. Is a tunnel oxide film 9
It is formed through 9. Floating gate 98
An ONO film 100 is formed on the surface of the oxide film 94. A control gate 101 is formed on the surface of the ONO film 100.

In the memory cell 102 having such a structure, the field oxide film 94 of the floating gate 98 is formed.
By changing the length Lx3 along the direction in which
The gate couple ratio can be changed. That is, the floating gate 98 has the channel region 97.
Since all of the floating gate 98 and the channel region 97 are covered, the area where the floating gate 98 and the channel region 97 overlap is constant regardless of the length Lx3 of the floating gate 98. Therefore, the floating gate 98 and the channel region 9
The capacitance between 7 is constant between each memory cell. On the other hand, when the length Lx3 of the floating gate 98 is changed, the area where the floating gate 98 and the control gate 101 overlap each other changes.
Therefore, the capacitance between the floating gate 98 and the control gate 101 changes. As described above, by changing the length Lx3 of the floating gate 98, the capacitance between the floating gate 98 and the control gate 101 can be changed, and the gate couple ratio of the memory cell 92 can be changed.

Therefore, in the first block 12, in order to obtain a memory cell having a mask ROM characteristic of read priority,
The length Lx3 of the floating gate 98 described above is shortened to reduce the gate couple ratio. On the other hand, in the second block 13, the length Lx3 of the floating gate 98 is increased to increase the gate couple ratio in order to obtain a memory cell having excellent programming characteristics of rewriting priority.
As described above, even when the memory cell of this modification is used, it is possible to form memory cells having characteristics suitable for different functions for each block.

Also in the nonvolatile semiconductor memory device of the second embodiment described above, when forming the floating gate, as described above, the first block 12 and the second block 1 are formed.
Corresponding to the floating gate of each memory cell of 3,
It is sufficient to use the reticle 8 on which a plurality of mask patterns 5 and 6 having different lengths in the x direction, that is, different areas are formed, and it is not necessary to use more complicated means.

That is, first, the p-type silicon substrate 93
A thick oxide film 94 is formed by injecting and oxidizing impurities in parallel regions which are separated from each other on the surface of the above, and then a tunnel oxide film 99 is formed, on which a first polysilicon film for a floating gate is formed. Form. In order to form this first polysilicon film, a resist is applied on the first polysilicon film, and this resist corresponds to the floating gate of each memory cell 92 of the first block 12 and the second block 13 described above. Then, exposure and development processes are performed using the reticle 8 on which a plurality of mask patterns 5 and 6 having different areas, that is, lengths in the x direction, are formed to form a resist pattern. The first polysilicon film is etched using the obtained resist pattern to form the floating gate 98 corresponding to each memory cell.

As described above, as a reticle used when patterning the first polysilicon film, the length Lx3 of the floating gate 98 differs between the first block 12 and the second block 13 in the x direction. By using the reticle 8 on which the mask patterns 5 and 6 are formed, it is possible to form a resist pattern for patterning the first polysilicon film by one exposure process using one reticle 8, so that a normal memory can be formed. It is possible to form memory cells having different characteristics in the first block 12 and the second block 13, respectively, without increasing the cell manufacturing process.

The memory cell array 11 can be divided into not only two blocks as described above but also three or more blocks according to the required function. In addition, as shown in FIG.
11 is divided into two first and second blocks 112 and 113, and a sub block 11 is further provided in the second block 113.
It is also possible to form 4. First to second block 11
2, 113 and the memory cells 115, 116, 117 formed in a matrix in the sub-block 114,
First-type memory cell 14 having cap 28 shown in FIG.
It has the same configuration as. The memory cell 114 of the first block 112 has a relatively short cap length and a small gate couple ratio in order to obtain a read-only mask ROM-like characteristic. Memory cells 116 formed in the second block 113 and other than the sub-block 114
Has a relatively long cap length and a large gate couple ratio in order to obtain the programming characteristic of rewriting priority. The memory cells 117 formed in the sub-block 117 include the first block 112 and the second block 11.
The third memory cell 115, 116 has an intermediate characteristic. Therefore, the cap length of the memory cell 117 is intermediate between the two, and the gate couple ratio is also intermediate.

In this case, by sharing the well or source between the blocks 112 and 113,
113 can be treated as an independent area. Therefore, it is not necessary to change the type of the memory cell 115 for each of the blocks 112 and 113.

However, the well isolation region and the block isolation region are increased, and the chip area may be increased. In particular, the problem becomes more serious as the size of one block becomes smaller. Therefore, the memory cell array 11 that uses a group of memory cells sharing a well and a source as one unit
If the memory cell array 111 is divided into each block by using a memory cell group having a required characteristic as one unit instead of dividing 1 into each block, the well isolation region and the block isolation region do not increase. The above-mentioned sub-block 114 shares a well and a source with the second block 113 and does not need a well isolation region or a block isolation region.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of a reticle used for manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics.

FIG. 2 is a schematic view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a first type memory cell of the nonvolatile semiconductor memory device shown in FIG.

FIG. 4 is a cross-sectional view showing a second type memory cell of the nonvolatile semiconductor memory device shown in FIG.

5A and 5B are cross-sectional views showing respective memory cells of the first block and the second block in one step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

6A and 6B are cross-sectional views showing memory cells of a first block and a second block in a step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

7A and 7B are cross-sectional views showing the memory cells of the first block and the second block in one step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

8A and 8B are cross-sectional views showing the memory cells of each of the first block and the second block in one step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

9 is a sectional view showing a memory cell of a second embodiment of the nonvolatile semiconductor memory device shown in FIG.

FIG. 10 is a schematic view showing a third embodiment of the non-volatile semiconductor memory device of the present invention.

[Explanation of symbols]

1 ... Reticle body, 2 ... Memory cell part, 3 ... First block, 4 ... Second block, 5, 6, 7 ... Mask pattern,
8 ... Reticle, 11 ... Memory cell array, 12 ... First block, 13 ... Second block, 14 ... First type memory cell, 15 ... Second type memory cell, 21 ... Silicon substrate, 2
2 ... Source region, 23 ... Drain region, 24 ... Tunnel oxide film, 25 ... Channel region, 26 ... Floating gate, 27 ... Interlayer insulating film, 28, 31 ... Cap, 2
9 ... ONO film, 30 ... Control gate.

Claims (3)

[Claims] 1. A non-volatile semiconductor memory device having a plurality of memory cell transistors, wherein the plurality of memory cell transistors are divided into transistor groups each including at least one memory cell transistor. A reticle used in the manufacture of a non-volatile semiconductor memory device having different characteristics of the memory cell transistor, wherein a mask pattern corresponding to each of the memory transistors is formed, and the area of the mask pattern is equal to that of the transistor group. Characterized by different between,
A reticle used for manufacturing a nonvolatile semiconductor memory device having transistor groups having different characteristics. 2. A memory cell transistor is disposed on a main surface of a semiconductor substrate of one conductivity type and is provided on a channel region between the source / drain regions of the opposite conductivity type provided separately from each other. 1 a floating gate provided via a gate insulating film, a cap made of a conductive material formed on the surface of the floating gate and having an area larger than the area of the floating gate, and a second cap on the surface of the cap. A control gate provided via a gate insulating film, which is used for exposing a resist for patterning the conductive material to be the cap, and the area of the mask pattern is the transistor group. The reticle according to claim 1, wherein 3. A memory cell transistor is provided on the channel region between the source / drain regions and the opposite conductivity type source / drain regions provided on the main surface of a semiconductor substrate of one conductivity type and spaced apart from each other. A floating gate made of a first conductive layer provided so as to cover a part or the whole of the source / drain region via a first gate insulating film, and a second gate insulating film provided on the surface of the floating gate. And a control gate formed of a first conductive layer, which is used for exposure of a resist for patterning the first conductive layer to be the floating gate, and has an area of the mask pattern. The reticle according to claim 1, wherein the reticle is different between the transistor groups.