JPH09326475A - Method for manufacturing non-volatile memory device and exposure mask - Google Patents

Abstract

In a contactless semiconductor memory device, the distance between word lines arranged at equal intervals in a memory cell region is limited by the resolution limit of lithography, and the device is highly integrated. Has been hampered. A word line 17a in a memory cell area 11a
In the lithography exposure for forming the pattern, a negative type mask that becomes a mask when the word line 17a is formed using the first region 2a of the exposure mask 2 in which only the phase shift pattern a is arranged on the transparent substrate 20. The resist film 18 is exposed. As a result, the phase shift pattern a
An unexposed image 22 below the resolution limit of exposure light is formed on the resist film 18 portion corresponding to the boundary part of the resist film 18
The word line forming layer (polycide layer 17) is etched using the resist pattern 18a made of as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile memory device and an exposure mask used for manufacturing the non-volatile memory device.

[0002]

2. Description of the Related Art In recent years, with the increase in integration of semiconductor devices, in non-volatile memory devices, contacts are not arranged in the memory cell region, but contacts are arranged in the peripheral region outside the memory cell region. The memory cell area is being reduced. As an example of such a contactless nonvolatile memory device, there is a NAND nonvolatile memory device as shown in the circuit diagram of FIG. As shown in this figure, one unit cell array of a contactless NAND-type nonvolatile memory device includes a plurality of (here, eight) memory elements 91 connected in series, and these memory elements 9
1 has a selection transistor 92 and a bit contact 93 connected in series. The bit contact 93 is shared by the plurality of storage elements 91, so that the storage cell area 9 in which the storage elements 91 are arranged is arranged.
The layout is such that the contacts are not arranged in a to achieve the reduction of the memory cell region 9a.

To manufacture the above-mentioned non-volatile memory device, lithography is performed using an exposure mask in which a light-shielding film pattern is arranged in all areas on a transparent substrate, and a resist pattern formed by this lithography is used as a mask. Each material layer is patterned by the etching used. For example, the storage element 91 and the selection transistor 9
In lithography for forming the second word line 94, as shown in FIG. 10A, an exposure mask in which a light shielding film pattern 202 having a width w ₁ corresponding to the width of the word line is arranged on the transparent substrate 201. 200, the semiconductor substrate 90
The resist film 903 formed on the material layer 902 above 1 is exposed. These light-shielding film patterns 202 are arranged at intervals p ₁ corresponding to the arrangement intervals of word lines. Next, the resist film 903 is developed, and the material layer 902 is etched using the resist pattern 903a thus obtained as a mask.

As a result, as shown in FIG. 10B, the word lines 94 having a predetermined width W ₁ are arranged and formed on the semiconductor substrate 901 at a predetermined interval P ₁ . After forming the word line 94 as described above, the floating gate 95 is formed below the word line 94 by etching using the resist pattern 903a as a mask. After that, the source / drain diffusion layer 96 is formed on the surface side of the semiconductor substrate 901 by ion implantation using the word line 94 as a mask.
Is implanted to form.

Also in the NOR type non-volatile memory device, in the contactless non-volatile memory device such as the isolated source type, the common source type and the virtual ground type, the above N
Similar to the AND type, the cell area has been reduced.

[0006]

[Problems to be Solved by the Invention]
Even in the semiconductor memory device having such a configuration, FIG.
The interval P between the word lines 94 shown in FIG.₁Word line 94
The resolution of the exposure light in lithography when forming
Therefore, it is limited. The interval P between the word lines 94 ₁Is
The floating gate 95 below the word line 94 is adjacent to the storage element.
It is sufficient if the children are separated, and the spacing is wider than necessary.
You don't have to. Therefore, the above-mentioned interval P₁Semiconductor memory
This is one of the factors that hinder the further high integration of the device.

[0007]

Therefore, the present invention for solving the above-mentioned problems is a method for manufacturing a nonvolatile memory device in which a contact is arranged in a peripheral region outside a memory cell region. The exposure in lithography for forming the word lines in the cell region is characterized in that the negative type resist film is exposed using the exposure mask portion in which only the phase shift pattern is arranged on the transparent substrate. .

In the above method of manufacturing a non-volatile memory device, since the negative resist film is exposed by using the exposure mask portion formed by arranging only the phase shift pattern on the transparent substrate, the phase shift pattern In the resist film portion corresponding to the boundary portion, an unexposed portion where the irradiation intensity of the exposure light is insufficient to polymerize the negative resist is generated due to the phase shift of the exposure light. Since the width of this unexposed portion is narrower than the width of the resolution limit of the exposure light, a resist pattern having a space narrower than the resolution limit of the exposure light is formed in the above-mentioned lithography. Therefore, the word lines formed in the memory cell region by etching using the resist pattern as a mask are arranged at intervals narrower than the limit of lithography.

Further, it is an exposure mask used for manufacturing a non-volatile memory device in which contacts are arranged in a peripheral region outside a memory cell region, and only phase shift patterns for forming word lines are arrayed. It is characterized in that the first region and the second region in which the light shielding film pattern is formed are arranged on the same transparent substrate.

In the above exposure mask, a first region in which only phase shift patterns for forming word lines are arranged and a second region in which a light shielding film pattern is formed are arranged on the same transparent substrate. ing. From this, by exposing the memory cell region to the first region, an unexposed pattern image is formed on the exposed surface of the memory cell region at the boundary of the phase shift pattern by diffraction of the exposure light. To be done. Further, by exposing the peripheral region to the second region, a light-shielding film pattern image is formed on the exposed surface of the peripheral region.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a cross-sectional process diagram for explaining a first embodiment in which a method for manufacturing a nonvolatile memory device according to the present invention is applied to a method for manufacturing a NAND-type nonvolatile memory device, and FIG. It is a top view corresponding to. Also,
FIG. 1 is taken along the line AA of FIG. The nonvolatile memory device manufactured here is a contactless NAND-type nonvolatile memory device described in the related art with reference to the circuit diagram of FIG.

First, as shown in FIGS. 1A and 2A, a semiconductor cell 11 has a memory cell region 11a in which a memory element is formed and a peripheral region 11b in which a select transistor and a contact are formed. Are arranged. Then, the element isolation 12 and the diffusion layer 13 are formed on the front surface side of the semiconductor substrate 11. The element isolation 12 is, for example, LOCO.
It is formed by the S method. Further, the diffusion layer 13 is formed by ion implantation and subsequent heat treatment, and the storage cell region 11 is formed.
An impurity having a conductivity type opposite to that of the memory element arranged in a is introduced.

Next, as shown in FIGS. 1B and 2B, after forming a tunnel oxide film 14 (not shown in the plan view of FIG. 2) on the upper surface of the semiconductor substrate 11, the tunnel oxide film is formed. A floating gate forming layer 15 is formed on the film 14. continue,
The portion of the floating gate forming layer 15 between the unit memory cell regions is removed by the photolithography technique and the subsequent etching. Then, the inter-poly insulating film 16 is covered with the floating gate forming layer 15 (not shown in the plan view of FIG. 2).
Then, a polycide layer 17 (a layer having a laminated structure of lower polycrystalline silicon and upper silicide: omitted in the plan view of FIG. 2) is formed as a word line forming layer on the interpoly insulating film 16.

Next, as shown in FIGS. 1 (3) and 2 (3), a resist pattern 18a serving as a mask for forming a word line is formed on the upper surface of the polycide layer 17 by using a photolithography technique. (Omitted in the plan view of FIG. 2). This step is an important step in the present invention. In this case, first, a negative type resist film 18 (not shown in the plan view of FIG. 2) is applied on the polycide layer 17. Next, the resist film 18 is formed from above the exposure mask 2.
The exposure light is applied to the.

Here, the exposure mask 2 is the transparent substrate 2
It has a first region 2a formed by arranging only the phase shift pattern a on 0. The phase shift pattern a arranged in the first region 2a changes the phase of the exposure light by 180 °.
It consists of shifting shifters, has a width w, and has an interval p = w.
Are arranged in. The width w of the phase shift pattern a and the interval p = w are set to be larger than the width of the word lines arranged in the memory cell region 11a by the interval between the word lines. The total number of the phase shift patterns a and the number of spaces a ′ between the phase shift patterns a is equal to that of the word line arranged in the memory cell region 11a and the word line of the select transistor arranged adjacent to the memory cell region 11a. Configure so that the total number is the same. However, the memory cell area 11
The width and interval of the phase shift pattern corresponding to the word line portion of the select transistor arranged adjacent to a do not need to correspond to the width of the word line of the memory element arranged in the memory cell region 11a. It corresponds to the width of the word line.

In the other area on the transparent substrate 20 other than the first area 2a, that is, the second area 2b, the entire transparent substrate 20 is covered with the light-shielding film pattern b or arranged in the peripheral area 11b. A light-shielding film pattern b for forming a word line portion (excluding the word line portion of the select transistor arranged adjacent to the memory cell region 11a) is arranged. In this way, when the light-shielding film pattern b for forming the word line portion is formed in the second region 2b of the exposure mask 2, the memory cell region 11a is formed.
It is possible to perform the exposure for forming the word line portion disposed in the peripheral region 11b and the word line portion disposed in the peripheral region 11b at one time.

The exposure using the exposure mask 2 having the above structure is
It is performed as follows. That is, the first of the exposure mask 2
In the portion of the resist film 18 exposed using the region 2a, a so-called unexposed portion in which the irradiation intensity of the exposure light is insufficient to polymerize the negative resist is generated. This is shown in Figure 3.
As shown in FIG. 3A, the phase of the exposure light passing through the portion where the phase shift pattern a is arranged and the portion where the phase shift pattern a is not arranged in the first area 2a of the exposure mask 2 are alternately reversed as shown in FIG. As a result, as shown in the graph of the irradiation intensity of the exposure light in FIG. 3C, the phase shift pattern a
This is because the exposure lights cancel each other at the boundary portion of, and the irradiation intensity of the exposure light at this portion is weakened. Therefore,
The width P of the unexposed image (22) is narrower than the resolution limit of exposure light. On the other hand, the resist film 18 portion exposed by using the second region 2b of the exposure mask 2 shown in FIGS. 1C and 2C corresponds to the arrangement portion of the light shielding film pattern b. A pattern image 23 (not shown in the plan view of FIG. 2) is formed. The width of the pattern image 23 is larger than the width of the resolution limit of the exposure light.

After the exposure is performed as described above, the resist film 18 is developed to remove the unexposed portion of the resist film 18. As described above, the polycide layer 17
A resist pattern 18a made of a negative resist on top
To form The resist patterns 18a are arranged at intervals smaller than the resolution limit of the exposure light in the memory cell area 11a, and at intervals larger than the resolution limit of the exposure light in the peripheral area 11b.

After the resist pattern 18a is formed on the polycide layer 17 as described above, etching is performed using the resist pattern 18a as a mask. As a result, as shown in FIGS. 1 (4) and 2 (4), the word line 17a made of the polycide layer 17 is formed, and the interpoly insulating film 16 and the floating gate formation layer 15 are patterned.

Next, after removing the resist pattern 18a, an impurity for forming a diffusion layer 19 to be a source / drain is introduced into the surface side of the semiconductor substrate 11 exposed between the word lines 17a by ion implantation. This impurity is n-type when the storage element and the selection transistor are n-channel transistors, and is p-type when the storage element and the selection transistor are p-channel transistors.

Next, as shown in the sectional view of FIG. 4, an interlayer insulating film 41 is formed on the semiconductor substrate 11 in a state of covering the word line 17a. After that, a contact hole 42 connected to the diffusion layer (drain diffusion layer) 19 is formed in the interlayer insulating film 41 in the peripheral region 11b. Next, the bit contact 43 connected to the bottom surface of the contact hole 42
And the bit line 44 is formed in a state of being connected to the bit contact 43. As described above, the contactless NAND nonvolatile memory device 1 is manufactured.

In the nonvolatile memory device 1 manufactured as described above, the word lines 17a arranged in the memory cell region 11a are arranged at intervals narrower than the limit of lithography. Therefore, the degree of integration of the storage elements arranged in the storage cell region 11a can be improved.

Next, FIG. 5 is a sectional process view for explaining a second embodiment in which the method for manufacturing a nonvolatile memory device according to the present invention is applied to a method for manufacturing a NOR type nonvolatile memory device. The nonvolatile memory device manufactured here is a contactless NOR nonvolatile memory device such as a separated source type, a common source type, or a virtual installation type.

Even when the present invention is applied to the method of manufacturing each NOR type nonvolatile memory device, the memory cell area is the same as the method of forming the NAND type nonvolatile memory device described in the first embodiment. Lithography is performed when forming the word lines inside. That is, as shown in FIG.
A negative resist film 18 is formed on a polycide layer 17 for forming a word line, and then only a phase shift pattern a is arranged on a transparent substrate 20 to form a first region 2a.
Exposure for forming the word line is performed using the exposure mask 2 having However, the word lines of the select transistors arranged in the peripheral regions 11b on both sides of the memory cell region 11a of the semiconductor substrate 11 are the memory cell regions 11a.
Since the distance between the word line and the word line is large, the exposure is performed using the second region 2b of the exposure mask 2 in which the light shielding film pattern b is arranged.

Next, the resist film 18 that has been exposed using the exposure mask 2 is developed to form a resist pattern 18a made of the negative resist film 18. Then, the polycide layer 17 is etched using the resist pattern 18a as a mask. As a result, the word line 17a made of the polycide layer 17 is formed as shown in FIG. Then, after removing the resist pattern (18a), a resist pattern (not shown) is formed here, and ion implantation is performed to form the diffusion layer 19 to be the source / drain.

Next, as shown in FIG. 5C, another resist pattern (not shown) is formed here, and ion implantation for forming the channel stop diffusion layer 51 is performed.
Next, as in the first embodiment described with reference to FIG. 4, the interlayer insulating film 41 is formed in a state of covering the word line 17a, and then the contact hole 42, the bit contact 43, and the bit line 44 are formed. To do. As described above, the contactless NOR type nonvolatile memory device 5 is manufactured.

FIG. 6A shows a circuit diagram of the separated source NOR type nonvolatile memory device manufactured as described above, and FIG. 6B shows a memory cell region of the nonvolatile memory device. The top view of the main part 61 is shown. Further, FIG. 7A shows a circuit diagram of a common-source NOR type nonvolatile memory device manufactured as described above, and FIG. 7B shows a memory cell region of the nonvolatile memory device. The part 71 top view is shown. Further, FIG. 8A shows a circuit diagram of the virtual ground type NOR non-volatile memory device manufactured as described above, and FIG. 8B shows a memory cell region of the non-volatile memory device. The part 81 top view is shown.

As shown in each of these figures, even when the manufacturing method of the present invention is applied to the manufacturing method of the NOR type nonvolatile memory device, the interval P between the word lines 17a of the memory elements in the memory cell region is It can be narrower than the lithography limit, and the area per unit cell can be reduced.

In each of the drawings for explaining the first and second embodiments, the unit cell is composed of eight transistors. However, the number of transistors per unit cell is not limited to the above, and the larger the number of transistors, the greater the reduction rate of the area per unit cell.

[0030]

As described above, according to the method of manufacturing the nonvolatile memory device of the present invention, the boundary portion of the phase shift pattern is used in the lithography exposure when forming the word line of the contactless nonvolatile memory device. It is possible to arrange the word lines at intervals below the resolution limit of the exposure light by forming an unexposed portion in which the exposure light dose is insufficient to polymerize the negative resist. Therefore, the area of the memory cell region in which the word lines are arranged can be reduced, and the contactless nonvolatile memory device can be highly integrated. Further, according to the exposure mask of the present invention, it becomes possible to carry out the method for manufacturing a non-volatile memory device without increasing the number of steps.

[Brief description of drawings]

FIG. 1 is a sectional process view (part 1) for explaining a first embodiment;
It is.

FIG. 2 is a plan process diagram for explaining the first embodiment.

FIG. 3 is a diagram illustrating exposure using only a phase shift pattern.

FIG. 4 is a sectional process diagram (2) for explaining the first embodiment.
It is.

FIG. 5 is a sectional process diagram illustrating the second embodiment.

FIG. 6 is a diagram showing an example of application to a separation source type device.

FIG. 7 is a diagram showing an example of application to a common source type device.

FIG. 8 is a diagram showing an example of application to a virtual ground type device.

FIG. 9 is a circuit diagram of a contactless NAND-type nonvolatile memory device.

FIG. 10 is a sectional process diagram illustrating a conventional manufacturing method and an exposure mask.

[Explanation of symbols]

2 exposure mask 2a first area 2b second area 11a memory cell area 11b peripheral area 17a
Word line 18 Resist film 20 Transparent substrate 43 Bit contact (contact) a Phase shift pattern

Claims (2)

[Claims] 1. A method of manufacturing a non-volatile memory device, wherein a contact is arranged in a peripheral region outside a memory cell region, wherein in lithography exposure for forming a word line in the memory cell region, A non-volatile memory device, comprising: exposing a negative resist film, which serves as a mask when forming the word lines, by using an exposure mask portion in which only shift patterns are arranged on a transparent substrate. Manufacturing method. 2. An exposure mask used for manufacturing a non-volatile memory device in which contacts are arranged in a peripheral region outside a memory cell region, wherein only phase shift patterns for forming word lines are arrayed. An exposure mask, wherein the first region and the second region having the light shielding pattern are arranged on the same transparent substrate.