JPH08228148A - PLL control method - Google Patents

Abstract

Provided is a PLL control method capable of shortening a lockup time at the time of changing a set frequency without lowering the signal purity of an output signal. In a PLL control method of supplying a control signal based on set frequency data and an output of a voltage controlled oscillator 6 to a voltage controlled oscillator 6 via a low-pass filter 5, the set frequency data is set in a PLL calculation unit 1. In response to the signal of, the characteristics of the low pass filter 5 are changed so as to temporarily shorten the lockup time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a PL that operates so that the output signal frequency always matches the set frequency.
The present invention relates to an L control method.

The PLL synthesizer circuit is a negative feedback circuit that operates so as to match the set frequency with the output signal frequency, and a low-pass filter is interposed in the negative feedback loop to improve the signal purity of the output signal. Has been done. Therefore, when the set frequency is switched, a lockup time based on the time constant of the low pass filter is required until the output signal frequency is fixed at the set frequency.

[0003]

2. Description of the Related Art In order to explain a conventional PLL control method, an example of a conventional PLL synthesizer circuit will be described with reference to FIG. 5, in which a clock signal CK, a set frequency data DA and a strobe signal are supplied from an external circuit to a PLL arithmetic unit 1. When STB is input and the strobe signal STB is input in the state where the set frequency data DA is input, the set frequency data DA is set to the PLL calculation unit 1 based on the clock signal CK.
Written in. Then, the PLL calculation unit 1 causes the crystal oscillator 2 to
The set frequency data DA is divided on the basis of the reference frequency of and the set signal fr is output to the phase comparator 3.

Further, the output signal of the prescaler 7 described later is input to the PLL arithmetic unit 1, and the PLL arithmetic unit 1 divides the output signal of the prescaler 7 and outputs it to the phase comparator 3 as a feedback signal fp.

The phase comparator 3 has a setting signal fr and a feedback signal f.
Based on p and pulse signals φr and φp depending on the frequency and phase difference between the two signals, the charge pump 4 outputs the output signal SG1 shown in FIG. 6 based on the pulse signals φr and φp. Low-pass filter 5 (hereinafter L
(Referred to as PF). The output signal SG1 includes a pulse component in the direct current component, and the direct current component rises and falls with the fluctuation of the frequency of the pulse signals φr and φp, and the pulse component corresponds to the phase difference between the pulse signals φr and φp. Changes based on

That is, when the phase of the pulse signal φp lags behind the frequency of the pulse signal φr, the output signal SG1
The H component PH of the pulse component of the output signal SG1 is larger than that of the pulse signal φr of the output signal SG1.

The LPF 5 is an output signal S of the charge pump 4.
An output signal SG2 obtained by smoothing G1 and removing the pulse component is output to a voltage controlled oscillator (hereinafter referred to as VCO) 6, and the VCO 6 outputs an output signal SG3 having a frequency corresponding to the voltage value of the output signal SG2 of the LPF5.

Further, the output signal SG3 of the VCO 6 is frequency-divided by the prescaler 7 and fed back to the PLL arithmetic unit 1 and further frequency-divided by the PLL arithmetic unit 1 and output to the phase comparator 3 as the feedback signal fp. To be done.

In such a PLL synthesizer circuit, when the set frequency data DA is changed from the frequency F1 to the frequency F2 by an external input, it is output from the PLL arithmetic unit 1 in response to the input of the strobe signal STB shown in FIG. 7 (a). The frequency fr1 of the setting signal fr is increased to, for example, fr2, and the output signal SG1 of the charge pump 4 becomes
Since the DC level increases as shown in (c), the voltage value of the output signal SG2 of the LPF5 also increases as shown in (d) of FIG. The frequency of the output signal SG3 of is also shifted from the frequency F1 that has been set up to that point to the newly set frequency F2. Since the output signal SG3 of the VCO 6 is always fed back to the PLL calculation unit 1 via the prescaler 7, the negative feedback loop operates so that the feedback signal fp matches the new setting signal fr2. Also, the setting signal f
When r is lowered, the DC level of the output signal SG1 of the charge pump 4 is lowered and similarly converges to a new set frequency.

Therefore, in such a PLL synthesizer circuit, one crystal oscillator 2 can output various frequencies with stability equivalent to that of crystal control. Note that in FIG. 7C, only the change in the DC level of the output signal SG1 of the charge pump 4 is displayed, and the display of the pulse component contained in the output signal SG1 is omitted.

[0011]

However, in the PLL control method as described above, the output signal SG of the charge pump 4 is
Since 1 is output to the VCO 6 via the LPF 5, the DC level of the output signal SG1 of the charge pump 4 changes based on the change of the set frequency data DA, and then the frequency of the output signal SG3 of the VCO 6 changes to the new set frequency F2. There is a lock-up time t1 based on the time constant of the LPF5 until it converges to, and when this PLL synthesizer circuit is used for a tuner, it becomes impossible to tune during this lock-up time t1 and noise is output. There is a problem.

Therefore, if the time constant of the LPF 5 is reduced in order to reduce the lockup time t1, the pulse component matched with the output signal SG1 of the charge pump 4 is input to the VCO 6, so that the output signal SG3 of the VCO 6 is output.
There is a problem that signal distortion is caused and the signal purity is lowered.

An object of the present invention is to provide a PLL control method capable of shortening the lockup time when changing the set frequency without lowering the signal purity of the output signal.

[0014]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the PLL synthesizer circuit outputs the control signal output from the PLL control unit 11 to the voltage controlled oscillator 6 via the low pass filter 5 based on the set frequency data from the outside and the output of the voltage controlled oscillator 6 and outputs the voltage. The output of the controlled oscillator 6 is configured to match the set frequency. Here, in the present invention, a method of changing the characteristics of the low-pass filter 5 in response to a signal for setting the set frequency data in the PLL control unit 11 and temporarily shortening the lockup time is adopted. To change the characteristics of the low pass filter 5, for example, the switching unit 8 is used.

(Operation) When the set frequency is changed, the characteristics of the low-pass filter 5 are changed so as to respond to the signal for setting the set frequency data in the PLL control section 11 and temporarily shorten the lockup time. To be

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. The same components as those in the conventional example are denoted by the same reference numerals, and description thereof is omitted.

The present embodiment shown in FIG. 2 has the same configuration as the conventional example except that the analog switch 8 is connected in parallel to the LPF 5 as a switching unit. Then, the strobe signal S is applied to the analog switch 8.
The analog switch 8 is closed only when TB is input and the strobe signal STB is input.

The detailed structure of the charge pump 4 will be described with reference to FIG.
The phase comparator 3 which is composed of an OS transistor and is connected to the input terminal of the phase comparator 3 and the PLL operation unit 1 at the preceding stage (both not shown in FIG. 3) have a CMOS structure. The analog switch 8 is composed of a pair of MOS transistors 9 and two inverters 10. The analog switch 8, the charge pump 4, the phase comparator 3 and the PLL operation unit 1 are Bi / CMOS.
The LPF 5 and the VCO 6 are external circuits that are housed in a single chip. In addition, the PLL control unit of the present invention includes a PLL calculation unit 1, a crystal oscillator 2 as an oscillator, a phase comparator 3, a charge pump 4, and a prescaler 7 in the present embodiment.

The VCO 6 is basically a Colpitts oscillator circuit, and is composed of capacitors C3, C4, C5, a coil L2 and an oscillating transistor T1. The resistors R1 and R2 are used to supply a base potential,
The coil L1 supplies the collector potential. The capacitors C1 and C2 are used to separate the input terminal voltage Vt from the collector potential in terms of DC.

Further, the capacitance value of the varicap Vc1 varies depending on the Vt level to vary the oscillation frequency of the Colpitts oscillator circuit, and the capacitor C6 changes the oscillation frequency to AC.
It is used to get out in a join.

Next, the operation (PLL control method) of the PLL synthesizer circuit having such a configuration will be described with reference to FIG. Now, as in the conventional example, new set frequency data DA is input to the PLL arithmetic unit 1 in order to change the output frequency of the VCO 6, and the strobe signal STB is input as shown in FIG. PL as shown in 4 (b)
When the setting signal fr1 output from the L arithmetic unit 1 is pulled up to the same fr2, the operation of the phase comparator 3 and the charge pump 4, as shown in FIG.
The DC level of the output signal SG1 output from the device increases.

At this time, since the analog switch 8 is closed based on the H-level strobe signal STB, the output signal SG1 of the charge pump 4 is output to the LPF 5 and also to the VCO 6 via the analog switch 8. Therefore, the output signal SG3 of the VCO 6 shifts from the frequency F1 that has been output until then to the same F2 with a slight lock-up time t2. When the strobe signal STB shifts to the L level, the analog switch 8 is opened and the output signal S of the charge pump 4 is sent to the VCO 6.
Since G1 is input as the output signal SG2 via the LPF5, the output signal SG3 from the VCO 6 has high signal purity.

As described above, in this PLL control method, when the set frequency data DA is changed and the set signal fr output from the PLL arithmetic unit 1 is changed, the analog switch 8 is closed based on the input of the strobe signal STB. Since the output signal SG1 of the charge pump 4 is directly output to the VCO 6 without passing through the LPF 5, the output signal SG3 of the VCO 6 is set to the same frequency F1 newly set from the frequency F1.
It is possible to quickly shift to 2 with a slight lockup time t2, and after the strobe signal STB shifts to the L level, an output signal SG3 without distortion is output from the VCO 6 based on the output signal SG2 of the LPF 5.

Further, the analog switch 8 is housed in the same chip together with the charge pump 4, the phase comparator 3, the PLL arithmetic unit 1, etc. Moreover, since the analog switch 8 is opened / closed based on the input of the strobe signal STB, it is an analog switch. Since it is not necessary to newly provide a special detection circuit for opening and closing 8, it is possible to reduce the circuit area of this PLL synthesizer circuit and to improve the reliability against noise mixed from the outside.

[0025]

As described in detail above, the present invention is excellent in providing a PLL control method capable of shortening the lockup time when changing the set frequency without lowering the signal purity of the output signal. Be effective.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a block diagram of a PLL synthesizer circuit embodying the present invention.

FIG. 3 is a circuit diagram showing a specific configuration of part of a PLL synthesizer circuit.

FIG. 4 is a waveform diagram showing the operation of the PLL synthesizer circuit.

FIG. 5 is a block diagram of a conventional PLL synthesizer circuit.

FIG. 6 is a waveform diagram showing an output signal of the charge pump.

FIG. 7 is a waveform diagram showing the operation of a conventional PLL synthesizer circuit.

[Explanation of symbols]

 5 Low-pass filter 6 Voltage controlled oscillator 8 Switching unit 11 PLL control unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takehiro Akiyama 1844-2, Kozoji-cho, Kasugai-shi, Aichi Within Fujitsu Viels S Co., Ltd. (72) Inventor Isoshi Takekawa 1844-2, Kozoji-cho, Kasugai-shi, Aichi Fujitsu Within VIS Co., Ltd.

Claims (7)

[Claims] 1. A PLL control method for supplying a control signal based on set frequency data and an output of a voltage controlled oscillator to a voltage controlled oscillator through a low-pass filter, wherein a signal for setting the set frequency data to a PLL control unit is used. A PLL control method which responds and changes the characteristic of the low-pass filter so as to temporarily shorten the lock-up time. 2. The PLL control method according to claim 1, wherein the signal for setting the set frequency data in the PLL control unit is a strobe signal. 3. The PLL control method according to claim 1, wherein the time for changing the characteristic of the low-pass filter is longer than the lock-up time. 4. The PLL control method according to claim 1, wherein the characteristic of the low-pass filter is changed by short-circuiting both ends of the low-pass filter. 5. The PLL control method according to claim 1, wherein the characteristic of the low-pass filter is changed by invalidating the characteristic. 6. The PLL control method according to claim 5, wherein the low pass filter is invalidated by short-circuiting both ends thereof. 7. The change in the characteristics of the low-pass filter is
The PLL control method according to claim 1, wherein the PLL control method is performed by changing the time constant.