JPH0823816B2 - Micro program change device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram control device, and more particularly to a device for modifying a microprogram stored in a control memory.

[Conventional technology]

Conventionally, even if the microprogram stored in the control memory is partially modified, after assembling the entire microprogram including the modified microinstruction on another computer, the service processor (SVP), etc. This is accomplished by replacing the entire microprogram by using the initial microprogram load (IMPL) function of the maintenance mechanism of.

Japanese Unexamined Patent Publication (Kokai) No. 62-31432 describes a device for temporarily modifying (modifying) a micro instruction at the time of execution. This device is intended to support the development of microprograms, not to rewrite microinstructions in the control memory during operation.

[Problems to be Solved by the Invention]

In the conventional method, the entire microprogram is replaced by the IMPL process, so that the data processing must be interrupted during that period. By the way, changes in microprograms are aimed at eliminating bugs, changing or strengthening functions, etc.
Nowadays, it is necessary to do it quite often, and now that the reliability of the hardware has improved, the number of times data processing is interrupted due to changes in microprograms is often
Over 10 times the interruption due to a failure.

The object of the present invention is to provide only microinstructions that require modification
Moreover, it is possible to rewrite the program substantially in parallel with the normal execution of the microprogram, thereby minimizing the loss of data processing time due to the operation of partial modification of the microprogram.

[Means for solving the problem]

The microprogram changing device of the present invention comprises means for storing information for identifying the address of a microinstruction to be changed, and means for writing desired address identification information in the storage means in parallel with normal execution of the microprogram. A means for detecting that the address identified by the address identification information is accessed during the execution of the microprogram, and a means for suppressing the execution of the microinstruction read from the address in response to the output of the detecting means. , A means for transferring the microinstruction changed to the address in response to the output of the detecting means, and a means for restarting the microinstruction read execution circuit for the same address following the transfer.

[Action]

According to the above configuration, in parallel with the execution of the microprogram, the information indicating the change target address is written in the storage device therefor, and the microinstruction is read from the change target address during the execution of the microprogram. Then, it is detected and execution of the microinstruction is blocked, instead the modified microinstruction is written to that address, which is subsequently read and executed. It That is, the microinstruction is rewritten without interrupting the data processing.

〔Example〕

FIG. 1 shows the essentials of the embodiment described in detail later, thereby helping to clearly understand the concept of the present invention.
The control memory (CS) 1 and the microinstruction reload instruction bit memory (CRIS) 2 have the same address, and each address of CRIS2 is a bit that takes the value of "1" when the microinstruction of that address should be changed. Is written early in the microprogram change operation. Then, as the microprogram is executed, the contents of the control memory address register (CSAR) 3 are supplied to both CS1 and CSIR2, thus the contents of CRIS2 at the same address as the microinstruction read for execution, That is, the micro instruction reload instruction bit 100 is read. This bit 100 is "1"
Then, the microinstruction execution inhibiting means 101 operates to inhibit the execution 102 of the microinstruction read from the address, and further rewrites 103 the microinstruction at the address.
Then, when it is finished, execution 104 of the rewritten microinstruction is performed.

FIG. 2 is a block diagram showing an embodiment of the present invention. Control memory (CS) 1, control memory address register (CSAR) 3, control memory data register (CSD)
R) 4, CSDR delay register (CSDRD) 11, and decoder 14
The part consisting of and is a normal microprogram control mechanism. In the normal state, when CS1 is accessed according to the address from CSAR3, the microinstruction data at that address is read into CSDR4, transferred from there to CSDRD11, and then the corresponding control signal 201 via decoder 14.
And is supplied to the controlled hardware 15. On the other hand, CS
Next microinstruction address section 202 of microinstruction in DR4
Is set in CSAR3 via selector 16 and specifies the address of the next microinstruction. Original data of the contents of CS1 (C
SD) is held in an auxiliary memory (for example, a magnetic disk) not shown.

According to the present invention, a microinstruction reload instruction bit memory (CRIS) 2 is provided. CRIS2 has the same address as CS1, and the capacity (word length) of each address is 1 bit. Normally, all bits in CRIS2 are "0". When a partial change in the microprogram is required, the operator must write the original microprogram data (CS
The change target microinstruction in D) is rewritten, and the change target address instruction data (ID) consisting of the change target address and the reload instruction bit with the value "1" is stored in the auxiliary memory, and the service processor (not shown) is stored. (SVP)
To change the microprogram. In response to this command, the SVP transfers the ID71 and CSD72 to the appropriate area 7 of main memory (which may be predetermined or specified by the operator) and then the CRI.
Start writing the reload instruction bit to S2.

First, the CS reload permission latch (CREL) 9 is reset. When CREL9 is in the reset state, selector 17
The reload instruction bit 203 in the ID 71 transferred from the VP is selected, and the selector 18 selects the CRIS address register (ISA) 19
, The change target address 204 in the ID 71 transferred from the SVP is selected. Therefore, the address to be changed is supplied to the address selection circuit of the CRIS2 via the selector 18, and the corresponding reload instruction bit is passed through the selector 17 and the reload instruction data register (RIDR) 5 to the writing circuit of the CRIS2. As a result, to the same CRIS2 address as the microinstruction target address,
"1" is written. Similarly, "1" is written in all other addresses to be changed in CRIS2. CREL9
Is in the reset state, the output of the AND circuit 12 is fixed to "0", so that CRIS2 is not referred to when the microprogram is executed. Therefore, the writing of the reload instruction bit to the VRIS2 is performed in parallel with the execution of the microprogram.

When the writing of the reload instruction bit to CRIS2 is completed, the SVP sets a latch (not shown) requesting the setting of CREL9, and then at an appropriate processing point (eg, EOP: End of Process) of the microprogram,
The above request is accepted and CREL9 is set. As a result, the selectors 17 and 18 are set to "0" and CS, respectively.
Switched to select the output of AR3, and then CSIR2
Will be read in synchronization with CS1.

Thereafter, every time a micro instruction is read from CS1, the contents of CRIS2 at the same address as that are read. CSA
The contents of R3 are the contents of the CSAR delay register (CC
ARD) 8 to prepare for saving the change target address described later. If the output 205 of CRIS2 is "0", the microinstruction read at that time is unchanged. In this case, AND circuit 1
The output of 2 is "0", and the microinstruction read from CS1 is executed normally. On the other hand, CRIS output 205 is “1”
Then, the output of the AND circuit 12 becomes "1" and the CS reload mode latch (CRML) 10 is set. Set CRML
The "1" output of 10 inhibits the normal functioning portion of the decoder 14 and prevents execution of the then read microinstruction.
Update of CSARD8 is prohibited by “1” output of CRML10, thereby saving the change target address. The "1" output of the AND circuit 12 is also a microprogram routine (CS reload routine) for writing a new microinstruction into CS1.
2. Activate the logic circuit 13 that controls the break-in to.

When the break-in control logic circuit 13 is activated, the STAR
A T signal is generated to activate the execution stage for the CR reload routine, and the selector 16 is switched to set the start address of the CS reload routine to CSAR3. The CS reload routine started in this way is the corresponding CSD7
2 (the address can be determined from the change target address stored in CSARD8 and the start address of the CSD in the main memory 7) is read into the CS write data register (CSWDR) 6 and the selector 17 The "0" selected by is set in RIDR5, the change target address in CSARD8 is transferred to CSAR3, and then CS1 and CRIS2 perform a write operation, which causes the microinstruction changed to CS1. While writing, reset the reload instruction bit in CRIS2 to "0". Finally, the CRML10 is reset, the normal function part of the decoder 14 is restored, and then
The normal microprogram execution sequence is resumed. As a result, the contents of CSAR3 at this point specify CS
The content of the address (address to be changed), that is, the microinstruction just rewritten, is read and executed. CS
During the execution of the reload routine, only the dedicated function part of this routine works in the microinstruction decoding / execution mechanism, and the normal function part is frozen. CREL9 is
It may be reset when the rewriting of all microinstructions that require modification is complete. However, after the entire contents of CRIS2 have been reset to "0", the output of the AND circuit 12 will not be "1", so the state of CREL9 does not affect the execution of the microprogram. It is sufficient to reset CREL9 at the beginning of the next change operation.

FIG. 3 is a diagram for explaining the micro instruction execution stage. The EX0 stage is a stage for accessing CS1, the EX1 stage is a stage for reading microinstructions, and the EX2 stage is a stage for decoding and executing microinstructions. The target address of CRIS2 is accessed and CRM in EX1 stage is accessed.
When L10 is set, its output inhibits the energizing signal EX2 of the EX2 stage, thereby preventing the execution of the microinstruction read from the address to be changed. CR
What is suppressed by the set output of ML10 is the decryption / execution portion 14a for normal functions, and the dedicated decryption / execution portion 14b of the CS reload routine belongs to the EXR2 stage described below, and the CS reload routine is executed. Is urged when The symbols TA and TB in the figure represent the timing at which data is set, and TB occurs in the middle of adjacent TAs.

FIG. 4 is a time chart of the microinstruction rewriting operation, and shows a case where the microinstruction is rewritten. When the microinstruction enters the EX1 stage, CRML10 is set to "1", which inhibits the execution of the microinstruction and the subsequent EX0 / EX1 / EX2 stages. Instead, C corresponding to EX0 / EX1 / EX2 stages respectively
EXR0 / EXR1 / EXR2 stages dedicated to S reload are started by the START signal at the same time when the CS reload routine start address is generated. The microinstruction address is stored in CSARD8 and set in CSAR3 just before the modified microinstruction is written to CS1. CRML10 is reset at the same time as the writing to CS1 is started, and following the end of writing to CS1, the EX0 / EX1 / EX2 stages are restarted and the microinstruction just rewritten is read and executed.

FIG. 5 shows another embodiment of the present invention. The difference from the embodiment shown in FIG. 2 is that the CS reload processing is performed by the SVP instead of the microprogram. In this embodiment, when CRML10 is set, after the EX0 / EX1 / EX2 stages are suppressed as in the embodiment of FIG.
In response to the CS reload request to the VP, the SVP responds to the C
S Reload processing 20 is performed. That is, SVP transfers the address to be changed stored in CSARD8 to CSAR3,
Write the corresponding CSD72 to CS1 and reset the reload instruction bit in CRIS2. After that, SVP
Resets CRML10 and restarts the microprogram execution stage (21).

In the embodiment shown in FIG. 2, microinstructions can be rewritten at high speed, but on the other hand, hardware dedicated to CS reload is required. The embodiment of FIG. 5 does not require such special hardware, but is slower.

Instead of CRIS2, a register group that stores the change target address and a comparator that compares the contents of CSAR3 with the contents of this register group may be used. However, in this variant, 1
The number of microinstructions that can be changed in one operation is limited by the number of registers.

[Effects of the Invention] According to the present invention, a microprogram can be changed substantially in parallel with the execution of the microprogram. Therefore, the data processing, which is the original task, is interrupted due to the change of the microprogram. You don't have to let me.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of the present invention.
2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram showing a microinstruction execution stage in the apparatus of FIG. 2, and FIG. 4 is a time chart of microinstruction rewriting operation in the apparatus of FIG. , Fifth
The figure is a block diagram of another embodiment of the present invention. 1 ... Control memory, 2 ... Memory for storing reload instruction bit for identifying change target address, 3 ... Control memory address register, 7 ... Main memory area, 8 ... Save accessed change target address Register for resetting, 10 ... Latch reset when the change target address is accessed, 12 ... AND circuit for detecting that the change target address is accessed, 13 ... Logic for activating the control memory rewriting routine Circuit, 14 …… Micro instruction decoding / execution circuit, 71 …… Change target address data,
72 …… Changed microinstructions.

Claims (3)

[Claims] 1. A microprogram controller having a rewritable control memory for storing a plurality of microinstructions forming a microprogram at respective addresses, and a circuit for sequentially reading and executing the microinstructions from the control memory. A means for storing the changed microinstruction, a means for storing information for identifying the address of the microinstruction to be changed, and a desired execution of the microprogram in the address identification information storage means for normal execution of the microprogram. Means for writing in parallel, means for detecting that an address identified by the address identification information is accessed during execution of the microprogram,
Means for suppressing execution of a microinstruction read from the address in response to the output of the detecting means, and means for transferring the modified microinstruction to the address in response to the output of the detecting means, Means for restarting the read execution circuit for the same address following the transfer. 2. The microprogram changing device according to claim 1, wherein the address identification information storage means has the same address as the control memory and stores information indicating whether each address is a change target address or not. . 3. The microinstruction transfer means and the restart means according to claim 1 or 2, wherein the microinstruction transfer means and the restart means are controlled by a part of the microprogram, and the read execution circuit is a dedicated part for the part of the microprogram. A microprogram changer including.