JPH01199231A - Microprogram changing device - Google Patents

Abstract

PURPOSE:To omit the stoppage of the computer drive that is needed for change of a microprogram and to reduce the loss of the data processing time by using a microinstruction rewriting means while the computer is working. CONSTITUTION:A control memory 1 and a microinstruction reloading instruction bit memory CRIS2 have the same addresses. Then the bit that secures the value '1' when the microinstruction of each address of the CRIS2 should be changed is written into said address in the early stages of the changing operation of a microprogram. Then the contents of a control memory address register 3 are supplied to the memory 1 and the CRIS2 as the microprogram is carried out. Then a microinstruction execution suppressing means 101 works in case the contents read out of the CRIS2 are equal to '1'. Thus the execution 102 of the microinstruction is suppressed. Then the execution 104 of the rewritten microinstruction is carried out after the rewriting 103 of the microinstruction is ended.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and in particular,
The present invention relates to a device for modifying microprograms stored in a control memory.

[Conventional technology]

Traditionally, changes to microprograms stored in control memory, even partial changes.

After assembling the entire microprogram including the changed microinstructions on another computer, the entire microprogram is replaced using the initial microprogram load (IMPL) function of a maintenance mechanism such as a service processor (SVP). It is carried out by this.

Japanese Unexamined Patent Publication No. 62-31432 describes a device for temporarily modifying microinstructions at the time of execution. This device is intended to support the development of microprograms, and does not rewrite microinstructions in control memory during operation.

[Problem to be solved by the invention]

In the conventional method, the entire microprogram is replaced by IMPL processing, so data processing must be interrupted during that period. By the way, the reality is that changes to microprograms are required quite frequently for purposes such as removing bugs, changing or enhancing functions, and now that hardware reliability has improved, it is often necessary to change microprograms. Data processing is interrupted more than 10 times more often due to changes than due to failures.

An object of the present invention is to make it possible to rewrite only the microinstructions that require modification, and substantially in parallel with the normal execution of the microprogram, thereby making it possible to process data that accompanies partial modification of the microprogram. The goal is to keep time loss to a minimum.

[Means to solve the problem]

The microprogram changing device of the present invention includes means for storing information identifying the address of a microinstruction to be changed, and means for detecting that an address identified by address identification information is accessed during execution of the microprogram. , means for suppressing execution of the microinstruction read from the address in response to the output of the detection means; means for transferring the changed microinstruction to the address in response to the output of the detection means; and means for restarting a microinstruction read execution circuit for the same address following the transfer.

[Effect]

According to the above configuration, during execution of the microprogram,
When a microinstruction is read from a modified address, this is detected, execution of the microinstruction is prevented, and a modified microinstruction is written to that address in its place; The microinstruction that was created is read and executed. That is, the microinstructions are rewritten while the computer is operating.

〔Example〕

FIG. 1 shows the main points of the embodiments described in detail later, thereby helping to clearly understand the concept of the present invention. Control memory (C8) 1 and microinstruction reload instruction pin I
- Memory (CRIS) 2 has the same address and CRIS
Each address in RIS2 has a pin that takes the value 1" when the microinstruction at that address is to be modified.
Written early in a microprogram change operation. Thereafter, as the microprogram is executed, the contents of control memory address register (C3AR) 3 are changed between C3I and C3.
IR2 and thus the contents of CRIS2 at the same address as the microinstruction read for execution, ie, the microinstruction reload indication bit 100, is read. If this bit 100 is 111 I+, the microinstruction execution inhibiting means 101 operates, inhibiting the execution 102 of the microinstruction read from the address, and further rewriting the microinstruction 103 at the address.
is performed, and upon completion of this, the rewritten microinstruction is executed 104.

FIG. 2 shows in block diagram form one embodiment of the invention. The control memory (C8) 1, the control memory address register (C8AR) 3, and the control section are common microprogram control-like grooves.

Under normal conditions, when the CSI is accessed according to the address from C3AR3, the microinstruction data at that address is read to C3DR4, and from there the C3DRD
After being transferred to II, it becomes a corresponding control signal 201 via the decoder 14 and is supplied to the controlled hardware 15. On the other hand, the next microinstruction address field 202 of the microinstruction in C3DR4 is transferred to the C3A through the selector 16.
Set to R3 to specify the address of the next microinstruction. The original data (C8D) of the contents of C81 is as follows.

It is held in an auxiliary memory (for example, a magnetic disk) that is not shown.

According to the invention, a microinstruction reload indication bit memory (CRIS) 2 is provided. CRIS2 is C3I
The capacity (word length) of each address is 1-pi. usually.

All bits in CRISZ are "0". When it is necessary to partially change the microprogram, the operator rewrites the microinstruction to be changed in the microprogram original data (C8D) in the auxiliary memory, and writes the microinstruction to be changed to the address to be changed and a load instruction bit with a value of "1". The change target address instruction data (ID) is stored in an auxiliary memory and is executed by a service processor (not shown).
P) to change the microprogram. In response to this command, SvP transfers ID 71 and C3D 72 to an appropriate area 7 in main memory (this area may be predetermined or specified by the operator) 5 and then to CRIS 2. Start writing the glue load instruction bit.

First, the CS reload permission clutch CREr,)9 is reset. When the CREL9 is in the reset state, the selector 17 selects the load instruction bit 203 in the ID71 transferred from SvP, and the selector 18 selects the CRI
The contents of the S address register (ISA) 19, that is, s
Change target address 20 in ID71 transferred from vp
Select 4. Therefore, the address to be changed is supplied to the address selection circuit of the CRIS 2 via the selector 18, and the corresponding reload instruction bit is supplied to the selector 17 and the reload instruction data register (RIDR) 5.
is supplied to the write circuit of CRIS2, and as a result,
11'' is written to the same CRIS2 address as the address of the microinstruction to be changed.Similarly, CRIS
tz 1 to all other modified addresses in 2.
pp is written. When CREL9 is in the reset state, CRIS2 is not referenced during microprogram execution. Therefore, the above-mentioned writing of the load instruction bit to VRIS2 is performed in parallel with the execution of the microprogram.

When the writing of the load instruction bit to CRIS2 is completed, SvP writes the latch (
(not shown), and then set an appropriate processing point of the microprogram (for example, E OP: End o
f Process), the above request is accepted and CREL9 is set.

As a result, selector 17 and selector 18 are each “
O” and C3AR3 output.
Then, C3IR2 is read out in synchronization with C8l.

Thereafter, every time a microinstruction is read from C81, the contents of CRIS2 at the same address are read. Note that in the normal state (C5ARD), the contents of C3AR3 are transferred to the C5AR delay register Δ8° in preparation for saving the address to be changed, which will be described later.

If the output 205 of CRIS2 is "0", there is no change in the microinstruction read at that time. In this case, the output of the AND circuit 12 is II OII, and the microinstruction read from CSt is executed as usual. On the other hand, CR
If the IS output 205 is 11111, the AND circuit 12
The output of becomes “1” and the CS reload mode latch (C
RML) Set to 10.

The set CRMLlo “1” output is the decoder 1
4 is inhibited from executing the microinstruction read at that time. For updates of C5AndD8, please refer to CR
It is prohibited by outputting "1" of MLlo, thereby saving the address to be changed.

The output of the AND circuit 12 is also used as a microprogram routine (
The logic circuit 13 that controls break-in to the CS reload routine is activated.

When the break-in control logic circuit 13 is activated, the 5T
The ART signal is generated to activate the execution stage for the CR reload routine, and the selector 16 is switched to set the start address of the CS reload routine to C3AR3. The OS reload routine started in this way is executed by the corresponding C3D72 (its address is C8AR
Address to be changed stored in D8 and main memory 7
) is read to the C8 write data register (C5WDR) 6, and "0" selected by the selector 17 is set to RIDR5, and then the change in C8ARDB is read out to the C8 write data register (C5WDR) 6. After transferring the target address to C3AR3, C8I and CR
Make IS2 perform a write operation, thereby writing the modified microinstruction to C81 and resetting the load instruction bit in CRISZ to 0''.Finally,
CRMLlo is reset to restore normal functioning of the decoder 14, and the normal microprogram execution sequence then resumes. As a result, at this point C
The contents of the OS address (address to be changed) specified by the contents of 3AR3, that is, the rewritten microinstruction, are read out and executed. While the CS reload routine is being executed, only the special function part of this routine is operated in the microinstruction decoding/execution mechanism, and the normal function part is frozen. Note that CREL 9 may be reset when all microinstructions that require modification have been rewritten.

However, after all the contents of CRIS2 are reset to "0", the output of the AND circuit 12 will never become "1", so the state of CREL9 will not affect the execution of the microprogram, and therefore the state of CREL9 will not affect the execution of the microprogram. It is sufficient to perform the reset at the beginning of the primary change operation.

FIG. 3 is a diagram for explaining the microinstruction execution stage. The EXO stage is a stage for accessing C81, the EXI stage is a stage for reading microinstructions, and the EX2 stage is a stage for decoding and executing microinstructions. CRI
When the change target address of S2 is accessed and CRMLlo in the EXI stage is set, the output suppresses the energizing signal EX2 of the EX2 stage,
This prevents execution of the microinstruction read from the address to be changed. What is suppressed by the set output of CRMLIO is the decoding/execution part 14a for normal functions, and the dedicated decoding/execution part 14b of the CS reload routine belongs to the EXR2 stage, which will be described later.
Energized when the S reload routine is executed. Note that symbols TA and TB in the figure represent timings at which data is set, and TB occurs between adjacent TAs.

FIG. 5 is a time chart of the microinstruction rewriting operation, and shows the case where the microinstruction (2) is rewritten. When the microinstruction ■ enters the EXI stage, CRMLlo is set to “1”, thereby inhibiting the execution of the microinstruction ■, and subsequent EXO/EXI/EX2
The stage is suppressed. Instead, EXO/EXI/EX
EX dedicated to CS reload corresponding to each 2X stage
The RO/EXRI/EXR2 stage is started by the 5TART signal at the same time as the CS reload routine start address is generated. The address of microinstruction ■ is C5AR
The microinstruction ■ saved in the D8 and modified is the C81
Set to C3AR3 immediately before being written to C3AR3. C8
At the same time as writing to C81 begins, CRMLIO is reset, and following the end of writing to C81, EXO/EXI
The /EX2 stage is restarted, and the rewritten microinstruction (2) is read and executed.

FIG. 5 shows another embodiment of the invention. This differs from the embodiment of FIG. 2 in that the CS reload process is performed by SvP rather than by a microprogram.

In this embodiment, when CRMLIO is set, after inhibiting the EXO/EXI/EX2 stage similar to the embodiment in FIG. 2, a CS reload request is issued to SvP,
In response to this, SvP performs CS reload processing 20.

That is, after SvP transfers the change target address stored in C3ARD8 to C3AR3, the corresponding C3
Writes D72 to C8I and resets the load instruction bit in CRISZ. After that, SvP
resets the CR tag 10 and restarts the microprogram execution stage (21).

The embodiment shown in FIG. 2 allows microinstructions to be rewritten at high speed, but on the other hand, requires hardware dedicated to CS reload. The embodiment of FIG. 5 does not require such special hardware, but is slow.

Instead of CRIS2, a group of registers for storing addresses to be changed and a comparator for comparing the contents of C3AR3 with the contents of this register group may be used.

However, in this modification, the number of microinstructions that can be changed in one operation is limited by the number of registers.

〔Effect of the invention〕

According to the present invention, a microprogram can be changed substantially in parallel with its execution, and therefore there is no need to stop the computer for changing the microprogram.

[Brief explanation of the drawing]

FIG. 1 is a block diagram representing the concept of the present invention.
FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram showing microinstruction execution stages in the device shown in FIG. 2, and FIG. 4 is a time chart of microinstruction rewriting operation in the device shown in FIG. 2. , 5th
The figure is a block diagram of another embodiment of the invention. l... Control memory, 2... Memory for identifying the address to be changed or storing load instruction bits, 3... Control memory address register, 7... Area of main memory,
8...Register for storing the accessed address to be changed; 10...Latch that is reset when the address to be changed is accessed; 12...Detecting that the address to be changed has been accessed. AND
Circuit, 13...! Logic circuit for starting the IIIJ memory rewrite routine, 14... Microinstruction decoding/execution circuit, 71... Address data to be changed, 72...
Modified microinstructions.

Claims (1)

[Scope of Claims] 1. A microprogram that has a rewritable control memory that stores a plurality of microinstructions constituting the microprogram at respective addresses, and a circuit that sequentially reads and executes the microinstructions from the control memory. In a control device, means for storing a changed microinstruction, means for storing information identifying an address of the microinstruction to be changed, and an address identified by the address identification information being accessed during execution of the microprogram. means for detecting that the microinstruction has been changed to the address in response to the output of the detection means; A microprogram modification device comprising means for transferring a microinstruction and means for restarting said read execution circuit for the same address following said transfer. 2. The microprogram changing device according to claim 1, wherein the address identification information storage means has the same address as the control memory, and stores information indicating whether each address is a change target address or not. 3. In claim 1 or 2, the microinstruction transfer means and restart means are controlled by a part of the microprogram, and the read execution circuit is a microprogram including a dedicated part for the part of the microprogram. Change device.