JPH08274346A - Semiconductor device and circuit using the same - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain a high performance amplifier circuit and mixer circuit by obtaining a dual gate FET with secured gate breakdown voltage and improved characteristics. [Structure] The intrinsic partial conductance during voltage control of a dual gate FET is made larger when using the first gate electrode 53 than when using the second gate electrode 54, and the drain breakdown voltage is the second.
By making the gate electrode 54 larger than the first gate electrode 53, deterioration of mutual conductance is eliminated and the breakdown voltage of the element is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having improved characteristics, a low noise amplifier circuit and a mixer circuit using the semiconductor device.

[0002]

2. Description of the Related Art In order to improve the characteristics of a circuit, instead of a normal single gate field effect transistor (FET), two gates are provided between a source and a drain to enable stable high gain high frequency amplification, and a dual gate. FET is used. The conventional dual gate FET is, for example,
E-E-Transaction on Electron Device (IEEE Trans. Electron Dev)
ices) ED-25, (1978), p. 580.

In this dual gate FET, a GaAs channel layer 2, an undoped InGaAs barrier layer 3 and an n-type contact layer 4 are laminated on a semi-insulating GaAs substrate 1 as shown in FIG. A source electrode 51 and a drain electrode 52 are provided on the upper side, and a first gate electrode 53 and a drain electrode 5 are provided near the source electrode 51.
Although the second gate electrode 54 is formed near 2, the first gate electrode 53 and the second gate electrode 54 are usually formed simultaneously in the same step.

[0004]

In the conventional dual gate FET described above, the first gate electrode and the second gate electrode were manufactured by the same process, and the characteristics were the same. When such an FET is applied to a high-power amplifier, a mixer, or the like, it is essential to increase the gate breakdown voltage, but there is a problem that the parasitic resistance increases as the breakdown voltage increases.

An object of the present invention is to improve the characteristics of a semiconductor device having first and second control electrodes like the gate electrode of a dual gate FET while ensuring the withstand voltage of the control electrode, and at the same time, to improve the characteristics of the semiconductor device. To obtain a high-performance low noise amplifier circuit and mixer circuit.

[0006]

The above object is to provide a carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and a channel region of the channel region. In a semiconductor device having a first control electrode and a second control electrode provided above a channel region for controlling a current, one of the first and second control electrodes, which is closer to the carrier injection part, is the first control. When the electrode is used, the transconductance of the intrinsic portion when the voltage is controlled by the first control electrode is larger than the transconductance of the intrinsic portion when the voltage is controlled by the second control electrode.

In the above semiconductor device, the first
When one of the second control electrode and the second control electrode which is closer to the carrier injection part is used as the first control electrode, the Schottky reverse breakdown voltage between the first control electrode and the electrode of the carrier extraction part is the second control electrode.
It is achieved by being larger than the Schottky reverse breakdown voltage between the control electrode and the electrode of the carrier extraction portion.

Further, the first control electrode is configured such that the distance from the channel region directly below to the first control electrode is smaller than the distance from the channel region directly below the second control electrode to the second control electrode, or The channel conductivity type ionized impurity concentration in the channel region directly below the control electrode is
This is achieved by setting the concentration of ionized impurities of the channel conductivity type of the channel region immediately below the second control electrode to be lower.

Further, the semiconductor material in contact with the second control electrode is different from the semiconductor material in contact with the first control electrode, and further, the semiconductor material is more electronic than the semiconductor material with which the first control electrode is in contact. Since the carrier that travels in the channel is an electron, which is a material having a small affinity, the semiconductor material has a larger sum of the electron affinity and the band gap than the semiconductor material in contact with the first control electrode. Then, it can be achieved by the fact that the carriers traveling in the channel are holes.

Further, the first and second control electrodes are
By disposing the heterojunction formed in the semiconductor recess on the heterojunction, or by varying the shape of the recess, or by disposing the first control electrode of the recess in the width of the second This is achieved by being narrower than the width where the control electrode is located.

Further, the channel region is a semiconductor layer formed by a heterojunction on a semiconductor substrate, and a semiconductor layer for supplying carriers which does not contain ionized impurities is provided above or below the channel region. By being spatially separated from the channel region, or by containing an ionized impurity of the same type as the polarity of carriers flowing in the channel when a voltage is applied between the first control electrode and the carrier injection part. , Respectively achieved.

Further, the semiconductor substrate is a GaAs substrate, and the channel region is GaAs or InGaAs.
And the semiconductor layer for supplying the carrier is Al
The channel region is made of GaAs, the channel region is made of GaAs in the GaAs substrate, and the semiconductor layer for carrier supply is made of GaAs or AlGaAs. Alternatively, the channel region is made of In in the GaAs substrate.
The semiconductor layer made of GaAs and supplied with carriers is InAl
By using As, the channel region is made of InAs in the GaAs substrate, and the semiconductor layer for supplying carriers is made of AlGaSbAs.

Further, the above-mentioned object is that the semiconductor substrate is made of In
It is a P substrate, the channel region is made of InGaAs,
This can be achieved when the semiconductor layer for supplying carriers is made of InAlAs.

Furthermore, the semiconductor device described in each of the above items, means for inputting a signal to the first control electrode of the semiconductor device, and means for applying a DC voltage to the second control electrode. A low noise amplifier circuit can be obtained by including a means for grounding the carrier injecting section and configuring a circuit for outputting from the carrier extracting section.

Furthermore, the semiconductor device described in each of the above items, means for inputting a high frequency signal to the first control electrode of the semiconductor device, and means for applying a DC voltage to the second control electrode. A mixer circuit can be obtained by forming a circuit for outputting a signal from the carrier extraction unit, which has a unit for inputting a local signal and a unit for grounding the carrier injection unit.

[0016]

When a semiconductor device such as a dual gate FET is used as an amplifier, the circuit configuration normally becomes as shown in FIG. 7. However, when simulating this circuit configuration, the model is simplified for simplicity. In many cases, cascode connection of a single gate FET as shown in FIG. 8 is used instead. In this case, the first FE whose source is grounded
T corresponds to the first gate electrode control portion of the dual gate, and the second FET whose gate is grounded corresponds to the second gate electrode control portion of the dual gate. Below, a simulation was performed in the circuit configuration shown in FIG.
A commercially available simulator using the harmonic balance method was used for the simulation, and a stats model was adopted as the device model. Table 1 shown below shows the largest sensitivity coefficient with respect to the output.

[0017]

[Table 1]

As shown in the table, it is understood that the transconductance of the first FET, the gate-drain capacitance and the drain conductance of the second FET have a great influence. Therefore, it can be seen that the improvement of the mutual conductance of the first FET and the reduction of the gate-drain capacitance and the drain conductance of the second FET are effective for improving the performance.

The potential-current correlation diagrams (dynamic load lines) at the drain electrode position of the first FET and the drain electrode position of the second FET obtained by the above simulation are shown in FIGS. 9 and 10, respectively. A voltage slightly more than twice the power supply voltage is applied to the drain electrode of the second FET, but almost no voltage is applied to the first FET. That is, it is understood that the withstand voltage of the FET is determined by the second FET. However, when measuring the transconductance and the Schottky reverse breakdown voltage of the gate, when measuring one gate, the other gate is in an open state.

It is generally known that the transconductance decreases when the withstand voltage of a semiconductor device such as the above FET is improved and the capacitance between the carrier injection portion and the extraction portion such as the gate-drain is reduced. . From these facts, in order to manufacture a semiconductor device such as a high performance dual gate FET having the first and second control electrodes, the withstand voltage of the first FET shown in FIG. By improving the mutual conductance while sacrificing the capacitance of the second FET, and improving the breakdown voltage and reducing the capacitance between the carrier injection portion and the carrier extraction portion while sacrificing the transconductance of the second FET. Can be optimized.

[0021]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a sectional structural view showing a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional structural view showing a second embodiment of the present invention, and FIG. 3 is a sectional structural view showing a third embodiment of the present invention. , Fig. 4
FIG. 8 is a diagram showing a circuit of a high output amplifier according to a fourth embodiment of the present invention. In the following description of materials, AlGaA
s is a part of Ga atoms in GaAs replaced by Al, InGaAs is a part of Ga atoms in GaAs replaced by In, and InAlAs is a part of Al atoms in AlAs. Is replaced with In.

First Embodiment FIG. 1 shows a sectional structure of a dual gate FET as a first embodiment of the semiconductor device of the present invention. Semi-insulating GaA
on the s substrate 1 by the molecular beam epitaxy (MBE) method, an undoped GaAs buffer layer (thickness: 500 nm) 5,
Undoped InGaAs channel layer (In composition: 0.2
5, thickness: 8 nm) 2, undoped AlGaAs spacer layer (Al composition: 0.25, thickness: 2 nm) 6, n-A
lGaAs carrier supply layer (Al composition: 0.25, thickness: 15 nm, Si concentration: 2 × 10 ¹⁸ / cm ³ ) 7, undoped AlGaAs barrier layer (Al composition: 0.25,
(Thickness: 10 nm) 3, and finally n-GaAs cap layer (Si concentration: 7 × 10 ¹⁸ / cm ³ , thickness: 16)
0 nm) 4 is deposited. A region including the channel layer 2 is mesa-type etched to separate elements (the etched portion is not shown), and then an insulating film made of SiO is deposited. A source electrode 51 which is an electrode of a carrier injection part and a drain electrode 52 which is an electrode of a carrier extraction part are formed by a lift-off method described below. First, an opening is formed in the insulating film by a normal photolithography process to form a lift-off mask. Also,
The opening of the insulating film is side-etched by wet etching to have a shape that facilitates lift-off. further,
The n-GaAs cap layer 4 is etched by wet etching to about 40 nm. AuGe / Mo / Au is used for the source and drain electrode materials, and after vapor deposition of the material, heat treatment at 400 ° C. is performed for 5 minutes in a nitrogen atmosphere.

Next, a photoresist pattern having an opening for the second gate electrode which is the second control electrode is formed by the same photolithography process, and an opening is provided in the insulating film by dry etching. Next, the n-GaAs cap layer 4 is removed by dry etching. At this time, side etching is performed by isotropic etching, and a region larger than the opening is removed by etching. The side etching amount is 0.5 μm. Next, the second gate electrode 54 having a gate length of 0.5 μm is undoped A
It is formed on the 1GaAs barrier layer 3 by lift-off.
Mo / Al is used as the gate electrode material. Note that the structure of the gate electrode is not limited to the Schottky gate and may be a gate having another structure.

Next, a new resist is applied to form a resist pattern having an opening for the first gate electrode which is the first control electrode, and an opening is provided in the insulating film by dry etching. Next, dry etching is applied to nG
The aAs cap layer 4 is removed. At this time, side etching is performed by isotropic etching, and a region larger than the opening is removed by etching. The side etching amount is 0.2 μm. Next, the first gate electrode 53 having a gate length of 0.3 μm is formed on the undoped AlGaAs barrier layer 3 by lift-off. Mo / Al is used as the gate electrode material. Thus, the semiconductor device having the structure shown in FIG. 1 was realized.

The semiconductor device according to the first embodiment has a source resistance of 0.4 Ω.mm and a gate resistance of 0.3 Ω.
mm, saturation output 33 dBm at 1.9 GHz, output 19 dB gain at compression point 19 dB, and power added efficiency 57%.

Second Embodiment FIG. 2 shows a cross sectional structure of an FET which is a second embodiment of the present invention. On the semi-insulating GaAs substrate 1, an undoped GaAs buffer layer (thickness: 500 nm) 5, an undoped InGaAs channel layer (In composition: 0.25, thickness: 8 nm) 2, an undoped AlGaAs by a molecular beam epitaxy (MBE) method. Spacer layer (Al composition: 0.25, thickness: 2 nm) 6, n-AlGaAs carrier supply layer (A
l composition: 0.25, thickness: 15 nm, Si concentration: 5 × 1
0 ¹⁸ / cm ³ ) 7, an undoped AlGaAs barrier layer (Al composition: 0.25, thickness: 10 nm) 3, an undoped GaAs cover layer (thickness: 20 nm) 8, an undoped AlGaAs layer (Al composition: 0.25, (Thickness: 3 nm)
9 is grown, and finally an n-GaAs cap layer (Si concentration: 7 × 10 ¹⁸ / cm ³ , thickness: 160 nm) 4 is deposited.

After the region including the channel layer 2 is etched into a mesa type to separate elements (the etched portion is not shown), an insulating film made of SiO is deposited. The source electrode 51 and the drain electrode 52 are formed by the lift-off method described below. First, an opening is formed in the insulating film by a normal photolithography process,
Use a lift-off mask. In addition, the opening of the insulating film is side-etched by wet etching to have a shape that facilitates lift-off. Furthermore, the n-GaAs cap layer 4 is etched by wet etching to about 40 nm. The source / drain electrode material is AuGe /
After using Mo / Au, 400 in a nitrogen atmosphere after material deposition.
Heat treatment at ℃ for 5 minutes.

Next, a photoresist pattern having an opening for the second gate electrode is formed by the same photolithography process, an opening is formed in the insulating film by dry etching, and then n-Ga is formed by dry etching.
The As cap layer 4 is removed. At this time, side etching is performed by isotropic etching, and a region larger than the opening is removed by etching. Next, gate length 0.5μ
A second gate electrode 54 of m is formed on the undoped GaAs cover layer 8 by lift-off. Mo / Al is used as the gate electrode material.

After that, a new resist is applied, a desired position of the resist is opened by EB lithography for the first gate electrode, the insulating film and the n-GaAs cap layer 9 are removed by etching, and wet etching and directional dry are performed. An opening is provided in the undoped AlGaAs layer 8 by etching. Next, the first gate electrode 53 having a gate length of 0.3 μm is formed on the undoped AlGaAs barrier layer 3 by lift-off. Mo / Al for gate electrode material
To use. Thus, the semiconductor device having the FET having the structure shown in FIG. 2 was realized.

The device according to this embodiment has a source resistance: 0.
43 Ω · mm, resistance between gates: 0.28 Ω · mm, 1.
It showed high performance with a saturation output of 35 dBm at 9 GHz, an output of 1 dB at a compression point of 20 dB, and a power added efficiency of 60%.

The conditions of the first and second embodiments may be changed as follows. In the above embodiment, the thickness of the undoped AlGaAs spacer layer 6 is 2n.
Although m was used, good results were obtained in the range of 1 to 4 nm. Further, the ionized impurity concentration of the n-AlGaAs carrier supply layer 7 is not limited to the above, but is 0.3 to 6 × 10 ¹⁸ / c.
Good results can be obtained within the range of m ³ . The ohmic material used for the source and drain and the Schottky material for the gate are not limited to the above, and other materials such as Al, Pt / Ti / Pt / Au as the Schottky material.
As the ohmic material, a non-alloy ohmic material such as Ti / Au may be used. Similar results can be obtained by using an epitaxial crystal growth method in the manufacturing process, instead of the MBE method, in which the growth can be controlled in atomic layer units, for example, a metal organic chemical vapor deposition (MOCVD) method. Further, the n-GaAs cap layer 4 is not limited to GaAs, but may be a substance such as InGa that easily makes ohmic contact.
You may use As etc. Also, undoped A just under the gate
1 GaAs layer 3 and undoped GaAs cover layer 8
May use n-AlGaAs or the like having a breakdown voltage of 1 × 10 ¹⁷ / cm ³ or less so that the breakdown voltage is not reduced. In addition, ion implantation or the like may be used together to reduce parasitic resistance. Although the HEMT structure in which the channel and the ion impurity layer are spatially separated is used in the present embodiment, the present invention is not limited to this, and the carrier supply layer is arranged on both sides of the reverse HEMT on the substrate side and the channel. Double hetero HEMT,
HI with channel doped with ionized impurities
Other crystal structures such as GFET have the same effect. In addition, although the example of the N-channel FET is used in this embodiment, P
The same applies to the case of the channel FET. In this case, a P-type material such as carbon, beryllium, or magnesium may be used as the ionized impurities. The material is not limited to the GaAs / AlGaAs / InGaAs system used in this embodiment, but an Sb system material such as GaAsSb or InGaAsS.
When b or the like is used, the characteristics are further improved. Needless to say, the same effect can be obtained even if a material such as InP is used as the substrate material.
s, the characteristics are further improved by using InAlAs for the carrier supply layer.

Third Embodiment FIG. 3 shows a sectional view of a third embodiment of the present invention. The high breakdown voltage layer 8 is previously grown on the semi-insulating GaAs substrate 1, an insulating film is vapor-deposited, and openings for source and drain electrode regions are formed at desired positions by a normal photolithography process. Next, Si ion implantation (irradiation amount: 3 × 10 ¹³ / cm to ² , acceleration voltage: 125 k)
V) is performed. Further, an opening for forming a channel region is provided at a desired position by a photolithography process, and S
i ion implantation (irradiation dose: 5 × 10 ¹² / cm to ² , accelerating voltage: 80 kV) and Mg ion implantation (irradiation dose: 5 ×
10 ¹² / cm to ² and accelerating voltage: 150 kV). Further, for the N'layer, an opening is provided at a desired position by a photolithography process and Si ion implantation (irradiation dose: 1 ×
N ′ layer, accelerating voltage: 200 kV), and heat treatment at 850 ° C. for 20 minutes in an arsine atmosphere. Next, the high breakdown voltage layer 8 is left only around the place where the second gate electrode is arranged, and the high breakdown voltage layer 8 in other regions is removed by etching. Then, the source electrode 51 and the drain electrode 52 are formed by lift-off. A for source / drain electrode material
Using uGe / Mo / Au, heat treatment at 400 ° C. is performed for 5 minutes in a nitrogen atmosphere after the material deposition. As the lift-off mask, a mask having an opening formed in an insulating film by a normal photolithography process is used. In addition, the opening of the insulating film is side-etched by wet etching to have a shape that facilitates lift-off. Next, a desired portion is opened by an ordinary photolithography process, and the insulating film is removed by dry etching. Gate length 1μ
The gate electrodes 53 and 54 having a width of m and a gate width of 12 mm are formed by lift-off. Ti / P for gate electrode material
t / Au is used. The semiconductor device having the structure shown in FIG. 3 was realized as described above.

The semiconductor device according to this embodiment has a source resistance of 0.35 Ω · mm and a gate resistance of 0.3 Ω · m.
m, saturation output 30 dBm at 1.9 GHz, output 1
The gain was 17 dB at the dB compression point, and the power added efficiency was 55%, showing high performance.

The conditions in this embodiment may be set as follows. The Si and Mg ion implantation conditions, the annealing conditions, the electrode materials and the like are not limited to the above, and may be changed to appropriate conditions according to desired FET characteristics. Further, the N'layer and the Mg implanter may be omitted.
Further, a p-type buffer region may be provided by implanting with high energy rather than forming a channel of P-type ions such as Mg ions and Be ions. Further, although an example of an N-channel field effect transistor has been shown in these embodiments, good results can be obtained also in a P-channel, but this case can be achieved by making the N-doped layer a P-doped layer.

The gate metal material is Ti / Pt / A.
u was used, but not limited to this, Al, Ti / Al, WS
You may use i etc. Further, Mo / Au or the like can be used as the source and drain electrode materials. The process also employs the method of forming the gate by lift-off, but the method is not limited to this, and the method of forming the gate first and forming the implantation region in self-alignment may be used.

Fourth Embodiment A fourth embodiment of a high power amplifier using the semiconductor device of the present invention is shown in FIG. The dual gate FET 100 described in any of the first to third embodiments is formed on the semiconductor substrate together with the matching circuit using the line 113 and the capacitor 108. The high-power amplifier thus obtained has a drain voltage and a drain current of the FET 100 of 4.7 V and 30 mA, respectively, and an input signal power of 10 mA.
Under the conditions of 0 mW and frequency of 1.9 GHz, good performance such as conversion gain of 15 dB, noise figure of 2.5 dB, and input / output VSWR of 2 or less was obtained.

In this embodiment, an example of a so-called monolithic IC in which the matching circuit is on the same substrate has been shown, but a hybrid IC which is slightly deteriorated in performance but is easy to manufacture, that is, a matching circuit is not on the same substrate. But good results are obtained. The frequency band is 1.9.
Although the circuit in the GHz band is described, good characteristics were obtained in other frequency bands by changing the matching circuit. Furthermore, good characteristics were obtained even in applications where the operating current and operating voltage are small, for example, when low power consumption operation is required for car phones and mobile phones. In this case, the cell size required to obtain the same characteristics as those that could be realized using conventional elements,
I was able to reduce it to less than half. This is because the element obtained by the present invention has better performance than the conventional element, and thus a high-performance amplifier can be obtained even if the circuit is configured with a small number of elements.

[0038]

As described above, the semiconductor device according to the present invention includes a carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and In a semiconductor device having a first control electrode and a second control electrode provided above the channel region for controlling a current in the channel region, one of the first and second control electrodes, which is closer to the carrier injection portion, is selected. When the first control electrode is used, the withstand voltage is high because the transconductance of the intrinsic part when the voltage is controlled by the first control electrode is larger than the transconductance of the intrinsic part when the voltage is controlled by the second control electrode. A semiconductor device with good performance can be obtained, and the performance of a high output amplifier or the like using the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional structural view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional structural view showing a second embodiment of the present invention.

FIG. 3 is a sectional structural view showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a circuit of a high output amplifier according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a basic structure of a dual gate field effect transistor of the present invention.

FIG. 6 is a cross-sectional view showing a conventional dual gate field effect transistor.

FIG. 7 is a diagram showing an amplifier circuit using a dual gate FET.

FIG. 8 is a diagram showing an equivalent amplifier circuit using two single gate FETs.

FIG. 9 is a current-voltage correlation diagram at the drain electrode of the first FET.

FIG. 10 is a current-voltage correlation diagram at the drain electrode of the second FET.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Channel Region 51 Carrier Injection Part Electrode 52 Carrier Extraction Part Electrode 53 First Control Electrode 54 Second Control Electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Nakamura 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Metropolitan Research Center, Hitachi, Ltd. (72) Satoshi Tanaka 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Center

Claims (20)

[Claims] 1. A carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and a channel for controlling a current in the channel region. In a semiconductor device having a first control electrode and a second control electrode provided in the upper part of the region, when one of the first and second control electrodes closer to the carrier injection part is the first control electrode, the second control electrode is used. A semiconductor device, wherein the transconductance of the intrinsic portion when the voltage is controlled by the control electrode is larger than the transconductance of the intrinsic portion when the voltage is controlled by the first control electrode. 2. A carrier injection part and a carrier extraction part provided in a desired region of a semiconductor substrate, a channel region provided between the carrier injection part and the extraction part, and a channel for controlling a current in the channel region. In the semiconductor device having the first control electrode and the second control electrode provided on the upper part of the region, when one of the first and second control electrodes closer to the carrier injection part is the first control electrode,
A Schottky reverse breakdown voltage between the control electrode and the electrode of the carrier extraction portion is larger than a Schottky reverse breakdown voltage between the second control electrode and the electrode of the carrier extraction portion. 3. The first control electrode is characterized in that a distance from a channel region directly below to the first control electrode is smaller than a distance from a channel region directly below to the second control electrode to a second control electrode. The semiconductor device according to claim 1 or 2. 4. The first control electrode has a channel conductivity type ionized impurity concentration in a channel region immediately below the second control electrode,
3. The semiconductor device according to claim 1, wherein a concentration of ionized impurities of a channel conductivity type in a channel region directly below the control electrode is lower than that of the control region. 5. The semiconductor according to claim 1, wherein a semiconductor material in contact with the second control electrode is different from a semiconductor material in contact with the first control electrode. apparatus. 6. The semiconductor material with which the second control electrode is in contact has a smaller electron affinity than the semiconductor material with which the first control electrode is in contact, and the carriers traveling in the channel are electrons. The semiconductor device according to claim 5. 7. The semiconductor material in contact with the second control electrode has a larger sum of electron affinity and band gap than the semiconductor material in contact with the first control electrode, and carriers traveling in the channel are The semiconductor device according to claim 5, wherein the semiconductor device is a hole. 8. The first and second control electrodes are respectively disposed on the heterojunction formed in the semiconductor recess, and the first and second control electrodes are respectively disposed on the heterojunction. Semiconductor device. 9. The semiconductor device according to claim 8, wherein the recesses in which the first and second control electrodes are arranged have different shapes. 10. The recess in which the control electrode is arranged has a width in which the first control electrode is arranged is narrower than a width in which the second control electrode is arranged. Alternatively, the semiconductor device according to claim 9. 11. The semiconductor device according to claim 1, wherein the channel region is a semiconductor layer formed by a heterojunction on a semiconductor substrate. 12. The channel region does not contain ionized impurities, and a semiconductor layer for supplying carriers is arranged above or below the channel region and spatially separated from the channel region. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 13. The method according to claim 1, wherein the channel region contains ionized impurities of the same type as the polarities of the carriers flowing in the channel when a voltage is applied between the first control electrode and the carrier injection portion. Item 5. The semiconductor device according to any one of Items 4. 14. The semiconductor substrate is a GaAs substrate, the channel region is made of GaAs or InGaAs, and the semiconductor layer for supplying the carriers is Al.
The semiconductor device according to claim 1 or 2, which is made of GaAs. 15. The semiconductor substrate is a GaAs substrate, the channel region is made of GaAs, and the semiconductor layer for supplying the carriers is GaAs or AlGa.
Claim 1 or Claim 2 which consists of As.
13. The semiconductor device according to claim 1. 16. The semiconductor substrate is a GaAs substrate, the channel region is made of InGaAs, and the semiconductor layer for supplying the carriers is made of InAlAs. Semiconductor device. 17. The semiconductor substrate according to claim 1 or 2, wherein the semiconductor substrate is a GaAs substrate, the channel region is made of InAs, and the semiconductor layer for supplying the carriers is made of AlGaSbAs. Semiconductor device. 18. The semiconductor substrate is an InP substrate,
3. The semiconductor device according to claim 1, wherein the channel region is made of InGaAs, and the semiconductor layer for supplying the carriers is made of InAlAs. 19. A semiconductor device according to any one of claims 1 to 18, means for inputting a signal to the first control electrode of the semiconductor device, and a DC voltage to the second control electrode. An amplifying circuit comprising a means for giving and a means for grounding the carrier injecting section, and constituting a circuit for outputting from the carrier extracting section. 20. A semiconductor device according to any one of claims 1 to 18, means for inputting a high frequency signal to the first control electrode of the semiconductor device, and a DC voltage to the second control electrode. And a means for inputting a local signal, and a means for grounding the carrier injecting section, and forming a circuit for outputting from the carrier extracting section.