JPH0831465B2 - Method for forming bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] An emitter-base capacitance (C
_EB ), base collector capacitance (C _BC ), collector substrate capacitance (C _CS ), internal base resistance (R _b0 ), external base resistance (R
_As a method of reducing _bb ), a process utilizing selective epitaxial growth and an increase in film thickness due to oxidation of the polycrystalline semiconductor layer, that is, reduction of the opening width of the polycrystalline semiconductor layer due to oxidation is proposed.

[Industrial applications]

The present invention relates to a method for forming a high speed bipolar transistor.

Since the bipolar transistor is a high-speed element compared to the MOS transistor, it is often used in high-speed logic integrated circuits, memory integrated circuits, linear integrated circuits, and the like.

[Conventional technology]

In order to realize the high speed of the bipolar transistor,
Various attempts have been made to reduce the above-mentioned C _EB , C _BC , C _CS , R _b0 , R _bb, etc. Here, a transistor having a normal structure will be described as a conventional example.

FIG. 2 is a sectional view of a conventional bipolar transistor.

In the figure, 21 is a p-type semiconductor substrate, 22 is an n ⁺ -type buried layer having a high impurity concentration, 23 is an n-type epitaxial growth layer and constitutes a collector region, 24 is a p-type element isolation region, and 25 is a p-type.
Type impurity introduced layer constitutes a base region, 26 an n type impurity introduced layer constitutes an emitter region, 27 an n ⁺ type collector contact region, and 28, 29, 30 a conductive layer, respectively. , The base electrode and the emitter electrode, and 31 is an insulating layer.

In a transistor having such a structure, since a pattern shift usually exists between the bottom surface and the surface of the epitaxial growth layer 23, it is necessary to form another mark for alignment in the lithography process.

In addition, the base region 25 must be considerably larger than the emitter region 26 in order to secure the insulation distance between the base electrode 29 and the emitter electrode 30. However, the intrinsic transistor region (operating region) that participates in the transistor function is only the region directly below the emitter region 26, and the other regions are for extracting the base electrode, and the size should be as small as possible for speeding up. Is desirable.

[Problems to be solved by the invention]

In the bipolar transistor according to the conventional example, (1) the base region must be made larger than the functionally required size, which is a constraint for high integration and further limits the operation speed.

(2) Since there is a pattern shift between the bottom surface and the surface of the epitaxial growth layer, it hinders the fine processing of the pattern.

However, it is difficult to form a high speed, highly integrated bipolar transistor.

[Means for solving problems]

To solve the above problems, a base region of another conductivity type semiconductor layer is formed on a collector region of one conductivity type semiconductor layer, an oxidation resistant insulating layer is formed on the base region, and the oxidation resistant insulating layer is covered. A polycrystalline semiconductor layer is grown, the polycrystalline semiconductor layer is opened to expose the oxidation resistant insulating layer, the opening of the polycrystalline semiconductor layer is oxidized to narrow the opening width, and the opening is narrowed from the opening. Formation of a bipolar transistor including a step of etching the oxidation-resistant insulating layer, opening the oxidation-resistant insulating layer to expose the base region, and burying one conductivity type semiconductor layer in the opening by selective growth to form an emitter region Achieved by the method.

The collector region is formed by depositing an insulating layer on a substrate, opening the insulating layer in a transistor forming region, and burying a single conductivity type semiconductor layer in the opening by selective growth, and the base region is formed. It is even more effective when another conductive type semiconductor layer is epitaxially grown on the entire surface of the substrate so as to cover the collector region.

[Action]

The present invention aims at speeding up by utilizing the following action.

(1) A very fine emitter region can be formed by forming the opening width smaller than the mask size of the opening for forming the emitter region by utilizing the volume expansion due to the oxidation of the polycrystalline semiconductor layer. Therefore, C _EB and R _b0 are reduced.

(2) The size of the base region is reduced along with the small size of the emitter region, and C _BC and R _bb are reduced.

(3) _CCS is reduced because the collector region is formed in a fine opening by using selective epitaxial growth.

As described above, since the fine emitter region can be formed, the base contact can be drawn out from the side wall of the base region, and the base region can be formed to the minimum necessary size, the parasitic capacitance and parasitic resistance can be reduced, Higher speed is possible.

In addition, since a normal full-face epitaxial process is not used, there is no pattern shift, and the process is suitable for miniaturization.

〔Example〕

1 (1) to (5) are sectional views of a bipolar transistor according to the present invention, which are shown in the order of manufacturing steps.

In FIG. 1 (1), 1 is a semiconductor substrate, and the surface index (11
1) p-type silicon (Si) substrate, 11 is a layer resistance of 20 Ω / neck, 1.5 μm thick n ⁺ type buried layer, arsenic ion (As ⁺ ) energy 60 KeV, dose 10 ¹⁶ cm ^-2 It is formed by injecting.

Next, chemical vapor deposition (CVD) is performed on the entire surface of the substrate as an insulating layer.
1 μm thick silicon dioxide (SiO ₂ ) layer 2 is grown.

CVD-SiO ₂ is monosilane (SiH ₄ ) and nitric oxide (NO)
The mixed gas of is reduced to 2 Torr and pyrolyzed at 800 ° C to grow.

Next, patterning is performed by an ordinary lithography process to form a collector region forming opening having an opening width a of 1.7 μm.

Next, an n-Si layer 3 having a thickness of 1 μm and a carrier concentration of 5 × 10 ¹⁶ cm ⁻³ is deposited as a collector region only in the opening by selective epitaxial growth of Si.

Here, doping is performed during epitaxial growth
Type.

For selective epitaxial growth of Si, silane dichloride (SiH ₂ Cl ₂ ) and a doping gas were used as reaction gases, and
The pressure is reduced to 0 Torr and the hydrogen reduction method is performed at 1100 ° C.

Next, single crystal Si is grown on the single crystal Si layer and poly Si is grown on the insulating layer by epitaxial-poly Siw growth. That is, by normal epitaxial growth on the entire surface of the substrate, a single crystal p-Si layer 4A having a thickness of 1000 to 2000Å and a SiO ₂ layer 2 as a base region are formed on the n-Si layer 3 in the collector region.
A p-poly Si layer 4B having a thickness of 1000 to 2000Å is grown on the top.

Epitaxial-poly Si growth uses SiH ₄ as a reaction gas.
Is used, and this is pyrolyzed at 760 Torr and 1050 ° C.

Dope contains 1 × 10 of boron (B) during epitaxial growth.
Doped with ¹⁸ cm ^-3 or boron ion (B ⁺ ) after epitaxial growth with energy of 40 KeV and dose of 10 ¹⁴ cm ^-2
Inject.

The p-poly Si layer 4B is further implanted with B ⁺ at a high concentration to form a base contact region.

The implantation conditions of B ⁺ at this time are energy 60 KeV and dose 10
¹⁶ cm ^-2 .

In Fig. 1 (2), silicon nitride (Si
₃ N ₄ ) layer is deposited on the entire surface of the substrate and patterned to form an oxidation resistant insulating layer with a thickness of 500 to 1 on the p-Si layer 4A in the base region.
A 000Å Si ₃ N ₄ layer 5 is formed.

CVD-Si ₃ N ₄ grows by decompressing a mixed gas of SiH ₄ and ammonia (NH ₃ ) to 3 Torr and thermally decomposing at 800 to 900 ° C.

Next, the Si ₃ N ₄ layer 5 is covered, and a thickness of 3000 is obtained by the CVD method.
Å, B-doped p-poly Si with carrier concentration of 1 × 10 ²⁰ cm ^-3
The layer 6 and the SiO ₂ layer 7 having a thickness of 3000 Å are sequentially grown.

In FIG. 1 (3), the SiO ₂ layer 7 and the p-poly Si layer 6 on the Si ₃ N ₄ layer 5 are opened to an opening width b of 0.5 μm by using ordinary lithography.

In FIG. 1 (4), p is obtained by using the Si ₃ N ₄ layer 5 as a mask.
-The poly-Si layer 6 is thermally oxidized to form an S
The iO ₂ layer 6A is formed.

At this time, the width d of the opening width becomes about 0.2 μm due to the expansion of the p-polySi layer 6 due to the oxidation.

Oxidation conditions are thermal oxidation with wet oxygen (O ₂ ) at 900 ° C.

In FIG. 1 (5), the Si ₃ N ₄ layer 5 exposed at the bottom of the narrowed opening is removed by etching with hot phosphoric acid (H ₃ PO ₄ ) to expose the p-Si layer 4A in the base region. To do.

Next, n-polySi is used as an emitter region in the opening.
Grow layer 8.

The doping of the emitter region is performed, for example, with As ⁺ energy of 100 Ke.
It is formed by implanting V at a dose of 10 ¹⁶ cm ^-2 and performing emitter drive at 1000 ° C.

This completes the formation of the main part of the transistor. After that, the emitter electrode is formed on the emitter region 8, the base electrode is opened on the p-polySi layer 6 and the n ⁺ -type buried layer 11 is formed by a normal process. The top is opened to form a collector electrode.

〔The invention's effect〕

As described in detail above, according to the present invention, it is possible to obtain a method for forming a planar bipolar transistor in which the base region can be functionally reduced to a necessary and sufficient size and the operating speed is improved.

[Brief description of drawings]

1 (1) to (5) are sectional views of a bipolar transistor according to the present invention shown in the order of manufacturing steps, and FIG. 2 is a sectional view of a conventional bipolar transistor. In the figure, 1 is a semiconductor substrate which is a p-type Si substrate, 11 is an n ⁺ -type buried layer, 2 is an insulating layer which is a SiO ₂ layer, 3 is a collector region which is an n-Si layer, and 4A is a base region which is p-Si. layer, 4B is p- poly-Si layer, the 5 Si ₃ N ₄ layer by oxidation insulating layer, is 6 p- poly-Si layer, 7 SiO ₂ layer, 8 is the emitter region n- poly-Si layer.

Claims (2)

[Claims] 1. A base region of another conductive type semiconductor layer is formed on a collector region of one conductive type semiconductor layer, an oxidation resistant insulating layer is formed on the base region, and the oxidation resistant insulating layer is covered to form a polycrystal. Growing a semiconductor layer, opening the polycrystalline semiconductor layer to expose the oxidation resistant insulating layer, oxidizing the opening of the polycrystalline semiconductor layer to narrow the opening width,
Etching the oxidation resistant insulating layer through the opening to expose the base region by opening the oxidation resistant insulating layer, and burying one conductivity type semiconductor layer in the opening by selective growth to form an emitter region. A method of forming a bipolar transistor including :. 2. The collector region is formed by depositing an insulating layer on a substrate, opening the insulating layer in a transistor forming region, and burying a single conductivity type semiconductor layer in the opening by selective growth. The method for forming a bipolar transistor according to claim 1, wherein the base region is formed by epitaxially growing another conductive type semiconductor layer on the entire surface of the substrate so as to cover the collector region.