JPH08314796A - Control circuit for dynamic ram - Google Patents

Abstract

PURPOSE: To shorten the write time in the case that data which are continuously vertically arranged as the print result are written in a dynamic RAM. CONSTITUTION: A CAS signal 608, an RAS signal 603, and an R/W signal 615 are inputted to a control circuit 616. When the CAS signal 608 rises or the CAS signal 608 is at a L level and the RAS signal 603 falls, the control circuit 616 makes an input circuit control signal 617 is made to fall to latch the state of an external data signal 611 in an input circuit 612 if the R/W signal 615 is at the L level. If the R/W signal 615 is at a H level, an output control signal 619 is set at the L level to output the state of an internal data signal 610 to the external data signal 611 through an output circuit 613 in the period when the CAS signal 608 is at the L level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM control circuit which contributes to high-speed data storage in a memory of an electrophotographic printer or the like.

[0002]

2. Description of the Related Art FIG. 2 is an explanatory diagram showing a conventional state of storing character data in an image buffer. Storage of character data in a conventional image buffer will be described with reference to this figure. In the present specification and drawings, numerical values with a B suffix are binary numbers, numerical values with a H suffix are hexadecimal numbers,
Those without a subscript are decimal numbers unless otherwise specified. In the circuit diagrams, time charts, and their descriptions, H is logically 1 at high potential, and L is logically 0 at low potential.
Is shown.

In FIG. 2, reference numeral 201 is character data (hereinafter referred to as font data) generally stored in a ROM or a RAM. If necessary, the printing mechanism part (hereinafter referred to as print data) can be printed as it is by the printing mechanism unit. It is copied as indicated by reference numeral 203 in the image buffer memory 202 in which the data of a raw point is called a pixel) is arranged. In the image buffer 202, other character data and pixel data for figures are arranged, and when necessary data for the page are complete, generally data is printed line by line from the uppermost pixel row (hereinafter, pixel row is referred to as line). Transfer to the mechanical section and apply ink to the position of the paper corresponding to 1 data (hereinafter referred to as marking)
However, by not applying ink to the position of the paper corresponding to the data of 0 (hereinafter referred to as non-marking), the contents of the image buffer 202 can be visually recognized on the print paper. Font data 201 is image buffer 202
The transition of the memory address, the value of each bit position, and the like in the case of being copied as indicated by reference numeral 203 in FIG.

In FIG. 3, reference numeral 204 is font data.
The area of the memory constituting 201 is shown. In this case, 8 bits in both the vertical and horizontal directions are the required areas for the data of one character. Reference numeral 205 is a relative address in which the first address of the font data is 0, and the bit position corresponding to the marking position of each address is 1, and the bit position corresponding to the non-marking position is 0, indicating the address and its contents. Reference numeral 208 shown in FIG. For example, relative address 3
The configuration content 207 corresponding to (206) is not marked from the left-not-is-not-is-not-is-not-is, and becomes 00100100B, that is, 24H (209).

FIG. 5 is an example of a partially enlarged view of the image buffer 202, and shows the relationship between the position of the portion 203 in the memory of the image buffer where the character data is copied and the address and bit position of the memory. That is, in this example, the number of pixels in the width direction of the image buffer 202 is eight times W, that is, one line requires W bytes. Therefore, when the address of the reference numeral 211 is Y, printing is performed immediately below the address data. The address of the storage location of the data to be stored is Y + W as indicated by reference numeral 214, and similarly, the address of the storage location 215 of the data to be printed on the 11th line below the reference numeral 211 is Y + 11 · W. However, Y is usually an integral multiple of W. In this example, font data 204 is coded from code 217
Copied to 218, the address is Y + W for 217
+1, the code 219 is Y + 2.W + 1, and the code 218 is Y + 8.W + 1. FIG. 6 shows the addresses of the image buffer 202 in which the font data 204 illustrated here and the contents thereof are stored in the memory, arranged in the order of the addresses of the memory. That is, in FIG. 5, the font data 204 is stored in continuous addresses, but in the memory 220 of the image buffer, as shown in FIG. 6, it is stored for each W address.

FIG. 7 is an explanatory diagram showing the input / output state of the dynamic RAM, and FIG. 8 is a time chart showing the operation of the dynamic RAM. In addition, in the description from FIG. 7 onward, the dynamic R has six address inputs and eight data input / output.
An example will be described in which 8-bit information can be stored in 4096 addresses of AM (hereinafter referred to as DRAM).

In FIG. 7, in a general DRAM 301, an address to be read or written is generated by synthesizing two time-divided address information, and each row latch signal (hereinafter RA
The address input 303 synchronized with the S signal) 302 is the high address, the address input 303 synchronized with the column latch signal (hereinafter referred to as the CAS signal) 304 is the low address, and the address consisting of all 12 bits is read / written from the DRAM. The address. The reference numeral 305 is DR
It is a signal (hereinafter referred to as R / W signal) indicating whether the operation for the AM301 is writing or reading, and H indicates reading and L indicates writing.

That is, as shown by reference numeral 306 in FIG.
If Adr1 is the target address, the upper 6 bits of that address data
Adr1H (310) is the falling edge (313) of the RAS signal (302).
) Appears in the address input 303 in synchronism with), and is held in the DRAM301 as the higher address of the DRAM301. Next, in synchronization with the falling edge (315) of the CAS signal 304, Adr1 is input to the address input 303.
Adr1L (311) representing the lower 6 bits of appears. Further, since the R / W signal 305 is L, a write operation occurs in the DRAM 301. Therefore, as shown in the figure, the data Dt1 (317) to be stored in the address Adr1 (306) appears on the data bus 318 before the CAS signal 304 rises, and the contents Dt1 (317) of the data Dt1 (317) by the time when the CAS signal 304 rises. Street number Adr1
Written at (306). The same applies to Adr2 in the figure.

FIG. 9 shows an example of the structure of the image buffer 202 shown in FIG. 5 using the DRAM shown in FIG. 7 when the width is 64 bytes, that is, when W = 64. In this example, since the DRAM 301 of FIG. 7 has a column address of 64 bytes for one row address, the number of pixels in the width direction of the image buffer 202 is also adjusted to 64 bytes. In FIG. 9, when the address 402 is Y, the storage location 404 of the data to be printed immediately below the address data in the print result is Y + 64.
Similarly, the address of the storage location 406 of the data to be printed at the beginning of the fifth line below the code 402 is Y + 5 × 64
= Y + 320 Here, in the same manner as shown in FIG. 5, when writing vertically arranged data in the print result, that is, data 1 (40
8), data 2 (409) and data 3 (410) are successively written in the addresses shown in FIG.

In FIG. 10, reference numerals 303, 302 and 304 are used.
Are address input, RAS signal, and CAS, as in Fig. 8.
This is a signal, and the target address, R / W signal, and D7-D0 are omitted. The address where the data 1 (408) is written is Y + 128 + 2, and if Y is a multiple of 64, the upper 6 bits of Y + 128 + 2 are (Y + 128 +
2) / 64 (the diagonal line “/” in the following formulas is the division operator) is (Y / 64) +2, and the lower 6 bits are (Y
+ 128 + 2) / 64 is a remainder, so it is 2 and corresponds to data 1.
Address input synchronized with the falling edge (504) of RAS signal 302
The value indicated by A5-A0 indicates Y / 64 + 2, and the address input A5-A0 that is also synchronized with the falling edge (506) of the corresponding CAS signal 304
Has a value of 2. RA for data 2 (409)
Address input A5 synchronized with the falling edge of S signal 302 (508)
-The value indicated by A0 indicates Y / 64 + 3, the value indicated by the address inputs A5-A0 synchronized with the falling edge (510) of the CAS signal 304 is 2, and the RAS for data 3 (410). The value indicated by the address inputs A5-A0 synchronized with the falling edge (512) of the signal 302 is
The value indicated by the address inputs A5-A0, which indicates Y / 64 + 4 and is synchronized with the falling edge (514) of the CAS signal 304, is 2.

[0011]

[Problems to be Solved by the Invention] In FIG.
The values indicated by the address inputs A5-A0 synchronized with the trailing edge of the signal 304 are all 2. Therefore, there is redundancy as information. When writing the data continuously arranged vertically in the print result, when writing to the DRAM 301 in the sequence shown in FIG. 10, the time is not optimized. That is, writing should be possible even faster.

[0012]

In order to solve the above problems, the present invention relates to a dynamic RAM control circuit for fetching an external data signal into a dynamic RAM by a row address latch signal and a column address latch signal. When updating the contents of the address in the same column direction, the external data signal is taken in at the falling edge of the column address latch signal when the row address latch signal is at the low level, and the row address latch when the column address latch signal is at the low level. It is characterized in that a control circuit is provided for latching an external data signal and capturing the internal data signal when the signal falls.

[0013]

According to the present invention having the above configuration, when updating the contents of the addresses in the same column direction of the data storage unit, the control circuit causes the row address latch signal to fall when the column address latch signal is at the low level. The external data signal is latched and taken into the internal data signal. Therefore, when the row address latch signal falls, the row address data synchronized with the row address latch signal and the column address data synchronized with the column address latch signal are simultaneously fetched, and the fetching time can be shortened.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a multiplex circuit of a DRAM according to an embodiment of the present invention.

In FIG. 1, reference numeral 600 is an address multiplex circuit (hereinafter referred to as ADRM) which designates a specific cell in a memory cell array by a combination of a row address and a column address of a normal DRAM.
This circuit 600 is arranged in parallel in the DRAM 301 shown in FIG. 7. Reference numeral 601 is a group of address input signals of the DRAM 301 similar to that shown in FIG.
Reference numeral 602 denotes a row address buffer which latches the address input signal group 601 at the falling edge of the RAS signal 603, the output of which is input to the row decoder 604, and the row decoder 604 selectively selects one memory cell according to the input. The row selection signal is valid. For example, when the row address buffer 603 outputs a signal group corresponding to 50, the row decoder 604 validates the 50th memory cell row selection signal, and the information of the 50th memory cell row reaches the sense amplifier array 606. .

Reference numeral 607 designates an address input signal group 601 as a CAS signal.
A column address buffer that latches at the falling edge of 608,
The output is input to the column decoder 609, and the column decoder 609 selectively validates one sense amplifier selection signal according to the input. The sense amplifier in the sense amplifier array 606 corresponding to the valid sense amplifier selection signal is the internal data signal line 610 connected to the input / output circuit.
Information of the selected memory cell is output, or information of the internal data signal line 610 is written to the selected memory cell. The sense amplifier not selected by the column decoder 609 and the selected sense amplifier when outputting the memory cell information to the internal data signal 610 are connected to the same memory cell row in order to retain the reached memory cell row information. Write back to. External data signal Dn611
CA is transmitted to the sense amplifier 606 via the input circuit 612 or is transmitted from the sense amplifier 606 to the external data signal line Dn611 via the output circuit 613.
It is determined by the control circuit 616 which receives the S signal 608 and the R / W signal 615.

The input circuit 612 is an external data signal 61 when the input circuit control signal 617 of the control circuit 616 falls.
Latch 1 and output as internal data signal 610. The control circuit 616 controls the R / W at the falling edge of the CAS signal 608.
When the signal 615 is L, it means a write operation, so the input circuit control signal 617 is made to fall at the time of the fall of the CAS signal 608, the external data signal 611 is latched by the input circuit 612, and the sense amplifier array 606 is made through the internal data signal 610. When the R / W signal 615 at the fall of the CAS signal 608 is H, it is a read operation. Therefore, the state of the internal data signal 610 is changed to the external data signal 611 via the output circuit 613 while the CAS signal 608 is L. To output.

Similarly, the control circuit 616 controls whether the CAS signal 608 falls or when the CAS signal 608 is L level.
If the R / W signal 615 is L at the falling edge of the RAS signal 603, the input circuit control signal 617 is dropped and the external data signal 611 is dropped.
The state of is latched by the input circuit 612 and the internal data signal 61
Output to the sense amplifier array 606 via
If the R / W signal 615 is H at the falling edge of the S signal 608 or at the falling edge of the RAS signal 603 while the CAS signal 608 is L, the internal data signal 610 status is C
While the AS signal 608 is L, the output control signal 619 is set to L and the state of the internal data signal 610 is output to the external data signal 611 via the output circuit 613.

With the above circuit configuration, a memory cell array
The cell information of 605 can be read or changed (ie, written). The details of the structure and configuration of the memory cell array 605, the write-back of memory cell information by the sense amplifier array 606, the connection with the internal data signal 610, and the like are described in DRAM ADRM.
It is known as a PX circuit and will not be described in detail.

FIG. 11 shows an ADRMPX circuit 600 according to this embodiment.
6 is a circuit diagram showing a control circuit 616 of FIG. In the figure, reference numeral 603 is a RAS signal, reference numeral 608 is a CAS signal, reference numeral
615 indicates R / W signals respectively, and reference numerals 804 and 805
Reference numeral 807 denotes a 2-input OR gate, and reference numeral 806 denotes an inverting gate. Reference numeral 808 denotes an input latch signal (hereinafter
Din-N), the input circuit 612 latches the external data signal 611 at the time of its fall. Reference numeral 809 is an output enable signal (hereinafter referred to as Dout Enable-N), and the output circuit 613 outputs the internal data signal 610 to the external data signal 611 while the signal level is L. Din −N signal 808 is RA
OR gate 80 with S signal 603 and CAS signal 608 as input
OR gate 805 with 4 outputs and R / W signal 615 as input
Since it is the output of RAS signal 603, CAS signal 608 and R / W signal
It becomes L only when 615 is all L.

FIG. 12 is a time chart showing the operation of the embodiment. In FIG. 12, the data 1 (408
) Corresponding to the falling edge of RAS signal 603, the address input A5-A0 indicates Y / 64 + 2 and CAS signal 60
The value indicated by the address inputs A5-A0 synchronized with the falling edge 106 of 8 is 2. RAS signal 603 for data 2 (4 09)
The value indicated by the address inputs A5-A0 synchronized with the falling edge 108 of
Y / 64 + 3, the column address is the falling edge of CAS signal 608 106
Since the value 2 latched at is sufficient, there is no change in the CAS signal 608 corresponding to data 2. Also data 3 (410)
In contrast, the value indicated by the address inputs A5-A0 synchronized with the trailing edge 110 of the RAS signal 603 indicates Y / 64 + 4, and the CAS signal 608 does not change as in the case of data 2 (409).

The control circuit 616 follows the R / W signal
When the CAS signal 608 falls, the input circuit 612 latches the external data signal 611, but the control circuit 616 causes
Since the RAS signal 603 is input, the external data signal 611 can be output to the sense amplifier array 606 via the internal data signal 610 at the falling edges 108 and 110 of the RAS signal 603.

Therefore, the falling edge 106 of the CAS signal 608 and the falling edges 108 and 11 of the RAS signal 603 shown in FIG.
At time 0, the input latch signal Din-N 808 shown in FIG. 11 changes from H to L and falls. Dout Enable-N signal 80
Since 9 is the output of the logical sum gate 807 which inputs the inversion signal of the CAS signal 608 and the R / W signal 615, the R / W signal 615 is high.
L when the CAS signal 608 is L. With the above description, the necessary functions of the control circuit 616 can be realized.

FIG. 13 is an explanatory diagram showing the DRAM, and shows an example in which the width of the image buffer is smaller than the number of column addresses of the DRAM. In the figure, the number of DRAM column addresses is W
Shown in DRAM, and 900 is the location of the image buffer in DRAM. That is, the address of the storage location 902 of the last or rightmost data of a certain line 901 and the address of the storage location 903 of the first or leftmost data of the next line are not consecutive, and the address for storing the leading data of each line must be Number of DRAM column addresses WDRAM90
It is a multiple of 1. By doing so, the ADRM shown in FIG.
With the time chart similar to that shown in FIG. 12, the PX circuit 600 can store vertically continuous data as a print result.
WB is the width of the image buffer 900, which is 64 as in FIG.
It is a byte. In this case, the memory area group 906 not used for the image buffer can be used for another image buffer or as a working area for storing other temporary state variables.

[0025]

As described above in detail, according to the present invention, when updating the contents of the addresses in the same column of the data storage unit, the control circuit causes the row address latch signal when the column address latch signal is at the low level. Since the external data signal is latched and fetched into the internal data signal at the falling edge of the signal, at the falling edge of the row address latch signal, the row address data synchronized with the row address latch signal and the column address data synchronized with the column address latch signal are stored. Are captured at the same time, and the capture time can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a multiplex circuit of a DRAM of an embodiment.

FIG. 2 is an explanatory diagram showing a conventional image buffer storage state.

FIG. 3 is an explanatory diagram showing a memory area.

FIG. 4 is an explanatory diagram showing addresses and contents.

FIG. 5 is a partially enlarged view of the image buffer.

FIG. 6 is an explanatory diagram showing a memory that stores font data.

FIG. 7 is an explanatory diagram showing an input / output state of a DRAM.

FIG. 8 is a time chart showing the operation of the DRAM.

FIG. 9 is an explanatory diagram showing a configuration example of an image buffer.

FIG. 10 is a time chart showing a change in input of a DRAM.

FIG. 11 is a circuit diagram showing a control circuit of the embodiment.

FIG. 12 is a time chart showing the operation of the embodiment.

FIG. 13 is an explanatory diagram showing a DRAM.

[Explanation of symbols]

 600 Address multiplex circuit 603 RAS signal 605 Memory cell array 608 CAS signal 615 R / W signal 616 Control circuit

Claims (1)

[Claims] 1. A dynamic RAM control circuit for fetching an external data signal into a dynamic RAM by means of a row address latch signal and a column address latch signal, when updating the contents of addresses in the same column direction of a data storage unit, the row address latch When the signal is low level, the external data signal is taken in at the falling edge of the column address latch signal, and when the column address latch signal is low level, the external data signal is latched and the internal data signal is latched at the falling edge of the row address latch signal. A control circuit for a dynamic RAM, which is provided with a control circuit for taking in.