JPH0831992B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a solid-state imaging device capable of reducing a parasitic capacitance of a video line and a chip size.

[Conventional technology]

Conventionally, as a solid-state image pickup device, one using a MOS transistor or one using a charge coupled device such as CCD or BBD is generally used. However, the one using a MOS transistor has a weak output signal, a poor signal-to-noise ratio, and a low photosensitivity.
Those using BBD etc. have a charge loss during charge transfer,
There are drawbacks such as difficulty in manufacturing. In order to solve these drawbacks, for example, as disclosed in Japanese Unexamined Patent Publication No. 58-105672, an electrostatic induction transistor (St
atic Induction Transistor; hereinafter referred to as SIT. ) Has been proposed.

Further, the present inventors have proposed various solid-state imaging devices that improve the invention of the above-mentioned application, and one configuration example among them is described based on FIGS. 6 (A) and 6 (B).

FIG. 6 (A) is a structural diagram of one pixel forming the solid-state imaging device by SIT, and FIG. 6 (B) is a circuit configuration diagram of the solid-state imaging device.

In FIG. 6 (A), an n ^- epitaxial layer 2 serving as a channel region is deposited on an n ⁺ silicon substrate 1 which acts as a drain of SIT. A shallow n ⁺ source region 3 is formed in the epitaxial layer 2, and the source region 3 is surrounded by the p ⁺ gate region 4 in the epitaxial layer 2. A MOS capacitor 5 is formed on the gate region 4, and a pulse is supplied via this capacitor 5. When the gate region 4 is reverse biased, a depletion layer is formed outside the gate region 4. When light is incident on the depletion layer and a hole-electron pair is generated, the electron is generated in the source 3 and the drain region 1.
And holes are accumulated in the gate region 4. Therefore, the gate potential rises, the current between the drain and the source is modulated by the voltage change, and an amplified signal is obtained depending on the light. In addition, 6 in FIG. 6 (A) is a separation area for separating each pixel.

In Fig. 6 (B), 10-11, 10-12, ... 10-21, 10
-22, ‥‥‥‥‥‥‥‥‥‥‥, 10-44 are SITs that constitute pixels each having the structure shown in FIG. 6 (A). It shows a column in which SITs are arranged vertically and horizontally in 4 rows and 4 columns. SI arranged vertically
The sources of T are commonly connected to the column lines 11-1, 11-2, ... 11-4, and the gates of the SITs arranged horizontally are connected to the row lines 12-1 via capacitors. , 12-2, ‥‥‥‥‥ 12-4
Respectively connected to.

Column lines 11-1, 11-2, ... 11-4 are drive transistors 17-1, 17-2, which are MOS transistors, ... 1
The sources of these drive transistors are connected to the gates of 7-4, and the sources of these drive transistors are transistors 13-1, 13-2, ...
Connected to video line 14 via. On the other hand, the drains of the drive transistors are commonly connected to the power supply V _DD . The video line 14 is grounded via a video line reset transistor 19, and a video line reset pulse φ _RV is applied to the gate of the transistor 19. The gates of the transistors 13-1, 13-2, ..., 13-4 for the horizontal selection switch are connected to the horizontal scanning circuit 15, and horizontal scanning pulses φ _S1 , φ _S2 , ... are connected to the respective gates. .................. φ _S4 is applied.

The row lines 12-1, 12-2, ... 12-4 are connected to the vertical scanning circuit 16, and the vertical scanning pulses φ _G1 , φ _G2 , ... φ _G4 are connected to these row lines. Is applied. Column line 11-
1, 11-2, ... 11-4 The drive transistor 17-
1, 17-2, ..... The ends on the side opposite to the side connected to 17-4 are the column line reset transistors 18-1, 18-2,
It is grounded via 18-4, and a column line reset pulse φ _R is commonly applied to each gate of these column line reset transistors.

And the SIT that constitutes the pixel 10-11, 10-12, ‥‥‥‥‥‥ 10-44
All drains of the silicon substrate 1 [Fig. 6 (A)]
And the drains are commonly connected to the power supply V _D.

FIG. 7 is a signal waveform diagram showing the timing of each pulse for operating the solid-state imaging device, and FIG. 8 is a circuit configuration diagram when focusing on one pixel SIT in the area sensor of the device. .

In FIG. 7, vertical scanning (gate selection) pulses φ _G1 , φ _G2 , ... Are pulses having two kinds of high levels V _RD and V _RS , and during the horizontal scanning period t _H of each line. It takes the value of the read level V _RD and becomes the reset level V _RS during the subsequent horizontal blanking period t _BL . The horizontal scanning (source selection) pulses φ _S1 , φ _S2 , ... Become high level in each horizontal scanning period and sequentially scan pixels arranged in a row. The reset pulse φ _R is a pulse that becomes a high level in each horizontal blanking period, and resets the pixel from which the signal is read.

In FIG. 8, C _GD is a gate-drain parasitic capacitance, C _GS is a gate-source parasitic capacitance, C _S is a source line floating capacitance, and R _ON is a horizontal selection MOS transistor.
The on resistance of T _S , C _V is the parasitic capacitance of the video line.

FIG. 9 shows the time of the gate potential V _G and the source potential V _S of the pixel SIT when the horizontal scanning pulse φ _S , the vertical scanning pulse φ _G , and the reset pulse φ _R are applied to the pixel SIT in the solid-state imaging device. This is a change in the economy. Note that φ
_B is a built-in voltage between the gate and the source which will be described later.

FIG. 10 is a diagram showing temporal changes in the gate potential V _G , the source potential V _S , and the video line potential V _V of the pixel SIT when the horizontal selection pulse φ _S becomes high level.

Next, referring to FIGS. 7 to 10, the manner in which the signal corresponding to the light incident thereon is read out from the pixel SIT will be sequentially described.

(1) When φ _G = V _RS (> φ _B ) and φ _R become high level at time t ₁ , the source potential V _S is reset to GND, and V _G = φ _B.

(2) When the pulses φ _G and φ _R become low level (GND) at time t ₂ , the gate potential V _G2 becomes the reverse bias state given by the following equation (1), and optical integration is started.

Here, C _J = C _GS + C _GD (3) At time t ₃ , this time is the light integration time, and the charge Q _ph generated by irradiation of light is accumulated in the gate capacitance (C _G + C _J ). It The above Q _ph is given by the following equation.

Q _ph = G _L · A · P · t _int = G _L · A · E (2) where G _L is the production rate (μA / μW), A is the light-receiving surface area (cm ² ), P is the irradiance of light (μW / cm ² ), t _int is the integration time (S), and E is the exposure dose (E = P · t _int ). Time t ₃
The gate voltage V _{G3 in} is expressed by the following equation (3) from the above equations (1) and (2).

(4) At time t ₄ , when φ _G = V _RD , the gate potential V _G4 becomes Becomes If V _G4 > V _P (here, V _P is the gate-source potential difference at which the drain current of the pixel SIT begins to flow and is called the pinch-off voltage), the drain current of the pixel SIT flows and the source line capacitance C _S To charge. This charging continues until the gate-source potential difference V _GS becomes V _P. Therefore, the source potential is given by the following equation.

Since V _P <φ _B , almost no current flows from the p ⁺ gate to the n ⁺ source of the pixel SIT.

(5) At time t ₅ , the line selection transistor T _S turns on and this on resistance R _ON
The potential V _S of the source line is amplified by the source follower amplifier composed of the load resistance R _L and the drive MOS transistor T _D. When the amplification factor of the source follower amplifier is a, the output V _OUT is given by the following equation.

In FIG. 10, when the horizontal selection pulse φ _S becomes high level, the driving transistor T _D starts charging the parasitic capacitance C _V of the video line, and after Δt time, the potential V _{V of the} video line is changed to the above (6 ) Is expressed as V _OUT . When the horizontal selection pulse φ _S falls to the GND level, the electric charge C _V · V _OUT accumulated in the parasitic capacitance of the video line starts discharging via the load resistance R _L.

(6) When the video line reset MOS transistor T _RV is turned on at time t ₆ , the residual charge in the parasitic capacitance C _V of the video line is
Discharges through the MOS transistor T _RV, the potential V _V video line becomes GND level.

As described above, the optical signal output of one pixel is read. In addition, the vertical scanning circuit 16 and the horizontal scanning circuit 15 sequentially output vertical scanning pulses φ _G1 , φ _G2 ,.
Select 1,12-2, ..., Horizontal scan pulse φ _S1 ,
By sequentially selecting the column lines 11-1, 11-2, ... for φ _S2 , ..., each pixel is sequentially selected, and a signal for one screen is obtained.

[Problems to be solved by the invention]

As can be seen from the equation (6), the solid-state imaging device described above can obtain a considerably large output as compared with the conventional MOS image sensor. However, if the number of horizontal pixels is increased for the purpose of improving the horizontal resolution, the parasitic capacitance of the video line increases with the number of horizontal selection transistors. Therefore, after the horizontal selection pulse φ _S is applied, the pixel signal V The delay time Δt until _OUT appears becomes large, and there is a possibility that a desired pixel signal cannot be obtained.

That is, the horizontal selection transistor shown in FIG.
13 ON resistances R _ON , parasitic capacitance C _VS connected to the video line per horizontal selection transistor, and horizontal pixel number N
_{Assuming h} , the resulting time constant is N _h · C _VS · R _ON . On the other hand, assuming that the image signal is reproduced by the current television system, if the horizontal scanning period is 53 μs, the time during which one pixel is selected is 53 μs / N _h considering the time for resetting the video line. Shorter. Further, in order for the rectangular wave to rise, it is generally necessary to have three times the time constant of the transmission line, so the following condition is not satisfied in order to obtain the output V _OUT determined by the equation (6) on the video line. Don't

3 · N _h · C _VS · R _ON <53 μs / N _h ······································ (7) Therefore, if an image pickup device with the number of horizontal pixels N _h = 1000 is to be realized by the configuration of the conventional example, the following conditions are satisfied. You have to meet.

Assuming that the parasitic capacitance C _VS of the horizontal selection transistor is composed only of the junction capacitance of the drain terminal of the transistor, the drain width of the transistor is 1.5 (μm), the gate width is W (μm), and the unit area of the drain is If the junction capacity per unit is 4 × 10 ^-16 [F / μm ² ], C _VS = 1.5 × W × 4 × 10 ^-16 = 6 × 10 ^-16 × W [F] ‥‥‥‥‥‥‥‥ (9) , ON resistance per channel width 1 [μm] is R ′
_{When set to ON} , R _ON = R ′ _ON / W ‥‥‥ (10) Substituting the values of equations (9) and (10) into equation (8), R ′ _ON <3 × 10 ³ ‥‥‥‥‥ It becomes (11). Equation (11) is the on resistance of the horizontal selection transistor.
R _ON means that it must be less than 3 [kΩ] per 1 [μm] of channel width.

On the other hand, the channel conductance g _sd in the triode region of the MOS transistor is expressed by the following equation (12), and the on-resistance is the reciprocal thereof.

Here, μ _O is mobility, ε _OX is SiO ₂ dielectric constant, ε _O is dielectric constant, T _OX is gate oxide film thickness, W is channel width, L
Is the channel length.

Now, the channel conductance g _sd of an N-channel MOS transistor having a channel length of 1.5 μm will be calculated. (1
In equation (1), μ _O = 700 [cm ² / V ・ sec], T _OX = 400 [Å], L =
1.5 [μm], V _G = 8 [V], V _T = 0.5 [V], V _P = 5
Substituting [V] gives g _sd 1 × 10 ⁻⁴ [mho] ∴R _ON = 1 / g _sd 10 [kΩ].

From the above, in order to realize the image pickup device with the number of horizontal pixels N _h = 1000 by the configuration of the conventional example, at least the parasitic capacitance of the video line is required when one horizontal selection transistor is provided for each column line. It turns out that it needs to be 3/10 or less.

When the number of horizontal pixels is increased, a problem in the image pickup apparatus of the conventional example is the reduction of the pitch per scanning circuit due to the reduction of the pixel pitch. For example the horizontal pixel pitch in the horizontal pixel number N _h = 1000, corresponding to 2/3 inch lens system 8.
8 [μm]. The horizontal pixel pitch is 6.4 [μm] for 1/2 inch lens system with the same number of horizontal pixels.
Is. The pitch per stage of the horizontal scanning circuit must be the same as these pixel pitches, which is quite difficult to achieve with current device and circuit technology.

The present invention has been made in order to solve the above two problems in the conventional solid-state image pickup device. Even if the number of horizontal pixels is increased, the video line parasitic capacitance does not increase, and the pitch per stage of the horizontal scanning circuit is increased. It is an object of the present invention to provide a solid-state imaging device capable of performing horizontal pixel scanning without reducing the number of pixels.

[Means and Actions for Solving Problems]

In order to solve the above problems, the present invention provides a solid-state imaging device arranged in a matrix, a plurality of row lines and column lines respectively connected to the solid-state imaging device, and a video for reading an optical signal of the solid-state imaging device. In a solid-state imaging device including a line, a first horizontal selection transistor arranged corresponding to each column line, and a plurality of the first horizontal selection transistors arranged so as to be commonly connected. And a second horizontal selection transistor, and each column line potential is selectively switched to the video line by the first and second horizontal selection transistors and transmitted.

Next, the basic circuit configuration of the horizontal scanning section of the solid-state imaging device having the above-described configuration according to the present invention will be described with reference to FIG. First
In the figure, 24-1, 24-2, ... 24-mn represent the source terminals of the horizontal selection transistors 13-1, 13-2, ... 13-mn, and are shown in FIG. Connect to the source terminals of the column (source) lines 11-1, 11-2 ... or drive transistors 17-1, 17-2, ... in the conventional solid-state imaging device shown in (B). It shows the part to be done. The horizontal selection transistors 13-1, 13-2, ..., 13-mn have the same number of drain terminals n each, and main horizontal selection transistors 20-1, 20-2 ,. Is connected to each source terminal. Further, the main horizontal selection transistors 20-1, 20-2 ,.
20-m drain terminals are commonly connected to the video line 14. A reset transistor 19 is connected to the video line 14, and a reset pulse φ _RV is applied to its gate.

Each gate of the main horizontal selection transistors 20-1, 20-2, ... 20-m has a first horizontal scanning circuit 15 having m scanning stages.
Connected to the first horizontal scanning pulse φ _S1 ,
φ _S2 , ... φ _Sm can be added. Further, the gates of the horizontal selection transistors 13-1, 13-2, ... 13-mn are commonly used every nth, and the horizontal scanning line 21 is connected to the second horizontal scanning circuit 23 having n scanning stages. -1,21-2,
_.. are connected by 21-n so that the second horizontal scanning pulses φ _SS1 , φ _SS2 ,.

And, in the above-mentioned configuration, while the main horizontal selection transistors 20-1, 20-2, ... 20-m are ON, the respective main horizontal selection transistors 20-1, 20-2, ... 20
-horizontal selection transistors 13-1, 13-2, connected to m
The first horizontal scan pulse φ _S1 , φ _S2 , ... φ _Sm and the second horizontal scan pulse φ so that 13-mn is turned on sequentially.
By applying _SS1 , φ _SS2 , _... φ _SSm ,
Horizontal scanning can be realized with the number of horizontal selection switch transistors connected to the video line 14 being only 1 / n of the number of pixels. This makes it possible to reduce the parasitic capacitance parasitic on the video line and increase the output terminal pitch of the horizontal scanning circuit.

In this basic configuration, the main horizontal selection transistors 20-1, 20-2, ... 20-m and the horizontal selection transistors 13-
Reference numerals 1, 13-2, ..., 13-mn represent sources and drains connected in series, but a drive transistor can be arranged between the selection transistors if desired.

〔Example〕

Examples will be described below. FIG. 2 is a circuit configuration diagram showing a first embodiment of the solid-state imaging device according to the present invention,
FIG. 3 is a diagram showing the timing of pulses applied to each element that constitutes the horizontal scanning circuit of the solid-state imaging device shown in FIG.

In FIG. 2, the same or equivalent constituent members as those of the conventional solid-state imaging device shown in FIG. 6B are designated by the same reference numerals. Note that the structure of the SIT that constitutes each pixel in this embodiment is exactly the same as that shown in FIG. 6A, and in this embodiment, the SIT that constitutes the pixel is 4 An example is shown in which the matrix is arranged in a matrix of 8 rows and 8 columns. The pulse signal waveform applied to the source or gate of each SIT that constitutes a pixel is exactly the same as that shown in FIG.

In FIG. 2, each pixel SIT10-11,10-12, ... 10-21,10-2 having the same structure as that shown in FIG. 6 (A)
2, ... 10-48 are arranged vertically and horizontally in a matrix form, and each source of the vertically arranged SIT is a column line 11-1, 11-
2, SIT connected in common to 11-8 and arranged horizontally
The gates of the row lines 12-1, 12-2, ...
It is connected to 12-4 respectively. The column line 11-
1, 11-2, ... 11-8 are connected to the respective gates of the drive transistors 17-1, 17-2, ... 17-8, which are MOS transistors, and these drive transistors are connected.
The sources of 17-1, 17-2, ... 17-8 are connected to the drains of the transistors 13-1, 13-2, ... 13-8, which constitute the horizontal selection switch, respectively. .

Transistors for horizontal selection switch 13-1, 13-2, ...
............ 13-8 connect two sources of the horizontal selection transistors belonging to adjacent column lines in common,
Further, these common connection terminals are connected to the video line 14 through the main horizontal selection transistors 20-1, 20-2, ... 20-4. The video line 14 is grounded via a video line reset transistor 19, and a video line reset pulse φ _RV is applied to the gate of the transistor 19.

Transistors for horizontal selection switch 13-1, 13-2, ...
The drains of 13-8 are commonly connected to the power supply V _DD through the drive transistors 17-1, 17-2, 17-8, respectively, and these horizontal selection switch transistors 13-
The gates of 1, 13-2, ..., 13-8 are commonly connected to the second horizontal scanning circuit 23 every other gate, and the second horizontal scanning pulses φ _SS1 and φ _SS2 are applied thereto, respectively. . The gates of the main horizontal selection switch transistors 20-1, 20-2, ..., 20-4 are connected to the first horizontal scanning circuit 15, and the first horizontal scanning pulses φ _S1 , φ _S2 , ...・ ・ ・ Φ _S4 is applied.

The row lines 12-1, ... 12-4 are connected to the vertical scanning circuit 16, and the vertical scan pulses φ _G1 , φ _G2 , ... are provided in the row lines 12-1, ... 12-4. ... φ _G4 is applied. The ends of the column lines 11-1, 11-2, ... 11-8 opposite to the side connected to the drive transistors 17-1, 17-2, ... 17-8 are , Column line reset transistors 18-1, 18-2, ... 18-8, which are respectively grounded, and the column line reset transistors 18-1, 18-2, ... 18-8
A column line reset pulse φ _R is commonly applied to the respective gates.

All of the drains of SITs 10-11, 10-12, ..., 10-48 that compose the pixel are all formed on the silicon substrate 1 [see Fig. 6 (A)].
Are formed by the
Commonly connected to V _D.

In this embodiment, vertical scanning pulses φ _G1 , φ _G2 , ...
Φ _G4 is applied to the row lines 12-1, 12-2, ... 12-4, and the selected pixel SIT is applied to the column lines 11-1, 11-2, ... 11-8. Source potential V according to the amount of charge accumulated in the gate of
The operation until _S appears is the same as that of the conventional example shown in FIGS. 6 (A) and 6 (B).

Next, in FIG. 2, a vertical pulse φ is applied to the row line 12-1.
_{After G1} is applied and the potential of the row line 12-1 reaches the read level V _RD , description will be made thereafter. When the row line 12-1 becomes the potential V _RD , the pixels SIT10-11, 10-12,
‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ 18-18
In 1-8, the source potential corresponding to the charges accumulated in the gates of the pixels SIT10-11, 10-12 ,.

As shown in FIG. 3, when the first horizontal scanning pulse φ _S1 becomes high level at time t ₁ ′, the main horizontal selection transistor 20-1 is turned on. Simultaneously with this or at a time t ₂ ′ slightly delayed, the second horizontal scanning pulse φ _SS1 becomes high level, and the horizontal selection transistor 13-1 is turned on. At this time, the source follower amplifier composed of the ON resistance of the drive transistor 17-1, the horizontal selection transistor 13-1, the ON resistance of the main horizontal selection transistor 20-1, and the load resistance _RL operates, and FIG. Similar to the conventional example shown in FIG. 6B, the potential of the column line 11-1 is amplified by the source follower amplifier, and its output appears on the video line 14.

At time t ₃ ′, the second horizontal scanning pulse φ _SS1 becomes low level, and the horizontal selection transistor 13-1 is turned off. At this time, the driving transistor 17-1 is disconnected from the video line 14, and thus the source follower amplifier stops operating. At the same time as or at a time t ₄ ′ slightly delayed, the video line reset transistor 19 is turned on by the video line reset pulse φ _RV applied to its gate,
The electric charges remaining in the source and drain of 14 and the main horizontal selection transistor 20-1 are discharged, and the video line reset transistor is turned off at time t ₅ ′.

Next, at the same time as the time t ₅ ′ or at a time t ₆ ′ slightly delayed, the horizontal selection transistor 13-2 is turned on by the second horizontal scanning pulse φ _SS2 , which causes the drive transistor 17-2 and the horizontal selection transistor 13-. 2 ON resistance and ON resistance and load resistance of main horizontal select transistor 20-1
The source follower amplifier composed of R _L operates, and the potential of the column line 11-2 is amplified by the source follower amplifier as in the conventional example shown in FIG. Appear in.

Next, at time t ₇ ′, the second horizontal scanning pulse φ _SS2
Becomes low level and the horizontal select transistor 13-2 is turned off, so that the source follower amplifier stops operating. At the same time as or slightly later than this time t ₈ ′
At the video line reset transistor 19 has a video line reset pulse φ _RV applied to its gate.
Is turned on again to discharge the electric charge remaining in the source / drain of the video line 14 and the main horizontal selection transistor 20-1, and the video line reset transistor 19 is turned off at time t ₉ ′. The first horizontal selection pulse φ _S1 becomes low level at t ₈ ″ during this time t ₈ ′ to t ₉ ′, and the main horizontal selection transistor 20-1 is turned off. Simultaneously with or after a short delay, the first horizontal scanning is started. The pulse φ _S2 goes high.

Similarly, the second horizontal scanning circuit 23 outputs the second horizontal scanning pulses φ _SS1 and φ _SS2 , whereby the horizontal selection transistors 13-3 and 13-4 are sequentially selected, and the column line 1
The potentials 1-3 and 11-4 are sequentially amplified and output to the video line 14.

Thus, the second horizontal scanning circuit 23 outputs the second horizontal scanning pulses φ _SS1 and φ _SS2 to sequentially select the horizontal selection transistors 13-1, 13-2, ... 13-8, and First
The horizontal scanning circuit 15 uses the first horizontal scanning pulse φ _S1 , φ _S2 , ...
The main horizontal selection transistors 20-1, 20-2, 20-4 are sequentially selected by scanning and outputting φ _S4 .
By the above operation, horizontal pixels are sequentially selected, and all the pixels connected to the row line 12-1 SIT10-11, 10-12, ... 10-
18 signals are output to the video line 14. Also line line
12-1, 12-2, ... 12-4 are selected by the vertical scanning circuit 16 by the vertical scanning pulse φ _G1 , as in the conventional solid-state imaging device.
phi _G2, performed by sequentially scanning the ‥‥‥‥ φ _G4,
Combined with the horizontal pixel selection operation described above, all pixel signals for one screen can be obtained.

In this embodiment, the horizontal pixel selection operation is performed by the horizontal selection switch transistors 13-1, 13-2, ... 13-8 and the main horizontal selection switch transistors 20-1, 20-2, .... 20-4
And with. Therefore, drive transistor 17-
The resistance component that exists when 17-8 charges the parasitic capacitance of the video line 14 is the sum of the ON resistances of these two horizontal selection transistors. However, the size of the on resistance of the horizontal selection transistors 13-1, 13-2, ... 13-8 can be freely selected in the circuit because its parasitic capacitance is not directly connected to the video line 14. Therefore, the resistance component existing when the parasitic capacitance is charged is the ON resistance of the horizontal selection transistor when one horizontal selection transistor is arranged in one column line and horizontal pixel selection is performed, as shown in the conventional example. Does not reach twice the value.

On the other hand, the number of main horizontal selection transistors 20-1, 20-2, 20-4 connected to the video line 14 is 1 / the number of horizontal pixels.
[Number of horizontal selection transistors connected to the main horizontal selection transistor], that is, 1/2 in this embodiment, and the parasitic capacitance of the video line by the horizontal selection transistor is 1/2 compared to the conventional case.

Therefore, drive transistors 17-1, 17-2, ...
The time constant when 17-8 charges the video line 14 is reduced to close to 1/2 of that in the above-mentioned conventional example. Ie tenth
Even when Δt shown in the figure is reduced to nearly half that of the conventional one, and the number of horizontal pixels is increased, the pixel output shown by the equation (6) can be obtained.

Further, the pitch of the scanning stages of the first horizontal scanning circuit 15 may be [the number of horizontal selection transistors connected to the main horizontal selection transistor] times the horizontal pixel pitch, that is, twice, so that the number of horizontal pixels increases and the horizontal pixel pitch increases. However, even if the pixel size is significantly reduced, the pitch of the scanning stages of the first horizontal scanning circuit 15 is not significantly reduced, so that the pattern layout of the first horizontal scanning circuit 15 can be easily performed.

FIG. 4 is a circuit configuration diagram showing a second embodiment of the present invention. Elements having the same operations as those of the element in the first embodiment shown in FIG. The description is omitted. In the first embodiment, the horizontal selection transistor 13
-1,13-2, ... 13-8 is a drive transistor 17-1,1
7-2, ..., 17-8 was connected to the load side, that is, the side connected to the video line 14, but in the second embodiment,
As shown, horizontal selection transistors 13-1, 13-2, ...
13-8 are the drive transistors 17-1, 17-2, ...
It is connected to the power supply side of 17-8. Except for this difference, the circuit configuration of the second embodiment is exactly the same as the circuit configuration of the first embodiment. In terms of operation and effect, drive transistors 17-1, 17-2, ... 17-8 and horizontal selection transistors 13-1, 13-2, ... 13-8, main horizontal selection transistors 20-1, 20-2, ... 20-4 and the circuit of this embodiment except for the characteristic of the source follower amplifier composed of load resistance _RL. The operation and effect are exactly the same as those of the first embodiment.

FIG. 5 is a circuit configuration diagram showing a third embodiment of the present invention. Elements having the same operations as those of the element in the first embodiment shown in FIG. Is omitted. In the first embodiment, each column line 11-1, 11-
2, ... 11-8 drive transistors 17-
1, 17-2, ... 17-8 are provided, and their outputs are horizontal selection transistors 13-1, 13-2, ... 13-8 and horizontal selection transistors 20-1, 20-2, ... Although the circuit configuration is such that 20-4 is used to switch to the video line 14 for transmission, in the present embodiment, the potential of each column line 11-1, 11-2, 11-8 is set. Horizontal selection transistors 13-1, 13-2, ... 13-8
And the main horizontal selection transistors 20-1, 20-2, ... 20-4 to switch to the video line 14 for transmission, and further each column line 11-1, 11-2 transmitted to the video line 14 ‥‥‥‥
The potential of 11-8 is amplified by a source follower amplifier composed of a single drive transistor 17 connected to the end of the video line 14 and a load resistor R _L.

That is, in the first embodiment, the horizontal selection transistor
13-1, 13-2, ... 13-8 and main horizontal selection transistor 20
-1, 20-2, ..., 20-4 are adapted to switch the output of the column line potential sensing source follower amplifier to the video line 14, but in the present embodiment, the horizontal selection is performed. The transistors and the main horizontal selection transistors are configured to switch the input of the column line potential sensing source follower amplifier to the video line 14. The operation except this point is exactly the same as that of the first embodiment.

Further, in the case of this embodiment, it is the pixels SIT10-11, 10-12, ... 10-48 that serve as a power source for charging the video line 14, but in this case, the problem is the first embodiment. Similar to the example, the time constant is composed of the on resistance of the transistor for horizontal selection switch connected to the video line 14 and its parasitic capacitance. In the case of the present embodiment, this time constant is reduced to close to 1/2 as compared with the conventional solid-state image pickup device as in the case of the first embodiment. Therefore, the same effect as the first embodiment can be obtained. To be Further, in this embodiment, the gate of the drive transistor (MOS transistor) 17 is connected to the end of the video line 14, but the effect is the same even if any element is connected to the end of the video line 14. Absent.

In each of the three embodiments described above, the horizontal pixel SIT
The horizontal selection transistors 13-1, 13-2, ... 13-8 connected to the main horizontal selection transistors 20-1, 20-2, ... 20-4 2 and the number of output stages of the second horizontal scanning circuit are two. Of the source / drain terminals of the main horizontal selection transistor, the terminal capacitance not connected to the video line 14 is the video line parasitic capacitance. It can be set to any number as long as it does not increase in comparison.

Although the MOS transistor is used as the driving transistor, the SIT may be used, and the load resistor R _L may be a depletion type MOS transistor.

Furthermore, in each of the above embodiments, only the one using the electrostatic induction transistor as the pixel is shown. However, the present invention is a solid-state transistor which performs scanning of the pixel by the selection transistor connected to the scanning circuit regardless of the constituent elements of the pixel. It can be applied to all imaging devices.

〔The invention's effect〕

As described above based on the embodiments, according to the present invention, it is possible to reduce the parasitic capacitance parasitic on the video line and increase the output terminal pitch of the horizontal scanning circuit at the same time, so that the chip size can be reduced. Can be measured,
Alternatively, by increasing the number of horizontal pixels, it is possible to easily realize a solid-state imaging device compatible with higher resolution.

Further, the solid-state imaging device according to the present invention can be manufactured by using exactly the same process as that of the conventional one, and therefore, it is possible to obtain advantages such as difficulty in manufacturing and increase in cost.

[Brief description of drawings]

FIG. 1 is a basic circuit configuration diagram of a horizontal scanning unit which is a main part of a solid-state imaging device according to the present invention, FIG. 2 is a circuit configuration diagram of a first embodiment of the present invention, and FIG. FIG. 4 is a signal waveform diagram showing the timing of the pulse applied to each part of the horizontal scanning circuit shown in FIG. 4, FIG. 4 is a circuit diagram of the second embodiment of the present invention, and FIG. 5 is the third embodiment of the present invention. Circuit configuration diagram, FIG. 6A is a structural diagram of one pixel of a solid-state imaging device configured by a conventional SIT, and FIG. 6B is a circuit configuration diagram of the solid-state imaging device as a whole.
6 is a signal waveform diagram showing the timing of pulses for operating the solid-state imaging device shown in FIG. 6B, and FIG.
FIG. 9 is a circuit configuration diagram for one pixel of the solid-state image pickup device shown in FIG. 9B, and FIG. 9 shows applied pulse signals and SIT in FIG.
A diagram showing the relationship between the gate potential and the source potential of a pixel,
FIG. 10 is a diagram showing the relationship between the horizontal selection pulse, the gate potential and the source potential of the SIT pixel, and the video line potential in FIG. In the figure, 10-11, 10-12, ... are pixel SITs, 11-1, 11
-2, ... is a column line, 12-1, 12-2, ... is a row line, 13-1, 13-2, ... is a horizontal selection transistor, 14 is a video line, 15 is a 1st horizontal scanning circuit, 16 is a vertical scanning circuit, 17-1, 17-2, ... are drive transistors, 18
-1,18-2, ... is the column line reset transistor, 19
Is a video line reset transistor, 20-1, 20-2,
... is the main horizontal selection transistor, 21-1, 21-2, ... is the horizontal scanning line, 23 is the second horizontal scanning circuit, 24-1, 24-2, ...
Indicates the source terminal of the horizontal selection transistors 13-1, 13-2 ,.

Claims (3)

[Claims] 1. A solid-state imaging device comprising solid-state imaging devices arranged in a matrix, a plurality of row lines and column lines respectively connected to the solid-state imaging device, and a video line for reading an optical signal of the solid-state imaging device. In the device, a first horizontal selection transistor arranged corresponding to each column line, and a second horizontal selection transistor arranged so as to be commonly connected to a plurality of first horizontal selection transistors. And a configuration in which each column line potential is selectively switched and transmitted to a video line by the first and second horizontal selection transistors. 2. The solid-state image pickup device according to claim 1, wherein the first and second horizontal selection transistors are configured to select a column line by on / off control. . 3. A solid-state image pickup device according to claim 1, further comprising means for sequentially controlling ON / OFF of the first and second horizontal selection transistors.